CN103794554A - Improved preparation method of through silicon via structure - Google Patents
Improved preparation method of through silicon via structure Download PDFInfo
- Publication number
- CN103794554A CN103794554A CN201410069336.3A CN201410069336A CN103794554A CN 103794554 A CN103794554 A CN 103794554A CN 201410069336 A CN201410069336 A CN 201410069336A CN 103794554 A CN103794554 A CN 103794554A
- Authority
- CN
- China
- Prior art keywords
- substrate
- deep hole
- silicon via
- via structure
- improved
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to an improved preparation method of a through silicon via structure. The improved preparation method comprises the following steps of a, providing a substrate and etching the inside of the substrate to form the required deep hole; b, performing oxygen plasma oxidation or oxygen plasma anodic oxidation in the deep hole under the oxygen plasma environment to form an oxidation layer on the inner wall of the deep hole, wherein the temperature of the substrate during oxidation of oxygen plasmas is 200 DEG C -600 DEG C; c, performing deposition in the deep hole with the oxidation layer to obtain a blocking layer and a seed layer, wherein the blocking layer is positioned between the seed layer and the oxidation layer; d, filling the deep hole with metal conductors, wherein the deep hole is filled with the metal conductors and the blocking layer wraps the metal conductors; e, thinning the back surface of the substrate to form the required through hole structure. The improved preparation method is simple in processing step, capable of reducing leak current forming the through silicon via (TSV) structure and stray capacitance and improving reliability, and wide in application range.
Description
Technical field
The present invention relates to a kind of process, especially a kind of improved through-silicon via structure preparation method, belongs to the technical field of semiconductor technology.
Background technology
Along with concentrating of chip functions and reducing of size, there is wide commercial application prospect take silicon through hole (TSV) structure as basic 2.5D/3D encapsulation technology.In TSV structure, between silicon base and copper, insulating barrier is most important to effective transmission of the TSV signal of telecommunication, and the main method that adopts the long-pending silicon oxide film of TSV inner hole deposition realizes electric insulation at present, forms metal/insulator/semiconductor (MIS) structure of Cu/SiOx/Si.In MIS structure, storeroom interface topography has very large impact to parasitic capacitance, leakage current and reliability.But, at present main flow Bosch technique (Bosch) is prepared TSV sidewall in the process of TSV structure and is unavoidably had conchoidal side wall construction, described shelly side wall construction causes parasitic capacitance and the leakage current of the MIS structure of TSV formation to increase, and accelerates component failure.
At present, in TSV structure preparation technology, the preparation method of insulating layer of silicon oxide, take chemical gaseous phase preparation method as main, mainly contains the methods such as chemical vapor deposition (CVD), ald (ALD) and thermal oxidation.
Chemical vapour deposition (CVD) and atom layer deposition process refer to that the chemical reaction by source gas covers one deck silicon oxide film in TSV hole inner wall surface deposition, and silicon base surface in this deposition process (hole inner wall surface) conchoidal sidewall pattern remains unchanged.The shortcoming of these two kinds of processes is in silica deposition process, still to have kept Bosch technique to prepare the conchoidal side wall construction forming in TSV process, and therefore electric leakage, the parasitic capacitance of the TSV structure of final preparation are larger, have reduced reliability of structure.
The method of thermal oxidation refers to carries out TSV structure high-temperature heat treatment under the environment of oxygen, generates one deck insulating layer of silicon oxide structure by the chemical reaction between oxygen and silicon.In this technological reaction process, can consume the part silicon of TSV internal surface of hole, and due to the diffusion of oxygen atom in silicon and silica body, the final silica/silicon interface roughness forming is improved greatly with respect to the former conchoidal sidewall in TSV hole.Illustrate that in the MIS structure that hot oxygen insulating barrier preparation technology forms than the TSV of CVD or ALD insulating barrier preparation technology assembling, the electrode surface roughness of semiconductor silicon one side is little, thereby leakage current and parasitic capacitance are little, reliability is improved.But that the disadvantage of thermal oxidation technology is technological temperature is higher, be only applicable at present first hole (via first) technique and keyset (interposer) technique, the requirement of boring (via middle) technique and rear boring (via last) technique in the middle of cannot meeting.
Therefore,, in TSV structure preparation technology, silica/silicon interface optimization new technology that exploitation is suitable for cryogenic conditions has very important significance.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of improved silicon through hole preparation method is provided, its processing step is simple, can reduce the leakage current and the parasitic capacitance that form TSV structure, improves reliability, wide accommodation.
According to technical scheme provided by the invention, a kind of improved through-silicon via structure preparation method, described through-silicon via structure preparation method comprises the steps:
A, provide substrate, described substrate comprises front and the back side corresponding with described front, and in substrate, etching forms required deep hole, and described deep hole extends from the direction at the sensing back side, front of substrate;
B, the oxygen plasma carrying out in described deep hole under oxygen plasma environment are oxidized or oxygen plasma anodic oxidation, and to form oxide layer on the inwall of deep hole, in described oxygen plasma oxidizing process, the temperature of substrate is 200 ℃ ~ 600 ℃;
C, in the deep hole with oxide layer deposition obtain barrier layer and Seed Layer, described barrier layer is between Seed Layer and oxide layer;
D, in above-mentioned deep hole, carry out metallic conductor filling, described metallic conductor is filled in deep hole, and barrier layer is wrapped in the outer ring of metallic conductor;
E, attenuate is carried out in the back side of substrate, to form required through-hole structure.
Described substrate is silicon substrate, and the degree of depth of deep hole in substrate is less than the thickness of substrate.Described substrate utilizes photoresist or hard template to carry out etching as mask, to obtain deep hole.
Described substrate utilizes photoresist etching to obtain after deep hole, removes the photoresist in substrate front side, and substrate and deep hole are cleaned.
Described substrate utilizes hard template etching to obtain after deep hole, and substrate and deep hole are cleaned.The thickness of described oxide layer is 0.1 μ m ~ 2 μ m.
In described steps d, metallic conductor is filled in after deep hole, utilizes CMP technique to carry out planarization to the front of substrate.
The material of described metallic conductor comprises copper.Described metallic conductor is filled in deep hole by plating mode.
Described hard template adopts silicon nitride layer.
Advantage of the present invention: using plasma oxidation technology or plasma anodization technology, under low temperature (being less than 600 degree) condition, realize the oxidation preparation of insulating layer of silicon oxide in TSV hole, optimize TSV and form silicon/oxidative silicon interface topography in MIS structure, reduce leakage current and the parasitic capacitance of TSV structure, improve device reliability.In conjunction with hard template etching technics, this technique can be applied to via middle technique.The oxide layer film thickness that the present invention prepares is even, and step coverage is very high.The present invention and traditional C VD cvd dielectric layer process compatible, further combined with TEOS CVD silica depositing operation, can improve the interface topography (roughness reduction) that TSV forms metal/silica in MIS structure, thereby further reduce TSV fabric drain electric current and parasitic capacitance, improve reliability.
Accompanying drawing explanation
Fig. 1 ~ Fig. 6 is the concrete implementing process cutaway view of the embodiment of the present invention 1, wherein
Fig. 1 is that the present invention utilizes photoresist etching to obtain the cutaway view after deep hole.
Fig. 2 is that the present invention removes the cutaway view after photoresist.
Fig. 3 is that the present invention utilizes oxygen plasma oxidation to obtain the cutaway view after oxide layer in deep hole.
Fig. 4 is that the present invention deposits the cutaway view obtaining after barrier layer and Seed Layer in deep hole.
Fig. 5 is that the present invention carries out the cutaway view after metallic conductor filling.
Fig. 6 is that the present invention carries out attenuate to substrate and obtains the cutaway view after through-silicon via structure.
Fig. 7 ~ Figure 11 is the concrete implementing process cutaway view of the embodiment of the present invention 2, wherein
Fig. 7 is that the present invention utilizes hard template etching to obtain the cutaway view after deep hole.
Fig. 8 is that the present invention is oxidized the cutaway view obtaining after oxide layer under oxygen plasma environment.
Fig. 9 is that this aspect obtains the cutaway view after barrier layer and Seed Layer in deep hole.
Figure 10 is that the present invention carries out the cutaway view after metallic conductor filling.
Figure 11 is that the present invention carries out attenuate to substrate and obtains the cutaway view after through-silicon via structure.
Description of reference numerals: 1-substrate, 2-deep hole, 3-photoresist, 4-the first oxide layer, 5-the first barrier layer, 6-the first sublayer, 7-the first metallic conductor, 8-hard template, 9-the second oxide layer, 10-the second barrier layer, 11-the second sublayer and 12-the second metallic conductor.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
In order to reduce the leakage current and the parasitic capacitance that form TSV structure, improve reliability, the preparation method of through-silicon via structure of the present invention comprises the steps:
A, provide substrate 1, described substrate 1 comprises front and the back side corresponding with described front, forms required deep hole 2 in the interior etching of substrate 1, and described deep hole 2 extends from the direction at the sensing back side, front of substrate 1;
B, the oxygen plasma carrying out in described deep hole 2 under oxygen plasma environment are oxidized or oxygen plasma anodic oxidation, and to form oxide layer on the inwall at deep hole 2, in described oxygen plasma oxidizing process, the temperature of substrate 1 is 200 ℃ ~ 600 ℃;
In the embodiment of the present invention, oxide layer is silicon oxide layer, the thickness of oxide layer is generally 0.1 μ m ~ 2 μ m, by oxygen plasma oxidation or oxygen plasma anodic oxidation under oxygen plasma environment, can under cryogenic conditions, realize the preparation of insulating layer of silicon oxide in TSV, reduce leakage current and the parasitic capacitance of TSV structure, improve TSV reliability of structure.
C, obtain barrier layer and Seed Layer in the interior deposition of deep hole 2 with oxide layer, described barrier layer is between Seed Layer and oxide layer;
D, in above-mentioned deep hole 2, carry out metallic conductor filling, described metallic conductor is filled in deep hole 2, and barrier layer is wrapped in the outer ring of metallic conductor;
E, attenuate is carried out in the back side of substrate 1, to form required through-hole structure.
For the different preparation process of silicon through hole, when the present invention specifically implements, can adopt the concrete steps of embodiment 1 or embodiment 2, by embodiment 1 and embodiment 2, the present invention is described further.
As shown in Fig. 1 ~ Fig. 6, the present embodiment, the TSV structure of go for first holing (via first), the preparation process of described through-silicon via structure comprises the steps:
A1, provide substrate 1, described substrate 1 comprises front and the back side corresponding with described front, forms required deep hole 2 in the interior etching of substrate 1, and described deep hole 2 extends from the direction at the sensing back side, front of substrate 1; Wherein, substrate 1 adopts silicon substrate, on the front of substrate 1, apply photoresist 3, utilize photoresist 3, as mask, etching is carried out in the front of substrate 1, to obtain deep hole 2 in substrate 1, deep hole 2 just extends towards the back side direction of substrate 1 from substrate 1, and the degree of depth of deep hole 2 is less than the degree of depth of silicon substrate 1, is also the non-through substrate 1 of deep hole 2.Utilizing photoresist 3 etchings to obtain after deep hole 2, need to utilize the method such as acetone or plasma etching to remove photoresist 3, and substrate 1 and the deep hole 2 removed after photoresist 3 are cleaned.Above-mentioned removal photoresist 3 and the step that substrate 1 is cleaned are the technical step of the art routine, and detailed process, by the art personnel are known, repeats no more herein.
B1, the oxygen plasma carrying out in described deep hole 2 under oxygen plasma environment are oxidized or oxygen plasma anodic oxidation, and to form the first oxide layer 4 on the inwall at deep hole 2, the temperature of the substrate 1 in described oxygen plasma oxidizing process is 200 ℃ ~ 600 ℃; While specifically enforcement, the first oxide layer 4 is silicon oxide layer, and the thickness of the first oxide layer 4 is 300nm, and in oxygen plasma oxidizing process, the temperature of substrate 1 is 400 ℃.In the embodiment of the present invention, the oxidation of oxygen plasma under oxygen plasma environment or oxygen plasma anodic oxidation obtain TSV hole inner boundary that the first oxide layer 4 and substrate 1 interface topography obtain with respect to existing Bosch technique slightly degree of making greatly reduce.
C1, obtain the first barrier layer 5 and the first sublayer 6 in the interior deposition of deep hole 2 with oxide layer, described the first barrier layer 5 is between the first sublayer 6 and the first oxide layer 4; In the embodiment of the present invention, can adopt existing conventional process to prepare the first barrier layer 5 and the first sublayer 6, the first barrier layer 5 covers in the first oxide layer 4, the first sublayer 6 covers on the first barrier layer 5, can effectively stop the follow-up copper metallic atom diffusion obtaining between metallic conductor 7 and substrate 1 by the first barrier layer 5.Usually, barrier layer adopts the materials such as titanium or titanium nitride, and Seed Layer adopts the conventional materials such as copper.
D1, carry out the first metallic conductor 7 fill in above-mentioned deep hole 2, described the first metallic conductor is filled in deep hole 2, and the first sublayer 6 is wrapped in the outer ring of the first metallic conductor 7; In the embodiment of the present invention, the first metallic conductor 7 adopts the mode of electro-coppering to be filled in deep hole 2, and after the first metallic conductor 7 is filled, the first sublayer 6 is wrapped in the outer wall of the first metallic conductor 7.In addition, the first metallic conductor 7 can exceed the front of substrate 1, now by CMP(Chemical Mechanical Polishing) technique carries out planarization to the front of substrate 1.The front of substrate 1 is carried out after planarization, the first barrier layer 5 and the first sublayer 6 on substrate 1 front are removed.
E1, attenuate is carried out in the back side of substrate 1, to form required through-hole structure.Carrying out, after above-mentioned steps, attenuate being carried out in the back side of substrate 1, exposing with the end of the first metallic conductor 7 of making adjacent substrates 1 back side, to carry out required attended operation.In the specific implementation, it is to carry out attenuate that substrate 1 is adopted to conventional step, the thickness thinning of substrate 1 is all removed the first oxide layer 4 of the first metallic conductor 7 belows, end, can be retained the first barrier layer 5 and the first sublayer 6 of the first metallic conductor 7 ends.
As shown in Fig. 7 ~ Figure 11, the technical process of boring (via middle) in the middle of the present embodiment is applicable to, the preparation method of described through-silicon via structure comprises the steps:
A2, provide substrate 1, described substrate 1 comprises front and the back side corresponding with described front, forms required deep hole 2 in the interior etching of substrate 1, and described deep hole 2 extends from the direction at the sensing back side, front of substrate 1; Wherein, substrate 1 adopts silicon substrate, hard template 8 is set on the front of substrate 1, utilize hard template 8, as mask, etching is carried out in the front of substrate 1, to obtain deep hole 2 in substrate 1, deep hole 2 just extends towards the back side direction of substrate 1 from substrate 1, and the degree of depth of deep hole 2 is less than the degree of depth of substrate 1, is also the non-through substrate 1 of deep hole 2.Utilizing hard template 8 etchings to obtain after deep hole 2, substrate 1 and deep hole 2 are cleaned.Hard template 8 is silicon nitride layer, above-mentioned hard template 8 is set, utilizes hard template 8 to carry out etching to substrate 1 and step that substrate 1 is cleaned is the technical step of the art routine, detailed process, by the art personnel are known, repeats no more herein.
B2, the oxygen plasma carrying out in described deep hole 2 under oxygen plasma environment are oxidized or oxygen plasma anodic oxidation, and to form the second oxide layer 9 on the inwall at deep hole 2, in described oxygen plasma oxidizing process, the temperature of substrate 1 is 200 ℃ ~ 600 ℃; When concrete enforcement, the second oxide layer 9 is silicon oxide layer, and the thickness of the second oxide layer 9 is 300nm, and in oxygen plasma oxidizing process, the temperature of substrate 1 is selected 400 degree.In the embodiment of the present invention, the oxidation of oxygen plasma under oxygen plasma environment or oxygen plasma anodic oxidation obtain interface that the second oxide layer 9 and substrate 1 silicon interface pattern obtain with respect to existing Bosch technique slightly degree of making greatly reduce.In the embodiment of the present invention, because hard template 8 is positioned at the positive of substrate 1 and does not remove, therefore, the second oxide layer 9 can not cover on the front of substrate 1.
C2, obtain the second barrier layer 10 and the second sublayer 11 in the interior deposition of deep hole 2 with oxide layer, described the second barrier layer 10 is between the second sublayer 11 and the second oxide layer 9; In the embodiment of the present invention, can adopt existing conventional process to prepare the second barrier layer 10 and the second sublayer 11, the second barrier layer 10 covers in the second oxide layer 9, the second sublayer 11 covers on the second barrier layer 10, can effectively stop the follow-up metallic copper atom diffusion obtaining between the second metallic conductor 12 and silicon substrate 1 by the second barrier layer 10.
D2, carry out the second metallic conductor 12 fill in above-mentioned deep hole 2, described the second metallic conductor 12 is filled in deep hole 2, and the second sublayer 11 is wrapped in the outer ring of the second metallic conductor 12; In the embodiment of the present invention, the second metallic conductor 12 adopts the mode of electro-coppering to be filled in deep hole 2, and after the second metallic conductor 12 is filled, the second sublayer 11 is wrapped in the outer wall of the second metallic conductor 12.In addition, the second metallic conductor 12 can exceed the front of substrate 1, now by CMP technique, planarization is carried out in the front of substrate 1.The front of substrate 1 is carried out after planarization, the second barrier layer 10 and the second sublayer 11 on substrate 1 front are removed.
E2, attenuate is carried out in the back side of substrate 1, to form required through-hole structure.Carrying out, after above-mentioned steps, attenuate being carried out in the back side of substrate 1, exposing with the end of the second metallic conductor 12 of making adjacent substrates 1 back side, to carry out required attended operation.In the specific implementation, adopt conventional step to carry out attenuate to substrate 1, the thickness thinning of substrate 1 is all removed the second oxide layer 9 of the second metallic conductor 12 belows, end, can be retained the second barrier layer 10 and the second sublayer 11 of the second metallic conductor 12 ends.
Using plasma oxidation technology of the present invention or plasma anodization technology, under low temperature (being less than 600 degree) condition, realize the oxidation preparation of insulating layer of silicon oxide in TSV hole, optimize TSV and form silicon/oxidative silicon interface topography in MIS structure, reduce leakage current and the parasitic capacitance of TSV structure, improve device reliability.In conjunction with hard template etching technics, this technique can be applied to via middle technique.The oxide layer film thickness that the present invention prepares is even, and step coverage is very high.The present invention and traditional C VD cvd dielectric layer process compatible, further combined with TEOS CVD silica depositing operation, can improve the interface topography (roughness reduction) that TSV forms metal/silica in MIS structure, thereby further reduce TSV fabric drain electric current and parasitic capacitance, improve reliability.
Claims (10)
1. an improved through-silicon via structure preparation method, is characterized in that, described through-silicon via structure preparation method comprises the steps:
(a), provide substrate (1), described substrate (1) to comprise front and the back side corresponding with described front, in substrate (1), etching forms required deep hole (2), described deep hole (2) extends from the direction at the sensing back side, front of substrate (1);
(b), in described deep hole (2), carry out oxygen plasma oxidation or the oxygen plasma anodic oxidation under oxygen plasma environment, to form oxide layer on the inwall in deep hole (2), in described oxygen plasma oxidizing process, the temperature of substrate (1) is 200 ℃ ~ 600 ℃;
(c), obtain barrier layer and Seed Layer having in the deep hole of oxide layer (2) deposition, described barrier layer is between Seed Layer and oxide layer;
(d), in above-mentioned deep hole (2), carry out metallic conductor filling, described metallic conductor is filled in deep hole (2), and barrier layer is wrapped in the outer ring of metallic conductor;
(e), attenuate is carried out in the back side of substrate (1), to form required through-hole structure.
2. improved through-silicon via structure preparation method according to claim 1, is characterized in that: described substrate (1) is silicon substrate, and the degree of depth of deep hole (2) in substrate (1) is less than the thickness of substrate (1).
3. improved through-silicon via structure preparation method according to claim 1, is characterized in that: described substrate (1) utilizes photoresist (3) or hard template (8) to carry out etching as mask, to obtain deep hole (2).
4. improved through-silicon via structure preparation method according to claim 3, it is characterized in that: described substrate (1) utilizes photoresist (3) etching to obtain after deep hole (2), remove the photoresist (3) on substrate (1) front, and substrate (1) and deep hole (2) are cleaned.
5. improved through-silicon via structure preparation method according to claim 3, is characterized in that: described substrate (1) utilizes hard template (8) etching to obtain after deep hole (2), and substrate (1) and deep hole (2) are cleaned.
6. improved through-silicon via structure preparation method according to claim 1, is characterized in that: the thickness of described oxide layer is 0.1 μ m ~ 2 μ m.
7. improved through-silicon via structure preparation method according to claim 1, is characterized in that: in described step (d), metallic conductor is filled in after deep hole (2), utilizes CMP technique to carry out planarization to the front of substrate (1).
8. improved through-silicon via structure preparation method according to claim 1, is characterized in that: the material of described metallic conductor comprises copper.
9. improved through-silicon via structure preparation method according to claim 1, is characterized in that: described metallic conductor is filled in deep hole (2) by plating mode.
10. improved through-silicon via structure preparation method according to claim 3, is characterized in that: described hard template (8) adopts silicon nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410069336.3A CN103794554A (en) | 2014-02-27 | 2014-02-27 | Improved preparation method of through silicon via structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410069336.3A CN103794554A (en) | 2014-02-27 | 2014-02-27 | Improved preparation method of through silicon via structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103794554A true CN103794554A (en) | 2014-05-14 |
Family
ID=50670090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410069336.3A Pending CN103794554A (en) | 2014-02-27 | 2014-02-27 | Improved preparation method of through silicon via structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103794554A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345836A (en) * | 2021-06-01 | 2021-09-03 | 浙江集迈科微电子有限公司 | TSV electroplating process |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101064347A (en) * | 2006-04-28 | 2007-10-31 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN101789417A (en) * | 2009-01-28 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Through-silicon via sidewall isolation structure |
| CN102074545A (en) * | 2009-11-09 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Integrated circuit element, semiconductor element and semiconductor technology |
| CN102299136A (en) * | 2010-06-28 | 2011-12-28 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
-
2014
- 2014-02-27 CN CN201410069336.3A patent/CN103794554A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101064347A (en) * | 2006-04-28 | 2007-10-31 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN101789417A (en) * | 2009-01-28 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Through-silicon via sidewall isolation structure |
| CN102074545A (en) * | 2009-11-09 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Integrated circuit element, semiconductor element and semiconductor technology |
| CN102299136A (en) * | 2010-06-28 | 2011-12-28 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345836A (en) * | 2021-06-01 | 2021-09-03 | 浙江集迈科微电子有限公司 | TSV electroplating process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103811416B (en) | The flattening method of through-silicon via sidewall | |
| US20140084472A1 (en) | Compound dielectric anti-copper-diffusion barrier layer for copper connection and manufacturing method thereof | |
| CN103377913B (en) | The forming method of opening | |
| CN102208363A (en) | Method for forming through silicon vias (TSV) | |
| TW201532241A (en) | Integrated circuit device and method for manufacturing the same | |
| US20190198337A1 (en) | Semiconductor device and semiconductor device manufacturing method | |
| US20140220762A1 (en) | Method of manufacturing isolation structure | |
| CN103943621B (en) | Fleet plough groove isolation structure and forming method thereof | |
| CN105448814A (en) | Method of forming semiconductor structure | |
| CN103700643B (en) | A kind of keyset deep-channel capacitor based on TSV technique and manufacture method thereof | |
| CN103794554A (en) | Improved preparation method of through silicon via structure | |
| US20150031202A1 (en) | Method for manufacturing semiconductor wafers | |
| CN105185702A (en) | Manufacturing method of high-K metal gate electrode structure | |
| CN104851835B (en) | Metal interconnection structure and forming method thereof | |
| CN108091609A (en) | The method that tungsten fills groove structure | |
| KR101767538B1 (en) | Metal-containing films as dielectric capping barrier for advanced interconnects | |
| CN108766953B (en) | Semiconductor device and method of forming the same | |
| CN103066093B (en) | A kind of deep trench isolation manufactures method and the image sensor structure of image sensor | |
| CN104347490A (en) | Through Si via filling method | |
| CN102945825A (en) | Copper interconnection structure with metal cap cover and manufacture method thereof | |
| CN107331646A (en) | Semiconductor structure and forming method thereof | |
| EP3093874B1 (en) | Tungsten layer depositing method capable of improving adhesive performance and filling performance | |
| CN103515281B (en) | The manufacture method of fleet plough groove isolation structure | |
| CN103413778A (en) | Forming method of isolation structure | |
| CN102610571B (en) | Method for forming double-stress etching barrier layer and front metal dielectric layers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140514 |