CN103765307B - Active matrix type display - Google Patents

Active matrix type display Download PDF

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Publication number
CN103765307B
CN103765307B CN201280037184.8A CN201280037184A CN103765307B CN 103765307 B CN103765307 B CN 103765307B CN 201280037184 A CN201280037184 A CN 201280037184A CN 103765307 B CN103765307 B CN 103765307B
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CN201280037184.8A
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CN103765307A (en
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川野英郎
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川野英郎
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Priority to JP2011195384A priority Critical patent/JP4918172B1/en
Priority to JP2011-195384 priority
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Priority to PCT/JP2012/063875 priority patent/WO2013035394A1/en
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134336Matrix
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3276Wiring lines
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0404Matrix technologies
    • G09G2300/0417Special arrangements specific to the use of low carrier mobility technology
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0819Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0247Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Abstract

The present invention relates to a kind of active matrix type display, problem is: as liquid crystal indicator or the pixel TFT of organic EL display, employ with amorphous silicon compare the bigger unbodied metal-oxide based semiconductor of field effect mobility or organic semiconductor time, low by the increase of the flicker level caused by the increase of overcharge effect and the uniformity of picture brightness, the display quality thus caused reduces, and suppresses it.Solution is: again derive flicker and the punch through voltage burnt out etc. during the higher middle tone of visibility shows and as relational expression between difference in the face of the opposite electrode current potential of overcharge effect index, difference in the face of the new opposite electrode current potential derived based on this is reduced to below tolerable limit value, is designed to meet above-mentioned condition.

Description

Active matrix type display

Technical field

The present invention relates to a kind of active array type at the transistor being configured with as each pixel breaker in middle element and show dress Put the technology that its display quality of middle reduction declines, reduce what the display quality caused by overcharge effect declined particularly to a kind of Technology, the time constant of the scan signal line that this overcharge effect is increased by the field effect mobility of transistor and extends is drawn Rise.

Background technology

Now, the thin film transistor (TFT) (hereinafter referred to as TFT) using amorphous (ア モ Le Off ァ ス) silicon thin film is used as liquid The switch element of crystal device etc., in the product such as display being widely used in radiotelevisor and PC.But its Field effect mobility is compared the least with silicon metal (brilliant シ リ U Application) with the polysilicon of below 100cm2/Vs, is about 0.5-1cm2/Vs, therefore along with large-scale high-precision refinement and the high-speed response of liquid crystal indicator, in order to ensure necessary electricity Flow, needs the size increasing TFT to tackle.

Result is that the parasitic capacitance of TFT increases, and in order to reduce the impact of parasitic capacitance, necessary auxiliary capacitor can increase. Auxiliary capacitor is formed as the cross capacitance between auxiliary capacitance line and pixel electrode, but in order to reduce time constant auxiliary electricity Holding line and generally preferably use the metal wiring with light-proofness, therefore result is that the increase of auxiliary capacitor brings auxiliary capacitance line Area increase, cause the reduction of aperture opening ratio.It is to say, along with large-scale high-precision refinement and high-speed response, aperture opening ratio without Method guarantees, amorphous silicon has a limit for the switch element of pixel.

On the other hand, in recent years, use the semiconductor element of metal-oxide based semiconductor thin film by extensive concern.This Thin film is had nothing in common with each other because of film build method and process conditions, and the field effect mobility of the thin film of solvable system (Soluble system) exists More than 3cm2/Vs, then has more than 10cm2/Vs, research from now on by the thin film of sputtering method (ス ッ パ ッ タ リ Application グ method) film forming It is expected to realize higher mobilance.It addition, can also be formed, have can film forming and being formed visible transparent at low temperatures The feature such as film and in the transparent substrate such as plastic base and thin film in flexible and transparent TFT (patent documentation 1).

It addition, as the oxide semiconductor film of the active layer for TFT, be made up of the oxide containing In, Ga and Zn The transparent amorphous thin film of half insulation be known by people, when using it for channel layer (チ ャ ネ Le), electrical conductivity is bigger InGaZnO3 (ZnO) 4 layer in the knot of top gate type (ト ッ プ ゲ ト type) TFT that lamination Au film is used as source-drain electrode Structure has been disclosed, and further, the TFT of amorphous InGaZnO4 compares with amorphous-si thin film transistor has the biggest electricity Field-effect mobility has been disclosed (patent documentation 2).

In addition to for liquid crystal indicator, other display dress is can be used in order to make these have the TFT of excellent characteristic Put, now the most active to its research and development carried out.Further, it is not necessary to set using expensive vacuum equipment as manufacture The exploitation of standby organic tft is the most active, the most also has product relevant that field effect mobility has exceeded 1cm2/Vs Report is burning the hotest to be applicable to the display device research and development as target.Patent document 3 discloses that a kind of by sweeping Retouch the scan line of the leading portion in direction and dielectric film to be formed with the Cs on of auxiliary capacitor between the pixel electrode of the configuration that partly overlaps In Array (the ア レ イ) substrate of gate type, reduce and flashed by produced by the reallocation of electric charge and the time constant of scan line Technology.

Prior art literature

Referenced patent document

Patent documentation 1: Japanese Unexamined Patent Publication 2000-150900 publication.

Patent documentation 2: Japanese Unexamined Patent Publication 2006-165529 publication.

Patent documentation 3: Japanese Unexamined Patent Publication 2003-177725 publication.

Summary of the invention

The problem that invention is to be solved

Fig. 1 corresponds to the equivalent circuit diagram of the outline of a part for the Array substrate of liquid crystal indicator 10, by scanning Multiple pixel regions that holding wire 11a, 11b...11n and display signal line 13a, 13b...13m are surrounded are with rectangular configuration. Scan signal line and display signal line are respectively provided with resistance, and cross one another region forms electric capacity.Therefore, each applied to being arranged on Time constant that signal potential (Vg, Vsig) the reason resistance of the current electrode of wiring end and electric capacity determine and make it propagate and prolong The most also distortion.Here, time constant is 1-1/e 0.632, i.e. the change of the current potential for being added on the current electrode of distribution Measure, the time required for its potential change of 63.2%.

Fig. 2 is the equivalent circuit diagram of the outline of pixel region shown in Fig. 1, and the grid of TFT15a is connected to scan signal line 11a, drain electrode is connected to display signal line 13a, and source electrode is connected to pixel electrode 19a.Pixel electrode 19a is by with scan signal line The auxiliary capacitance line 25a of the almost parallel configuration of 11a and dielectric film intersect, and cross part is auxiliary capacitor Cs.Auxiliary capacitance line 25a is also There is resistance, form electric capacity at the cross part with display signal line 13a.

Here, in order to reduce resistance, auxiliary capacitance line 25a needs to be formed by light-proofness metal, and therefore its existence makes opening Rate reduces.In order to suppress the reduction of aperture opening ratio, the composition of auxiliary capacitor needs various consideration, such as can be with pixel electricity The electrode of pole 19a electrical connection and the intersection region of auxiliary capacitance line 25a form auxiliary capacitor, or does not configure auxiliary capacitor Line 25a, forms auxiliary electricity in the intersection region of the extension of pixel electrode 19a and the scan line of epimere or hypomere pixel Hold.

It addition, be formed with parasitic capacitance Cgs between grid source between the grid of TFT15a and source electrode.By these distributions and pixel It is arranged in same insulative substrate the first substrate constituted, and between the second substrate being made up of insulative substrate, accompanies Liquid crystal layer 17a, thus constitutes liquid crystal indicator 10.Together with pixel electrode 19a, liquid crystal layer 17a clamped and constitute liquid crystal electricity The opposite electrode 21a holding Clc configures on the first substrate or on second substrate.

Fig. 3 represents in the equivalent circuit of Fig. 2, more higher just than opposed electrode potential Vcom by pixel electrode current potential Vp Grid current potential Vgl when polarity write is to charge to load capacitance Cload, Vgh, display signal line current potential Vsig, pixel electrode electricity The sequential chart (タ イ ミ Application グ チ ャ fore-telling) of position Vp and opposite electrode current potential Vcom.Fig. 3 (A) is from scan signal line 11a The figure of the pixel (left) that current electrode is nearer, Fig. 3 (B) is the current electrode pixel (right) farther out from scan signal line 11a Figure.

Current electrode to scan signal line 11a in Fig. 3, supplies only additional during the selection of scan signal line 11a making TFT15a becomes the grid current potential Vgh of ON state, becomes the grid current potential Vgl of OFF state at the additional TFT15a of making of non-selection period Pulse type scan signal line current potential Vg.The scan signal line current potential Vg of the current electrode of scan signal line 11a will be added to outward from OFF When the grid current potential Vgl of state switches to the grid current potential Vgh of ON state, due to the impact of timeconstantτ g, away from current electrode The grid current potential Vgh that the current potential of scan signal line 11a is moved to ON state from the grid current potential Vgl of OFF state needs certain time, because of This TFT15a from OFF state be converted to ON state need time elongated, during selection in load capacitance Cload charging time Between shorten.

Here, load capacitance is given by.

Cload=Clc+Cs+Cgs+Cother

Here Cother is coupling electric capacity (the カ ッ プ リ Application グ formed between pixel electrode 19a and each distribution about Capacity) summation.Therefore design liquid crystal indicator 10 time, need by TFT be sized to make from current electrode farthest Pixel during selecting in complete charging.In Fig. 3 (A), (B), when completing charging before ending during selection, pixel electrode 19a Current potential Vp, i.e. source electrode current potential Vs with the current potential i.e. drain electrode current potential Vd of display signal line 13a almost equal, from TFT15a to Load capacitance Cload does not has electric current to flow through, so the change of pixel electrode current potential Vp stops.So, when ending during selection, even The pixel electrode current potential Vp of each pixel being connected on same scan signal line is roughly equal.

The scan signal line current potential Vg being added on the current electrode of scan signal line 11a when ending during selection is from ON shape Gate electrode potential Vgh of state switches to gate electrode potential Vgl of OFF state, and the conducting state of each TFT15a connected starts Migrate to OFF state from ON state.Become from the current potential of gate electrode potential Vgh of ON state gate electrode potential Vgl to OFF state Change and affected by timeconstantτ g too, therefore the longest at a distance of the most remote required time with current electrode.That is, scanning letter it is added to When scanning signal on number line 11a is rectangular pulse, it is arranged in the scanning signal moment of TFT15a on current electrode side from ON The current potential Vgh of state drops to the current potential Vgl, TFT15a of OFF state and becomes OFF state, the electricity of this scan signal line current potential Vg Position variation delta Vg makes pixel electrode current potential Vp reduce by parasitic capacitance Cgs.

The slippage Δ Vp of pixel electrode current potential Vp at this moment is expressed as during Δ Vg=Vgh-Vgl being represented by the following formula.

Δ Vp=(Cgs/Cload) Δ Vg... (1)

Pixel electrode current potential slippage Δ Vp is considered as being made by the pixel electricity that the coupling effect of parasitic capacitance Cgs causes The slippage of electrode potential Vp, or gate electrode potential is when the current potential Vgh of ON state changes to the current potential Vgl of OFF state, dimension When holding the total amount of electric charge being stored in load capacitance Cload along with parasitic capacitance Cgs applied voltage change in polarity electric charge again The slippage of the produced pixel electrode current potential Vp of distribution.Current potential when above-mentioned pixel electrode current potential Vp is ended during selecting The phenomenon of the current potential dropping to the TFT15a corresponding to OFF state is referred to as break-through, the slippage of pixel electrode current potential Vp at this moment Δ Vp is referred to as punch through voltage (prominent I け) Δ Vp.

Vd Vs when ending during selection, therefore source-drain voltage Vds is Vds 0, from display signal line 13a to pixel Electrode 19a does not has electric current to flow through, but the reduction of this pixel electrode current potential Vp makes Vds=Δ Vp, corresponding gate-source voltage Vgs Electric current flows to pixel electrode 19a from display signal line 13a.The side of the current electrode of scan signal line 11a, gate electrode potential wink Between drop to the current potential Vgl, TFT15a of OFF state from the current potential Vgh of ON state and become OFF state, even if therefore Vds=Δ Vp, TFT15a only produce when the grid current potential Vgl that gate electrode potential is OFF state electricity small as the electric current Ioff between drain-source Stream, the change of the pixel electrode current potential Vp thus caused can be ignored.

But, along with TFT15a is away from the current electrode of scan signal line 11a, drop to OFF from the current potential Vgh of ON state Time needed for the voltage of the current potential Vgl of state declines is longer, and therefore TFT15a will not become OFF state moment, and TFT15a becomes Becoming in the period before OFF state, the electric current of corresponding source-drain voltage Vds flows to pixel electrode 19a from display signal line 13a.Also That is after ending during Xuan Zeing, the charging to load capacitance Cload is also continuing, and punch through voltage Δ Vp reduces.Break-through causes The reduction of pixel electrode current potential Vp, and the result of risings both phenomenons combination of pixel electrode current potential Vp that charging causes, Effective punch through voltage, i.e. effectively punch through voltage Δ Vp reduce.

When such as overall to the picture same current potential with positive polarity charges, TFT15a becomes pixel electrode during OFF state Current potential Vp reduces along with the current electrode away from scan signal line 11a, effective punch through voltage Δ Vp, therefore pixel electrode current potential Vp Rise.As a result, opposite electrode current potential Vcom and the difference of pixel electrode current potential Vp, i.e. liquid crystal layer applied voltage are along with away from scanning letter The current electrode of number line 11a and increase.During the write of negative polarity, pixel electrode current potential Vp i.e. source electrode current potential Vs writes than positive polarity Fashionable low, therefore gate-source voltage Vgs increases, and the charge volume to load capacitance proceeded after ending during selection also increases Greatly.

Therefore in negative polarity writes, effectively punch through voltage is little when writing than positive polarity.Now, show in positive polarity being write Show that holding wire current potential and effective punch through voltage are expressed as Vsig+ and Δ Vp+, display signal line current potential in negative polarity being write It is expressed as Vsig-and Δ Vp-, by respective to TFT15a positive polarity and negative polarity when OFF state with effective punch through voltage Pixel electrode current potential is expressed as Vp+ and Vp-, then Vp+ and Vp-is expressed from the next respectively.

Vp+=(Vsig+)-(Δ Vp+)

Vp-=(Vsig-)-(Δ Vp-)

It addition, the voltage being effectively added to liquid crystal layer can be regarded as powering up outside the liquid crystal layer of positive polarity and negative polarity The meansigma methods of pressure is basically identical.Therefore, when the average liquid crystal layer applied voltage of positive polarity and negative polarity is expressed as Vavg, Vavg It is expressed from the next.

Vavg=[{ (Vp+)-Vcom}+{Vcom-(Vp-) }]/2

={ (Vsig+)-(Vsig-) }/2+{ (Δ Vp-)-(Δ Vp+) }/2

Thus, in the pixel close to the current electrode of scan signal line, to load capacitance after ending during selecting Charging does not continues to, therefore Δ Vp-=Δ Vp+, average liquid crystal layer applied voltage Vavg={ (Vsig+)-(Vsig-) }/2.From In the current electrode of scan signal line pixel farther out, superfluous charging makes Δ Vp-< Δ Vp+, therefore powers up outside average liquid crystal layer Pressure ratio pixel close to the current electrode of scan signal line is low.Therefore, TFT15a is from the current electrode of scan signal line 11a The most remote, it is added to the average voltage of liquid crystal layer 17a, i.e. effective applied voltage is compared the lowest with the applied voltage specified.

During selection end after TFT15a become OFF state till period be referred to as overcharge during, during overcharge from TFT15a flows into the electric current of pixel electrode and is referred to as overcharge current, and the charging of load capacitance Cload was referred to as by overcharge current Charging, phenomenon produced by overcharge is generically and collectively referred to as overcharge effect.

As it has been described above, overcharge effect makes pixel electrode current potential Vp migrate (シ from the current potential specified in liquid crystal indicator Off ト), this migration amount increases along with the current electrode away from scan signal line 11a.As a result, various display is brought The bad reduction with display quality.When such as picture entirety shows same gray scale, the liquid crystal layer applied voltage that original picture is overall It is equal, but overcharge effect makes liquid crystal layer applied voltage drop from the lateral end side of the current electrode of scan signal line Low, therefore create the stable Luminance Distribution of referred to as brightness step (degree is tiltedly).But, when overcharge can suppress allowing In the range of time, brightness step is reduced in permissible range, use on will not be problematic.

The phenomenon that overcharge effect produces also has in addition to brightness step various situations.Wherein have higher Visibility, performance more significantly phenomenon be, optimal opposite electrode current potential Vcom, be distributed in the face of opt in caused by flicker (Off リッカー).Referring to the drawings, the optimal opposite electrode current potential Vcom producing overcharge effect, in the face of opt, distribution is drawn The mechanism of production of the flicker risen illustrates.

In liquid crystal indicator, constitute the liquid crystal capacitance Clc of a load capacitance Cload part of TFT15a, by pixel electricity Pole 19a and opposite electrode 21a and the liquid crystal layer 17a being clipped in these electrodes is constituted, by two interelectrode electric field controls liquid The orientation of the liquid crystal molecule in crystal layer, and then control the intensity of the light of permeate crystal layer 17a.Opposite electrode 21a and pixel electrode The orientation of the electric field controls liquid crystal molecule produced between 19a, therefore can not independently control the current potential of two electrodes in each pixel, But make the electrode potential of either one identical with other pixels from externally fed, the most independently control the opposing party Electrode potential.

At this moment, because pixel structure simplifies, so being favourable for aperture opening ratio and yield rate.Therefore, one As liquid crystal indicator in, opposite electrode and other pixels are formed integrated structure, current potential is powered from outside.Specifically Ground is said, opposite electrode generally, configures in counter substrate in the liquid crystal indicator of TN pattern and VA pattern on the whole Huge solid electrode (ベ タ) structure, in IPS pattern be scan signal line direction arrangement with each pixel one The structure changed.It addition, in the IPS pattern of a part, it was also proposed that cross and the most independently control Pixel electrode and the structure of opposite electrode.This structure has on this point at the inner evenness improving liquid crystal layer applied voltage Profit, but dot structure becomes complicated, is easily caused the reduction of aperture opening ratio and yield rate.

During as it has been described above, opposite electrode current potential Vcom moves to the multiple TFT being connected to same scan signal line, pixel electricity If electrode potential Vp is uneven in display picture, the applied voltage of liquid crystal layer 17a also can be uneven.As a result, uneven liquid The distribution of crystal layer applied voltage makes Luminance Distribution the most uneven, reduces display quality.Therefore, improve pixel electrode current potential Vp's Inner evenness is particularly significant.

Liquid crystal molecule can be electrolysed by DC voltage, it is therefore desirable to alternating voltage drives, and drives and makes to be added to liquid crystal layer The polarity of voltage often inverts.Therefore, when such as picture entirety shows same gray scale, TFT15a is positive polarity during OFF state Pixel electrode current potential is expressed as Vp+, and negative polarity pixel electrode current potential is expressed as Vp-, then by the potential setting of opposite electrode 21a For powering up outside dipolar liquid crystal layer during the meansigma methods of positive polarity pixel electrode current potential Vp+ and negative polarity pixel electrode current potential Vp- Press equal.

At this moment opposite electrode current potential Vcom is referred to as optimal opposite electrode current potential Vcom, opt, represents with following formula.

Vcom, opt={ (Vp+)+(Vp-) }/2

Opposite electrode current potential Vcom when optimal opposite electrode current potential Vcom, opt migrate, positive polarity and the liquid crystal of negative polarity Layer applied voltage is different, and the orientation of the liquid crystal molecule of the most each polarity is the most different.That is, the orientation of liquid crystal molecule changes over Change, therefore through light intensity be not certain, the most constantly vibrate, this vibration through light intensity just become flicker from And it is visible by naked eyes.Or, when the state that dipolar applied voltage is different continues, the difference of dipolar applied voltage, make Work for effective impressed DC voltage, induce the impurity ion in liquid crystal layer captured (ト ラ ッ プ) to pixel electrode The phenomenon on surface etc..If captured impurity ion increases, captured impurity ion can be formed by liquid crystal molecule Electric field response, can cause and burn out (I pays I) thus visible by naked eyes.

Fig. 4 (A) schematically illustrates different n points and the f point of arrangement on scan signal line direction, respective from it Optimal opposite electrode current potential Vcom, opt (n), Vcom, the flicker rate corresponding to the migration of opt (f) to opposite electrode current potential Vcom Relation.Here flicker rate refers to the light intensity of 30Hz proportion in full impregnated crosses light intensity at measuring point.The light of 30Hz It it is the frequency being easiest to be discovered as flicker by the mankind.Fig. 4 (B) schematically illustrates the current electrode at scan signal line Side in the location of pixels of opposition side, the feelings that pixel electrode current potential Vp and opposite electrode current potential Vcom changes because of overcharge effect Condition.

The solid line that in Fig. 4 (A), n point is corresponding represents the region close to the current electrode of scan signal line, the void that f point is corresponding Line represents from current electrode region farther out.The flicker rate of each point has one corresponding to the opposite electrode current potential Vcom of each point Minima, no matter opposite electrode current potential Vcom rises or declines on this basis, and flicker rate all increases.During flicker rate minimum Opposite electrode current potential Vcom is optimal opposite electrode current potential Vcom, the opt of this point, additional optimal opposite electrode current potential Vcom, The each point of opt, its opposite electrode current potential Vcom and the difference of pixel electrode current potential Vp, the i.e. liquid crystal layer of positive polarity and negative polarity are additional Voltage is equal.

As it was previously stated, overcharge effect makes positive polarity together with effective punch through voltage of the liquid crystal layer applied voltage of negative polarity Reducing, therefore as shown in Fig. 4 (B), the pixel electrode current potential Vp of positive polarity and negative polarity is along with the power supply electricity from scan signal line Pole is the most remote and rises, optimal opposite electrode current potential Vcom, opt be also as from scan signal line current electrode more away from and on Rise.When therefore opposite electrode current potential Vcom being set to certain value, as shown in Fig. 4 (A), even if the opposite electrode current potential of certain point Vcom is optimal opposite electrode current potential Vcom, opt, but other points then migrate from optimal opposite electrode current potential Vcom, opt, because of This flicker rate increases.

So, the flicker rate overall in order to reduce picture, as shown in Fig. 4 (B), to being present in n point and f point these 2 Good opposite electrode current potential Vcom, opt (n), Vcom, the c point setting opposite electrode current potential Vcom of the centre of opt (f), but at this moment Opposite electrode current potential Vcom be not the most optimal opposite electrode current potential Vcom, opt for any point of n point and f point, therefore Flicker cannot be completely eliminated.Therefore, for the flicker that cannot be completely eliminated, need to be suppressed within tolerable limit.

Flicker is to be caused, therefore by optimal opposite electrode current potential by positive polarity and the difference of the liquid crystal aligning of negative polarity Flicker rate corresponding to the deviation of Vcom, opt, it is on the physical property of the liquid crystal such as viscosity and dielectric constant anisotropy and affects liquid The thickness of liquid crystal layer of crystal layer electric field intensity etc. have interdependence with the parameter that response speed is relevant.But the most each panel vendor Liquid crystal indicator all has the target properties such as identical high-speed response and low voltage drive, and therefore result is if shown The basic specification such as pattern and driving method is the same from words, the least relative to the difference of these parameters of difference of liquid crystal material.

That is, by optimal opposite electrode current potential Vcom, the ratio of the change of the flicker rate corresponding to the deviation of opt, in display In the case of pattern is identical with driving method unrelated with liquid crystal kind, be substantially certain.Therefore, above-mentioned cannot be completely eliminated The visibility of flicker is with the optimal opposite electrode current potential Vcom of the following stated, difference in the face of opt, i.e. optimal opposite electrode current potential Difference δ Vcom, has the strongest dependency between opt.As shown in Fig. 4 (B), the optimal opposite electrode current potential of opposite electrode current potential Vcom The deviation of Vcom, opt, maximum at n point and f point, along with location of pixels diminishes close to central authorities.So, can will be equivalent to from Pixel that the current electrode of scan signal line is nearest and the optimal opposite electrode current potential Vcom of farthest pixel, the difference of opt, Good opposite electrode potential difference δ Vcom, opt is as the index of overcharge effect.

Then, optimal opposite electrode potential difference δ Vcom, opt is defined by the formula.

δ Vcom, opt=Vcom, opt (far)-Vcom, opt (near)

Here, Vcom, opt (near) represent the optimal opposite electrode from the nearest pixel of the current electrode of scan signal line Current potential, Vcom, opt (far) represent the optimal opposite electrode current potential of farthest pixel.

Overcharge effect as above can cause the display in the face by liquid crystal layer applied voltage caused by inhomogeneities Quality Down.Therefore, it is necessary to suppression overcharge effect, it is proposed that various methods.One of them be as it is shown on figure 3, Having a kind of method is that the change moment of display signal line current potential Vsig is delayed to the scan signal line current potential Vg grid from ON state After the moment of grid current potential Vgl that current potential Vgh is switched to OFF state, this method has been applied in a lot of liquid crystal display dresses In putting.In such as patent documentation 3, during for the change of current potential of change moment of current potential of scan signal line and display signal line The establishing method carved gives embodiment.

That is, connect before the TFT15a of this scan signal line 11a becomes OFF state, the current potential of display signal line 13a along The when that the charging of the load capacitance connecting next section of scan signal line 11b changing, the drain electrode electricity of overcharge period TFT Position Vd is from current potential corresponding to potential change corresponding to this pixel to next section of pixel.As a result, the pixel electrode current potential of this pixel from Setting there occurs bigger migration.In order to suppress above-mentioned situation, the TFT of this scan signal line to be connected such as need to become completely OFF state also changes the current potential of display signal line.This waiting time typically can be set to substantially with the time of scan signal line Constant is similar.

This mode is by suppressing overcharge effect in the setting of overcharge period TFT operating point.Overcharge with The field effect mobility of the flowing difficulty or ease of overcharge current, i.e. semiconductor layer has interdependence, therefore migrates for field effect Even if, overcharge is also had enough inhibitions for the amorphous silicon that rate is less the most in aforementioned manners, but field effect Mobility the most likely cannot obtain the inhibition enough to overcharge when increasing.But, for overcharge Between effect and field effect mobility, the report of the detailed result of study of relation does not the most also have.

Therefore, the inventor of the present invention utilizes the mould using in the exploitation of liquid crystal indicator all the year round and constantly improveing Intending device (シ ミ ュ レ タ), carry out with optimal opposite electrode potential difference δ Vcom, opt is as the mould of the index of overcharge effect Intend.In acquired results, the relation between overcharge effect and field effect mobility is as shown in Figure 5.Fig. 5 is to employ conduct 26 inches of Full-HD of the amorphous silicon of semiconductor layer, frame frequency 120Hz, TN pattern liquid crystal indicator in, field effect is moved The result that shifting rate is tried to achieve in the range of 0~50cm2/Vs.

Relative to general optimal opposite electrode potential difference δ Vcom, the tolerable limit of opt is about 0.2V, electric field effect in Fig. 5 The increase answering mobility has made optimal opposite electrode potential difference δ Vcom, and opt is considerably beyond 0.2V.That is, in order to imitate at electric field Mobility is answered when increasing, to reduce optimal opposite electrode potential difference δ Vcom, opt, it is necessary to import countermeasure in design and manufacturing process.

It addition, liquid crystal indicator is to control the orientation shape with the liquid crystal molecule of dielectric constant anisotropy by electric field State, therefore relative to being applied to the voltage of liquid crystal layer 17a, liquid crystal capacitance Clc can difference, punch through voltage Δ Vp is also according to liquid crystal Layer applied voltage and different.It addition, flicker and the visibility burnt out etc. are different according to liquid crystal layer applied voltage too.Liquid crystal The brightness flop of the change correspondence of layer applied voltage, the 50% liquid crystal layer applied voltage V50 when the brightness of high-high brightness 50% Greatest around, therefore overcharge effect caused by inhomogeneities various in the face of the liquid crystal layer applied voltage that overcharge produces Strengthen at the visibility of phenomenon liquid crystal layer applied voltage the most nearby.

Therefore, the parsing of overcharge effect is carried out when 50% liquid crystal layer applied voltage V50, will power up outside 50% liquid crystal layer It is 50% punch through voltage Δ Vp that the punch through voltage Δ Vp of pressure V50 particularly shows, v50.In addition in the present invention, the solution of overcharge effect Analysis need not the liquid crystal layer applied voltage during brightness being limited to high-high brightness 50%, can be according to the visibility of overcharge effect Impact select the liquid crystal layer applied voltage of other ratios.

The higher display state of visibility of flicker is picture entirety when show same middle tone, therefore electric to break-through Pressure Δ Vp can only consider 50% punch through voltage Δ Vp, v50.But, burning out is the liquid crystal layer by above-mentioned positive polarity and negative polarity Produced by the difference of applied voltage, this voltage difference be effective punch through voltage face in inhomogeneities caused, the most at last Overcharge effect is faint in the case of can ignoring, under the display state that different gray areas mix, and punch through voltage Δ Vp changes along with gray scale, causes producing in effective applied voltage of liquid crystal layer direct voltage component.

The difference caused accordingly, as gray scale, i.e. direct voltage component corresponding to the difference of liquid crystal layer applied voltage Different rejection conditions, the method all the time used is the maximum punch through voltage during load capacitance Cload minimum by formula (1) Δ Vp, max, and maximum punch through voltage Δ Vp, minimum punch through voltage Δ Vp when max and load capacitance Cload maximum, min's Difference, i.e. maximum punch through voltage difference d (Δ Vp) max=Δ Vp, max-Δ Vp, min, it is set in below reference value.

It addition, liquid crystal capacitance Clc is also different because of applied voltage, the maximum of liquid crystal capacitance Clc and minima table respectively Being shown as Clc, max, Clc, min, 50% liquid crystal capacitance Clc corresponding for liquid crystal layer applied voltage V50 are expressed as 50% liquid crystal capacitance Clc, v50, then its each self-corresponding load capacitance Cload can also be expressed as maximum load electric capacity Cload, max, minimal negative Carry electric capacity Cload, min, 50% load capacitance Cload, v50.

Here, optimal opposite electrode potential difference δ Vcom, in the parsing of opt, by positive polarity pixel electrode current potential Vp+ with negative The moment that calculates of polarity pixel electrode potential Vp-started to the time of 3 times during selecting as the moment of ending during selecting Moment of process.Moment after TFT becomes OFF state the most completely when this is break-through described later compensation driving, by calculating The pixel electrode current potential in this moment, the impact of leakage current when can ignore the OFF state of TFT, it is possible to clearly Carry out the parsing of overcharge effect.

The method designed the existing pixel corresponding to amorphous silicon (a-Si) with reference to the following drawings illustrates.This is right The summary of the device model of ratio is as described below.Pixel fineness Full-HD (scan signal line number 1080), Pixel Dimensions 100 μ m 300 μm, scan signal line selects period 7.55 μ s, the relative dielectric constant of gate insulating film and thickness be respectively 7.4,Liquid crystal mode of operation is TN, and maximum liquid crystal capacitance Clc, max are 0.365pF, and minimum liquid crystal capacitance Clc, min are 0.177pF, 50% liquid crystal capacitance Clc, v50 are 0.271pF.

It addition, TFT shape is as shown in Figure 6, for amorphous silicon, being made as the U-shaped generally used, the long L of raceway groove imagines One minimum process size is also set to 4 μm.The setting item of the said equipment model, whole existing for described in this specification It is all common for method and embodiments of the invention described later.Other individual settings project and parameter are the most independent Indicate.

The pixel design of liquid crystal indicator is made up of 2 key elements: determine the TFT chi that load capacitance Cload of TFT is corresponding Very little, and, formed between scan signal line and display signal line and pixel electrode that suppression is arranged in around pixel electrode The produced coupling of parasitic capacitance.As the 3rd key element, also have impurity in leakage current based on TFT and liquid crystal layer from The load capacitance that the charge maintenance capability of load capacitance Cload corresponding to son imposes a condition sets, but this is with the mistake of the present invention Charging is separate, is therefore not explained in this.

Coupling between display signal line and pixel electrode 19a, can by auxiliary capacitance electrode is arranged in both it Screen effect produced by between is substantially reduced.But, in order to reduce the coupling between display signal line and pixel electrode, necessary Auxiliary capacitor size ordinarily be about more than 0.1pF.

To this, the coupling between pixel electrode 19a and scan signal line, particularly and between this scan signal line 11a The change of the produced pixel electrode current potential Vp of coupling, mainly connect the TFT15a having pixel electrode 19a source electrode and Produced by parasitic capacitance Cgs formed on the intersection region of gate electrode, the most above-mentioned punch through voltage Δ Vp.That is, coupling electric capacity Main body be parasitic capacitance Cgs of TFT, therefore cannot utilize screen effect to reduce coupling, result its just in all of coupling In play dominating role.

Reduce parasitic capacitance Cgs that method is reduction formula (1) of punch through voltage Δ Vp or increase load capacitance Cload, or Person reduces scan signal line potential change amount Δ Vg.The raceway groove width W and the long L of raceway groove of TFT15a, and the gate electrode electricity of ON state Position Vgh by assuring that for the magnitude of current of load capacitance Cload charging is determined, the gate electrode of W/L and ON state Current potential Vgh coordinates contrary relation mutually.

But, gate electrode potential Vgh of ON state is highly susceptible to the output bias etc. of the driving IC of scan signal line Impact, therefore it is not recommended that carry out fine-adjusting current amount according to gate electrode potential Vgh of ON state, but needs necessary ON state The value of gate electrode potential Vgh is set as a value being attached with certain surplus.Therefore, the gate electrode electricity according to ON state it is usually After position Vgh substantially determines current value, it is finely adjusted further according to raceway groove width W.In order to increase W/L, preferably long for raceway groove L is set Obtain the least, be typically all set as technologic minimum process size, be fixed value the most in design.OFF state Gate electrode potential Vgl is the work that the impact of leakage current of threshold voltage vt h and TFT15a by reducing TFT15a determines Skill parameter, design can be regarded as fixed value.

It addition, the liquid crystal capacitance Clc constituting load capacitance Cload substantially determines according to Pixel Dimensions, therefore load capacitance Dominant trait's parameter of Cload is auxiliary capacitor Cs.Therefore, the important parameter of the value of decision punch through voltage Δ Vp is as raceway groove width Parasitic capacitance Cgs of the function of W and load capacitance Cload of the function as auxiliary capacitor Cs.Therefore, raceway groove width W is with negative Carry electric capacity Cload to meet with restrictive condition relevant for punch through voltage Δ Vp, and it can be made to restrain by revising mutually numerical value Determine.

Non-compensation drives

As existing pixel method for designing, for the island semiconductor of TFT15a employs the situation of amorphous silicon, Illustrate referring to the drawings.The individual parameters of this situation is, scan signal line timeconstantτ g=2.5 μ s, threshold value electricity Gate electrode potential Vgh=20V of pressure Vth=1.5V, ON state, gate electrode potential Vgl=-6V of OFF state, field effect is moved Shifting rate μ eff=0.5cm2/Vs.

Fig. 6 is the TFT shape being widely used as amorphous silicon TFT, it is characterized in that split deviation (closing せ ズ レ) institute The parasitic capacitance Cgs rate of change produced is the least.In this case, wide for raceway groove W can be defined as the source on island semiconductor 57 Edge (the エ ッ ヂ) length of electrode 51.It addition, because channel shape is U-shaped, therefore there is a minima in the wide W of raceway groove Wmin-u.This is because, in the case of the line part shorter only formation arc sections of U-shaped, parasitic capacitance produced by split deviation Cgs rate of change is increased dramatically.Using U-shaped electrode as drain electrode 53, inner side linear electrode as source electrode 51, the long L of raceway groove If=4 μm, minima Wmin-u of the wide W of raceway groove during the μm of source electrode width=4 is 14.3 μm.

In Fig. 6, the distance of the end of the end of gate electrode 55 and island semiconductor 57 is set as that the split with being equivalent to 3 σ is inclined Under difference adjacent to each other time consistent, because semiconductor layer is relative to gate electrode layer arrangement in a row, island semiconductor 57 and gate electrode 55 It is the relation of direct split, so the distance of the end of the end of gate electrode 55 and island semiconductor 57 is set as being equivalent to 3 σ's Directly split precision δ d.Equally, the distance on the top of the end of island semiconductor 57 and drain electrode 53 is set as with being equivalent to 3 σ Split deviation under adjacent to each other time consistent, because semiconductor layer and source-drain electrode layer are embarked on journey row relative to gate electrode layer jointly Row, island semiconductor 57 and drain electrode 53 are the relations of split the most indirectly, so the end of island semiconductor 57 and drain electrode The distance of the end of 53 is set as being equivalent to the indirect split precision δ i of 3 σ.

In this specification, in the explanation of comparative example and embodiments of the invention, will be equivalent to the direct split precision δ d of 3 σ It is set as 3 μm and 4 μm respectively as common item with indirect split precision δ i.This value is the liquid crystal cause initial stage as described later The numerical value of craft precision.But, even today that split precision improves, gate electrode end and semiconductor layer end spacing and In the top spacing of semiconductor layer end and drain electrode, it should the bigger surplus to split deviation will be guaranteed, the most often will These distances are set as 3 μm and 4 μm as the liquid crystal cause initial stage, at this moment can have the split deviation being equivalent to 4 σ and 5 σ Surplus.

The parasitic capacitance Cgs region formed in the region surrounded by dotted line 59 in Fig. 6 can be defined as, from by island half The central authorities of the channel region that source electrode 51 on conductor 57 and drain electrode 53 are clipped in the middle to the region near source electrode 51, and The sum of the intersection region of source electrode 51 and gate electrode 55.It addition, the change of parasitic capacitance Cgs of split deviation generation is considered as Region on island semiconductor 57 is unchanged, and is only the change of the intersection area of source electrode 51 and gate electrode 55.

Therefore, parasitic capacitance Cgs is by raceway groove width W, raceway groove long L, TFT shape and split precision and unit-area capacitance Determined.The width Ws of source electrode 51 can be set to technologic minimum process size, the therefore design parameter of parasitic capacitance Cgs Only raceway groove width W, other are all that technological parameter is the most in design for fixed value.

Chargeable maximum load electric capacity in sum, in the design of liquid crystal indicator, corresponding to raceway groove width W The domain of the existence of Cload, max and the punch through voltage Δ Vp corresponding to raceway groove width W is reduced to the bottom line of below reference value The domain of the existence of maximum load electric capacity Cload, max of necessity, the candidate areas that common collection area is pixel of both.Should In candidate areas, during auxiliary capacitor Cs minimum, aperture opening ratio is maximum, becomes best pixel.

Particularly to existing amorphous silicon, for punch through voltage Δ Vp, maximum during load capacitance Cload minimum is worn Logical voltage Δ Vp, max, and maximum punch through voltage Δ Vp, minimum punch through voltage Δ Vp when max and load capacitance Cload maximum, Difference between min, i.e. maximum punch through voltage difference d (Δ Vp) max is reduced to reference value and the following is restrictive condition all the time.Should State is as shown in Figure 7.Here, as the restrictive condition to punch through voltage Δ Vp, the maximum punch through voltage that will use all the time The higher limit of Δ Vp, max and maximum punch through voltage difference d (Δ Vp) max is set to 1.7V, 0.35V.

In Fig. 7, the figure of W-Cload represents the chargeable maximum capacitor corresponding to raceway groove width W, i.e. W-Cload characteristic, ditch Maximum load electric capacity Cload, max corresponding to road width W are set in the downside of the figure of this W-Cload.W-Δ Vp, the chart of max Show that maximum punch through voltage Δ Vp, max corresponding to raceway groove width W are maximum load electric capacity Cload, max during higher limit, in order to Making maximum punch through voltage Δ Vp, max less than its higher limit, need the maximum load electric capacity Cload of formula (1), max is set in The upside of this figure.It is upper that the figure of W-d (Δ Vp) max illustrates maximum punch through voltage difference d (Δ Vp) max corresponding to raceway groove width W Maximum load electric capacity Cload, max during limit value, in order to make maximum punch through voltage difference d (Δ Vp) max less than its higher limit, needs Maximum load electric capacity Cload, max are set in the upside of this figure.

That is, in order to make it each be reduced to below reference value, by maximum load electric capacity Cload, max is set in WCload's The downside of figure, and in the figure of W-d (Δ Vp) max and W-Δ Vp, the upside of the figure of max.In Fig. 7, the figure of W-d (Δ Vp) max Being positioned at W-Δ Vp, the upside of the figure of max, therefore in the underside area of figure of W-Cload and be positioned at the figure of W-d (Δ Vp) max The candidate areas that upper-side area is pixel.When not having other conditions, this pixel candidate areas split shed rate is maximum, i.e. by hiding The point of the auxiliary capacitor minimum that the electrode of photosensitiveness is constituted is best pixel.Therefore, the figure of W-Cload and the figure of W-d (Δ Vp) max Relative to W all in monotonic increase, the intersection point X of two figures is best pixel.

Fig. 8 is for the figure of W-Cload in Fig. 7 and the state of the intersection point X of the figure of W-d (Δ Vp) max, to 50% break-through electricity Pressure Δ Vp, v50 are design 50% punch through voltage Δ Vp, v50typ during design load, and parasitic capacitance Cgs is because of split deviation 50% punch through voltage Δ Vp during change, v50 relative to designing 50% punch through voltage Δ Vp, v50typ with during ± 0.5V change The result that good opposite electrode potential difference δ Vcom, opt are simulated and obtain.

In Fig. 7, the figure of W-d (Δ Vp) max is W=37.3 μm, Cload with the state of the intersection point X of the figure of W-Cload, max =0.802pF, is Δ Vp if conversion, v50=1.29V.By optimal opposite electrode potential difference δ Vcom, the higher limit of opt is set to ξ +=0.2V, if lower limit is set to ξ-=-0.2V, ξ in Fig. 8+and ξ-50% punch through voltage Δ Vp, v50 be respectively 1.13V and 1.71V.Thus, 50% punch through voltage Δ Vp, v50 are to increase at Δ Vp, v50 relative to the variable quantity of allowing of design load It is respectively δ (Δ Vp, v50) +=1.71-1.29=0.42V, δ (Δ Vp, v50)-=1.29-1.13=time big and when reducing 0.16V。

50% punch through voltage Δ Vp, if in the change direction of v50 without deflection by δ (Δ Vp, v50)+and δ (Δ Vp, V50)-in a less side determine, at this moment δ (Δ Vp, v50)-=0.16V determines pixel.The change of punch through voltage Δ Vp is complete When portion is caused by the change of parasitic capacitance Cgs, the tolerable limit δ Cgs of this change is equivalent to 4.49fF according to formula (1).This parasitism The change of electric capacity Cgs is only by time caused by split deviation, and the tolerable limit of this split departure uses unit-area capacitance to calculate 5.14 μm are equivalent to if going out.

Here, the change area of parasitic capacitance Cgs be equivalent to the width Ws of source electrode 51 on direct split departure δ d with The change of the composition length of split departure δ i indirectly, when the occurrence frequency of these split deviations is normal distribution, this synthesis is spelled Close departure δ di and be expressed as SQRT (δ d^2+ δ i^2).Here the square root in SQRT () represents bracket, A^2 represents the power of A. The split precision at liquid crystal cause initial stage is δ d=3 μm under 3 σ, δ i=4 μm, and δ di at this moment is 5 μm.In recent years split precision obtains Improving, δ d=2 μm, δ i=3 μm under 3 σ, δ di is that the deviation of 5.14 μm is equivalent to 4.3 σ.

That is, under the craft precision at liquid crystal cause initial stage, the split departure of the photoresist of parasitic capacitance Cgs can be more than 5.14 μm is in the case of 3 more than σ, is equivalent to 4.3 σ under the craft precision of today, and therefore the impact on yield rate is the least, permissible Ignore.Therefore, in the case of field effect mobility is the a-Si of 0.5cm2/Vs, even if not considering optimal opposed electricity during design Electrode potential difference δ Vcom, opt, the split departure provided with the craft precision of today is optimal opposite electrode current potential if manufacturing Difference δ Vcom, within opt also can be automatically controlled at allowable limit.

On the other hand, for the transparent amorphous oxide semiconductor (TAOS) that field effect mobility is 10cm2/Vs, It is used for the situation of existing method for designing, illustrates referring to the drawings.Here individual parameters is, scan signal line Timeconstantτ g=2.5 μ s, gate electrode potential Vgh=15V of threshold voltage vt h=0V, ON state, the gate electrode of OFF state Current potential Vgl=-2V, field effect mobility [mu] eff=10cm2/Vs.

Fig. 9 illustrates relation (W-Cload characteristic), the raceway groove width W in TAOS to raceway groove width W and chargeable maximum capacitor With the relation (W-Δ Vp, max characteristic) of maximum punch through voltage Δ Vp, max and and maximum punch through voltage difference d (Δ Vp) max Relation (W-d (Δ Vp) max characteristic) is simulated the result tried to achieve.In Fig. 9, when being given with in the case of amorphous silicon About the restrictive condition of maximum punch through voltage Δ Vp, max and maximum punch through voltage difference d (Δ Vp) max time, for meeting Δ Maximum load electric capacity Cload, max during Vp, max 1.7V and d (Δ Vp) max 0.35V, even if will in the figure of W-Cload Raceway groove width W is set as that minima Wmin-u of U-shaped TFT can also write.In the case of not providing other restrictive conditions, Good pixel candidate is present in W-Δ Vp, and W-d (Δ Vp) max above the figure of max schemes the upper and minima of raceway groove width W On the point of Wmin-u.The pixel of this state is W=14.3 μm, Cload, max=0.477pF, is Δ Vp if conversion, v50 =0.67V.

Figure 10 is the best pixel candidate for trying to achieve from Fig. 9, to 50% punch through voltage Δ Vp, when v50 is design load Design 50% punch through voltage Δ Vp, v50typ, and 50% punch through voltage when parasitic capacitance Cgs changes because of split deviation etc. Δ Vp, v50 are relative to designing 50% punch through voltage Δ Vp, and v50typ is with optimal opposite electrode potential difference δ during ± 0.5V change The result that Vcom, opt are simulated and obtain.

In Figure 10, ξ +=0.2V, ξ-=-0.2V, 50% punch through voltage Δ Vp, v50 are that the situation allowing change limitation is When 50% punch through voltage Δ Vp, v50 reduce, δ (Δ Vp, v50)-=0.0236V.Corresponding parasitic capacitance Cgs allow change The ultimate value of amount is for being equivalent to 0.531fF.The change of this parasitic capacitance Cgs is entirely the feelings produced by the split deviation of photoresist Departure feasible value under condition is equivalent to 0.608 μm.

The tolerable limit of this departure, though be equivalent under the split precision of today 3 σ direct split departure δ d and When split departure δ i is respectively 2 μm and 3 μm indirectly, just corresponds to 0.506 σ, in volume production line, split accuracy control is existed 0.506 below σ is impossible in reality.Therefore, it is the TAOS of 10cm2/Vs for field effect mobility, in order to design By optimal opposite electrode potential difference δ Vcom during liquid crystal indicator, opt controls below tolerable limit value, except maximum being worn Logical voltage Δ Vp, max and maximum punch through voltage difference d (Δ Vp) max control beyond below reference value, in addition it is also necessary to import new limit Condition processed.

Additionally, by optimal opposite electrode potential difference δ Vcom in above explanation, the tolerable limit value of opt be set to ξ += 0.2V, ξ-=-0.2V, this value is an example of the value in actual application.Actually optimal opposite electrode potential difference δ The tolerable limit value of Vcom, opt is the value determined by product specifications, is different to each goods.But, field effect is moved When shifting rate increases, optimal opposite electrode potential difference δ Vcom, even if the tolerable limit value of opt is bigger than the value shown in example, existing Craft precision under control allowing by optimal opposite electrode potential difference δ Vcom, opt in the range of the departure that can manufacture The design of the liquid crystal indicator in value remains highly difficult.

Compensate and drive

As it was previously stated, overcharge current is to be worked as the source-drain voltage Vds of TFT by punch through voltage Δ Vp to be produced Raw, therefore overcharge effect extremely depends on punch through voltage Δ Vp.Therefore, punch through voltage Δ Vp is reduced and can effectively reduce Overcharge effect.As the one of which of these means, list break-through and compensate driving.It is by driving that break-through originally compensates driving Dynamic make punch through voltage Δ Vp reduce thus reduce auxiliary capacitor Cs, increase aperture opening ratio.

Break-through compensates driving and had been proposed that a variety of method practical, substantially utilizes the coupling of auxiliary capacitor Cs The reduction of the pixel electrode current potential Vp being caused break-through compensates, fully reduce effective punch through voltage Δ Vp this It is identical on Dian.That is, the pixel electrode electricity caused by the change of the scan signal line current potential Vg of parasitic capacitance Cgs The variable quantity of position Vp, follows the pixel electrode current potential Vp's that the potential change of the auxiliary capacitance electrode by auxiliary capacitor Cs caused When variable quantity is equal, the change of pixel electrode current potential Vp is repealed by implication, here it is break-through compensates the principle driven.

Then, as break-through compensation condition, following formula is set up.

(Cgs/Cload) Δ Vg=(Cs/Cload) Δ Vcs... (2)

Here, Δ Vcs is the potential change amount of auxiliary capacitance electrode.This relational expression is formed at pixel at auxiliary capacitor Cs Also set up in the case of the extension of electrode and the intersection region of scan signal line of leading portion pixel, i.e. Cs on Gate structure. In this case, scan signal line current potential Vg is reduced to the gate electrode of OFF state from gate electrode potential Vgh that TFT is ON state Before current potential Vgl, it is reduced to the current potential Vgc of the lower 3rd than Vgl.That is, the current potential of this scan signal line is from the grid electricity of ON state When electrode potential Vgh switches to gate electrode potential Vgl of OFF state, the current potential of leading portion scan signal line switches to Vgl from Vgc.This Time, Δ Vcs=Vgl-Vgc.

The existing example driven is compensated, referring to the drawings to amorphous silicon employs Cs on as corresponding break-through The situation of Gate illustrates.The individual parameters of this situation is, scan signal line timeconstantτ g=2.5 μ s, threshold voltage Gate electrode potential Vgh=20V of Vth=1.5V, ON state, gate electrode potential Vgl=-6V of OFF state, field effect migrates Rate μ eff=0.5cm2/Vs.Raceway groove width W is with being suitable for the non-compensation of break-through and driving in the case of in amorphous silicon, it is 37.3 μ m。

It is less on the impact of the charging of load capacitance Cload in the period that TFT is ON state that break-through compensates driving, is here Even making to ignore.Therefore, W-Cload characteristic at this moment and W-Δ Vp, max characteristic and W-d (Δ Vp) max characteristic are with Fig. 7 Equally.

Figure 11 is to have carried out the existing method in the case of break-through compensates driving in amorphous silicon by Cs on Gate In 50% punch through voltage Δ Vp, v50 and optimal opposite electrode potential difference δ Vcom, the relation of opt is simulated the knot of gained Really.L is to represent 50% punch through voltage Δ Vp, the design load of v50, i.e. designs corresponding to 50% punch through voltage Δ Vp, v50typ Optimal opposite electrode potential difference δ Vcom, opt, i.e. design optimal opposite electrode potential difference δ Vcom, the figure of the relation of typ, M (0V) ~M (2V) is each design 50% punch through voltage Δ Vp representing 0V~2V, 50% punch through voltage Δ Vp, the change of v50 in v50typ Optimal opposite electrode potential difference δ Vcom corresponding to change, the figure of the relation of the change of opt.

Along with designing 50% punch through voltage Δ Vp, the increase of v50typ, design optimal opposite electrode potential difference δ shown in L Vcom, typ slowly increase, and intersect with transverse axis when about 2V.At this moment, 50% punch through voltage Δ Vp, v50 are each when increasing and reduce From allow variable quantity δ (Δ Vp, v50)+and δ (Δ Vp, v50)-equal, allow that variable quantity is maximum.Specifically, Δ Vp, δ (Δ Vp, v50) +=δ (Δ Vp, v50)-=0.150V during v50typ=2.12V, under this state, the change of Δ Vp, v50 is complete Allow that Cgs variable quantity δ Cgs is 2.49fF when portion is to be caused by the change of Cgs.This Cgs change is entirely is drawn by split deviation Rise time allow split departure, the direct split precision δ d and indirect split precision δ i that are equivalent to 3 σ are respectively 2 μm and 3 μm Time, be equivalent to 2.37 σ.At this moment maximum load electric capacity Cload, max are 0.526pF, auxiliary with comparing when the non-compensation of break-through drives Helping electric capacity Cs can reduce 0.276pF, just this part just can make aperture opening ratio increase.

Here it is not described in detail, in the case of in actual design, break-through compensates and drives, the design of punch through voltage Carry out to condition without restriction, try to achieve design 50% punch through voltage Δ Vp based on formula (1), if v50typ typically about 2V~2.5V.Although split accuracy control not can not still can be had any problem at 2.37 σ or following in manufacturing engineering, because of This reality is improve split precision etc. by the transformation of manufacture equipment to come corresponding.That is, even if taking above-mentioned labour, depend on So need break-through to compensate the punch through voltage restrictive condition in the case of driving and relax the auxiliary capacitor reduction and opening of realizing brought Mouth rate increases.In the manufacturing engineering implementing above-mentioned correspondence, the break-through of existing amorphous silicon compensates in the case of driving, just Calculating does not considers with the restrictive condition that punch through voltage is relevant, finally optimal opposite electrode potential difference δ Vcom, and opt also can be controlled System is in permissible range.

It addition, compensate driving in spite of implementing break-through, the reason that the overcharge of break-through impact produces is, wearing of formula (2) Logical compensation condition is to make break-through compensation process consistent at the current potential in moment of ending, on the other hand, and actually scan signal line electricity The potential difference that the time rate of change of the current potential between position and the pixel electrode current potential compensating driving is inconsistent and produces, thus produce Overcharge current.

That is, the establishing method of the time constant of scan signal line and auxiliary capacitance line is entirely different, especially with regard to electric capacity Setting, normally due to both dielectric films constitute different so unit-area capacitance is the most different, the additionally feelings of scan signal line Under condition, the value of only time constant is important, on the other hand, in order to also in addition to time constant in the case of auxiliary capacitance line There is the functions such as reduction coupling, will be determined by calculating tight to capacitance.So, normally due to scan signal line and auxiliary The time constant difference of capacitor line is relatively big, the initial stage during the overcharge after particularly just ending during the selection of scan signal line, Pixel electrode potential change amount that the potential change of scan signal line is caused and the potential change of auxiliary capacitance line are caused Pixel electrode potential change amount is not repealed by implication.The variable quantity of consequent pixel electrode current potential is source-drain voltage Vds, Overcharge current produces.

Or in the case of Cs on Gate, pixel electrode is divided into from the process of the potential change that this scan signal line accepts 2 stages, the first stage be select during just end after the current potential of scan signal line switch from gate electrode potential Vgh of ON state To the change of the current potential Vgc of the lower than gate electrode potential Vgl of OFF state the 3rd, second stage be from the 3rd current potential Vgc cut Shift to the change of gate electrode potential Vgl of OFF state.The process of the corresponding potential change from the acceptance of leading portion scan signal line is only Be from the 3rd current potential Vgc switch to OFF state gate electrode potential Vgl change once.Accordingly, there exist one to sweep from this Retouch holding wire accept pixel electrode potential change amount and from leading portion scan signal line accept pixel electrode potential change amount not The period mutually offsetted, because creating overcharge current in Gai Qijian.

If summary carried out above, at the existing amorphous silicon that field effect mobility is about 0.5cm2/Vs In the design of liquid crystal indicator, the impact of overcharge effect is less, even if the most not providing caused, work by overcharge effect For the restrictive condition that the optimal opposite electrode potential difference δ Vcom, opt of the index of flicker are relevant, optimal opposite electrode potential difference δ Vcom, opt also can fall in permissible range naturally.But, if field effect mobility increases, overcharge effect also increases, because of In the case of this field effect mobility is the TAOS of 10cm2/Vs, in order to optimal opposite electrode potential difference δ Vcom, opt are dropped As little as in permissible range, need to import new restrictive condition when design.

The present invention is in view of, done by above point, it is an object of the invention to provide the active square of a kind of high display quality Matrix type display apparatus.It is an object of the invention to further, be 1cm2/Vs to 70cm2/Vs to having field effect mobility scope The active matrix type display of transistor, improve its display quality.It is an object of the present invention to provide this active further The manufacture method of array display device.

For solving the means of problem

In the present invention, flicker that the overcharge effect increased in the increase with field effect mobility causes or picture In the index that brightness uniformity reduces, use difference in the face of the opposite electrode current potential Vcom on scan signal line direction, the most right Put difference in Electrode Potential δ Vcom, it is provided that for flicker or picture brightness uniformity being reduced control in permissible range new Restrictive condition in design, it is achieved high-quality active matrix type display.

The present invention also provides for a kind of method, can suppress to affect after field effect mobility is more than 1cm2/Vs the most aobvious The display quality caused by overcharge effect write reduces.In display quality by charge effects impact for brightness step, burning Badly wait with being distributed relevant parameter in the face of optimal opposite electrode current potential Vcom, opt.Especially, visibility it is directed to higher Flicker, by optimal opposite electrode current potential Vcom, difference, i.e. optimal opposite electrode potential difference δ in the face of the scan-line direction of opt Vcom, opt are as index, it is provided that the new design condition that suppression flicker or picture brightness uniformity reduce.Further this Bright provide, when the field effect mobility of semiconductor layer is more than 1cm2/Vs, determine ON state gate electrode potential Vgh, The value of the process control parameter of electric capacity Cgs etc. between gate electrode potential Vgl of OFF state, load capacitance Cload and grid source, and Can be by optimal opposite electrode potential difference δ Vcom, opt controls the relational expression in allowing excursion.

Specifically, optimal opposite electrode potential difference δ Vcom, during the middle tone of the brightness that opt can be expressed as high-high brightness n% N% punch through voltage Δ Vp, the linear function of vn, and the change by produced parasitic capacitance Cgs of impact etc. of manufacturing process Changing the n% punch through voltage Δ Vp caused, the change of optimal opposite electrode potential difference δ Vcom, opt corresponding to the change of vn is made For n% punch through voltage Δ Vp, the function of vn specifies.Further, for technological level, in order to less than optimal opposed electricity Tolerable limit value ξ of electrode potential difference δ Vcom, opt, needs the condition met by the design load of n% punch through voltage Δ Vp, vn, logical Before crossing, the relational expression of regulation derives.

Figure 24 is scan signal line timeconstantτ g=2.5 μ s, the gate electrode potential of threshold voltage vt h=0V, ON state Vgh=15V, gate electrode potential Vgl=-6V of OFF state, design 50% punch through voltage Δ Vp, during v50typ=1.5V, will close Be formula, and optimal opposite electrode potential difference δ Vcom will be designed by simulation, typ field effect mobility [mu] eff be 0~ The figure that the result tried to achieve in the range of 100cm2/Vs compares.In analog result, along with the increasing of field effect mobility [mu] eff Greatly, designing optimal opposite electrode potential difference δ Vcom, typ monotonic increase, but the value calculated according to relational expression, in field effect Designing optimal opposite electrode potential difference δ Vcom in the region of mobility [mu] eff > 50cm2/Vs, typ is to reduce.Overcharge is The phenomenon that overcharge current causes, the difficulty of electric current flowing, the i.e. the biggest overcharge current of field effect mobility are the biggest, because of The minimizing of this value calculated according to relational expression implies and has exceeded the applicable limit.

It addition, in the field effect mobility [mu] eff region that slope of a curve is the biggest when about below 2cm2/Vs, mould Intending result and do not obtain stable curve, there occurs inclination, this is key area for simulation.Its reason is, for electricity The change of field-effect mobility μ eff, designs optimal opposite electrode potential difference δ Vcom, and the change of typ is the sensitiveest, it is taken as that be The convergence in numerical analysis that results from is relatively low.To this, although the value calculated according to relational expression is stable curve, will close Be formula derive time use formula for interpolation (interior formula) to carry out matching (fitting) analog result, it is taken as that result from simulation The inclination of constringent curve shape is that equalization is caused, and field effect mobility [mu] eff is about below 2cm2/Vs's In region, relational expression the value calculated more has reliability than analog result.

Figure 25 is to represent the figure that the value calculated from relational expression deducts the value Δ after the analogue value.In order to will calculate from relational expression Value regards the most consistent as with the analogue value, and the tolerable limit of both differences is assumed to 20mV, then according to Figure 25, about 1.5 ~in the region of 70cm2/Vs, field effect mobility [mu] eff is below tolerable limit.Here, error 20mV is, as showing Show when the luminance difference of the top and bottom of the picture that the time constant of holding wire caused is converted into liquid crystal layer applied voltage poor Tolerable limit and the value that uses, Figure 25 is not the result of the applied voltage difference comparing neighbor, but the analogue value and by closing It is the comparison of the value that formula calculates, therefore as the ultimate value that there was no significant difference, uses 20mV.

It addition, if it is considered that field effect mobility [mu] eff is in the simulation corresponding to about 2cm2/Vs area below Convergence is relatively low, actually can regard the lower limit 1.5cm2/Vs to be less than in the most consistent region as, near 1cm2/Vs Can also regard as the most consistent.

More than according to, the scope of application of relational expression is the scope that field effect mobility is about 1cm2/Vs~70cm2/Vs, The scope of preferably 1.5cm2/Vs~50cm2/Vs.It addition, the scope of n is about 15-70, say, that be applicable to 15% and arrive The middle tone of 70% brightness shows.Further, when n is set to 50, the ratio of the transmitance change that in general change in voltage is corresponding Example is maximum, is therefore preferably optimal opposite electrode potential difference δ Vcom, and opt is expressed as 50% punch through voltage Δ Vp, the one of v50 Secondary function.

It addition, for flicker, be not only the change of the brightness flashed on and off interior on a large scale of display picture, be radius yet For several mm sizes tiny area brightness slight vibration whole display picture on a large scale in random distribution.Adjacent is micro- The luminance difference of little blinking region, due to tiny area and also brightness is unstable, actual measurement is highly difficult, is phase if subjective assessment When in about the 1-3 gray scale of 256 gray scales or more than.In this case, all without being considered as so-called flicker time most, But because small brightness irregularities display picture on a large scale in distribution, the profile that can cause display image is unintelligible, whole The image quality that body obscures etc..The flicker of this pattern is also referred to as winking.

It is by the optimal opposite electrode current potential Vcom caused by the slight film thickness distribution of gate insulating film that its reason speculates, In the face of opt, inhomogeneities is caused.That is, the thickness precision of the insulating properties thin film of gate insulating film etc. the most all manages and is setting Value ± 10% within.But, measure the determining film thickness image being disposed on around pixel region of thickness, the most not measure The film thickness distribution of actual pixel region.It is, therefore, usually considered that reality is worth the different region of thickness of little some % than management Being randomly dispersed in picture overall, for winking, this slight thickness difference can produce the distribution of slight punch through voltage, make The degree difference obtaining overcharge effect is the phenomenon can recognized by naked eyes.

In the case of considering adjacent 2 winking regions, because being the close and the narrowest and small region of mutual spacing, Each the change project caused by craft precision of the thickness etc. of the split departure in region and wiring width, liquid crystal layer, removes All can be regarded as identical beyond the thickness of gate insulating film.That is, it is exhausted that two interregional differences only result from grid Parasitic capacitance Cgs between the grid source of the TFT of the film thickness difference of velum.

In this case, the optimal opposite electrode current potential Vcom corresponding to the difference of two interregional punch through voltages, the difference of opt The slope η of the straight line M with represented by the formula (4) of the present invention is the most consistent.This is because, η is the change of parasitic capacitance Cgs between grid source The change of the optimal opposite electrode potential difference δ Vcom corresponding to change, opt of 50% punch through voltage Δ Vp, v50 that change etc. causes Ratio, the overcharge current caused by change of raceway groove long W during the change of parasitic capacitance between the grid source that split deviation is caused The impact of change, be the least with between grid source, the impact of the change of parasitic capacitance Cgs is compared.Therefore, the absolute value of η is the least The difference of adjacent winking degree is the least, can improve display quality.It addition, because being the phenomenon in the narrowest and small scope, Two interregional be considered as only between grid source parasitic capacitance Cgs be different, therefore control the right of each pixel for independent Put the situation of electrode potential, it is also possible to evaluate winking by η.

Figure 12 is to represent 50% punch through voltage Δ Vp, the design load of v50, i.e. designs 50% punch through voltage Δ Vp, v50typ With design optimal opposite electrode potential difference δ Vcom, the straight line L of the relation between typ, and 50% punch through voltage Δ Vp, v50 from Design optimal opposite electrode potential difference δ Vcom during 50% punch through voltage Δ Vp, v50typ change, the variation relation of opt straight Line M, and optimal opposite electrode potential difference δ Vcom, higher limit ξ+of the permissible range of opt and lower limit ξ-between relation Concept map.

The inventors found that straight line L can pass through below formula (3) and represent.

L: δ Vcom, typ=(α Δ Vp, v50typ+ β) γ ... (3)

Here, should be noted that the slope of straight line L is just, i.e. α γ > 0.This is that punch through voltage Δ Vp is as source-drain voltage Vds and work and produce overcharge current, and then carry out caused by overcharge.It addition, α, β, γ can be by aftermentioned The coefficient tried to achieve of formula.

The inventors found that straight line M can pass through below formula (4) and represent.

M: δ Vcom, opt=η (Δ Vp, v50-Δ Vp, v50typ)+δ Vcom, typ... (4)

Here, should be noted that the slope η < 0 of straight line M.This is because, 50% punch through voltage Δ Vp, v50 increases with change Time, the slippage of pixel electrode current potential Vp increases, makes optimal opposite electrode potential difference δ Vcom, opt reduce.

Then, by optimal opposite electrode potential difference δ Vcom, the high limit of tolerance value of opt and lower limit be expressed as ξ+and ξ-, ξ+and 50% punch through voltage Δ Vp of ξ-correspondence, v50 is expressed as Δ Vp, v50-and Δ Vp, v50+.Optimal in order to make Opposite electrode potential difference δ Vcom, the higher limit of opt is at ξ+following, if optimal opposite electrode potential difference δ of Δ Vp, v50- Vcom, opt at ξ+below, so according to

η ((Δ Vp, v50-)-Δ Vp, v50typ)+(α Δ Vp, v50typ+ β) γ ξ+

Can obtain

Δ Vp, v50typ-(Δ Vp, v50-) { (α Δ Vp, v50typ+ β) γ-(ξ+) }/η.

Equally, in order to make optimal opposite electrode potential difference δ Vcom, the lower limit of opt ξ-more than, if Δ Vp, v50+ Optimal opposite electrode potential difference δ Vcom, opt at ξ-above, so according to

η ((Δ Vp, v50+)-Δ Vp, v50typ)+(α Δ Vp, v50typ+ β) γ ξ-

Can obtain

(Δ Vp, v50+)-Δ Vp, v50typ { (ξ-)-(α Δ Vp, v50typ+ β) γ }/η.

Accordingly, by Δ Vp, v50 on the direction that Δ Vp, v50typ increase allow variable quantity δ (Δ Vp, v50)+, and Δ Vp, v50 allow variable quantity δ (δ Vp, v50)-be expressed as on the direction that Δ Vp, v50typ reduce

δ (Δ Vp, v50) +=(Δ Vp, v50+)-Δ Vp, v50typ > 0

δ (Δ Vp, v50)-=Δ Vp, v50typ-(Δ Vp, v50-) > 0

Below formula (5) and formula (6) can be obtained.

δ(δVp,v50)+≦{(ξ-)-(α·ΔVp,v50typ+β)γ}/η...(5)

δ(δVp,v50)-≦{(α·ΔVp,v50typ+β)γ-(ξ+)}/η...(6)

Therefore, as long as meeting formula (5) and formula (6) during design, just can control allowing by the flicker that overcharge effect causes In limit.

Here, the reason of the liquid crystal layer applied voltage being directed to high-high brightness 50% is, it is that transmitance-liquid crystal layer is additional In the relation of voltage, the region of the ratio maximum of the transmitance change that change in voltage is corresponding.That is, for liquid crystal layer applied voltage Change, the change of transmitance is the sensitiveest, therefore by the sudden strain of a muscle caused by inhomogeneities in the face of liquid crystal layer applied voltage in overcharge Bright and burning out etc. is easy to be recognized by naked eyes.But, along with the increase of the picture brightness of liquid crystal indicator in recent years, brightness 50% is the brightest, and therefore for the eyes of the mankind, visibility is relatively low, under the picture that specific luminance 50% is darker, sometimes depending on recognizing Property can height a bit.Therefore, referring to the drawings, to when picture brightness is set to the n% of high-high brightness, the formula of the present invention is tried to achieve (3) example of scope of the n and time formula (4) sets up illustrates.

Figure 22 is for δ Vcom, the opt corresponding for liquid crystal layer applied voltage Vn that picture brightness is high-high brightness n%, by mould The figure that plan result and δ Vcom, the opt-Vn characteristic obtained from formula (3) compare.Individual parameters is, the scan signal line time is normal Number τ g=2.5 μ s, gate electrode potential Vgh=15V of threshold voltage vt h=0V, ON state, gate electrode potential Vgl of OFF state =-2V, field effect mobility [mu] eff=10cm2/Vs.Further, display pattern is set to the liquid crystal layer state without applied voltage The normaly white of the lower i.e. high-high brightness of transmitance 100%, the relative dielectric constant ε 100 of liquid crystal during brightness 100% set For the minima 3.00 in the relative dielectric constant-applied voltage characteristic of liquid crystal, the liquid crystal layer applied voltage V100 of ε 100 correspondence As the threshold voltage of liquid crystal, liquid crystal layer applied voltage maximum V0 is set to 6.5V, brightness during V0 as 0%, liquid at this moment Brilliant relative dielectric constant ε 0 is set to 6.18.

Transmitance-have mutually between liquid crystal layer applied voltage characteristic and the relative dielectric constant-applied voltage characteristic of liquid crystal Having stronger dependency, the relative dielectric constant ε n of liquid crystal during brightness n% is by linearly inserting based on ε 0 and ε 100 Mend (shape) and try to achieve, try to achieve liquid corresponding to ε n by the relative dielectric constant of liquid crystal-liquid crystal layer applied voltage characteristic Crystal layer applied voltage Vn.It addition, Δ Vp, v50typ are replaced with the break-through of the liquid crystal layer applied voltage Vn of brightness n% by formula (3) The design load Δ Vp of voltage, calculates δ Vcom, opt, is also carried out same step in simulations after vntyp.

In Figure 22, for 50% liquid crystal layer applied voltage V50, the value tried to achieve from formula (3) is with the value of analog result and differs Cause, have the difference of about 6mV.This represents the precision that relational expression of the present invention is had, and it is allowed relative to general δ Vcom's, opt Ultimate value 200mV, is the deviation of about 3%, will not come into question in actual applications, therefore can be regarded as the most consistent 's.The difference of the δ Vcom, opt that try to achieve from formula (3) and simulation respectively, if the error within admitting of 10mV, then about In the range of 15% liquid crystal layer applied voltage V15~70% liquid crystal layer applied voltage V70, i.e. in the range of brightness 15%~70% Being considered as almost consistent, in the range of this, the formula (3) of the present invention is set up.It addition, in the region exceeding this scope, formula (3) value the most not differs greatly with the analogue value, therefore the 0% liquid crystal layer applied voltage V0 when the substantially inspection of not precision prescribed ~100% liquid crystal layer applied voltage V100 gamut in formula (3) also can use.

Figure 23 is the η-Vn characteristic will tried to achieve with the analog result that carries out under Figure 22 identical conditions and the formula (4) from the present invention The figure compared.By 50% punch through voltage Δ Vp in formula (4), v50 and design 50% punch through voltage Δ Vp, v50typ replaces respectively It is changed to n% punch through voltage Δ Vp, vn and design n% punch through voltage Δ Vp, calculates η after vntyp, be also carried out in simulations walking equally Suddenly.In Figure 23, liquid crystal layer applied voltage is in 10% liquid crystal layer applied voltage V10~the district of 100% liquid crystal layer applied voltage V100 In territory, i.e. brightness be 10%~100% scope in analog result in the range of error ± 1% and the formula (4) of the present invention Causing, formula (4) is set up in this range.More than according to, the following is concrete summary of the invention.

In the liquid crystal indicator of the active array type of the present invention, field effect mobility at more than 1cm2/Vs and Below 70cm2/Vs, optimal opposite electrode potential difference δ Vcom, the high limit of tolerance value of opt and lower limit be expressed as ξ+and ξ-, The n% punch through voltage Δ Vp, vn of ξ+and ξ-correspondence is expressed as Δ Vp, vn-and Δ Vp, vn+, designs n% punch through voltage table Be shown as Δ Vp, vntyp, n% punch through voltage Δ Vp, vn from design n% punch through voltage Δ Vp, vntyp increase time and reduce time Allow that change limitation amount is expressed as δ (Δ Vp, vn) +=(Δ Vp, vn+)-Δ Vp, vntyp and δ (Δ Vp, vn)-=Δ Vp, vntyp-(Δ Vp, vn-), the design load of optimal opposite electrode potential difference δ Vcom, opt, i.e. design optimal opposite electrode electricity Potential difference δ Vcom, typ are expressed as formula (3),

δ Vcom, typ=(α Δ Vp, vntyp+ β) γ ... (3)

The optimal opposite electrode potential difference δ Vcom that the variable quantity of n% punch through voltage Δ Vp, vn is corresponding, the variable quantity of opt Schedule of proportion is shown as η, and α, β, γ are the coefficient that formula described later is tried to achieve respectively, it is characterised in that δ (Δ Vp, vn)+and δ (Δ Vp, Vn)-be respectively set as meeting formula (5) and formula (6).

δ (Δ Vp, vn)+{ (ξ-)-(α Δ Vp, vntyp+ β) γ }/η ... (5)

δ (Δ Vp, vn)-{ (α Δ Vp, vntyp+ β) γ-(ξ+) }/η ... (6)

Further, n can be set as the scope of 15~70 by the present invention.Further, n can be preferably 50.N is set to 50, ξ + and the 50% punch through voltage Δ Vp, v50 of ξ-correspondence be expressed as Δ Vp, v50-and Δ Vp, v50+, 50% punch through voltage Δ Vp, v50 from designing 50% punch through voltage Δ Vp, v50typ increase time and reduce time allow that change limitation amount is expressed as

δ (Δ Vp, v50) +=(Δ Vp, v50+)-Δ Vp, v50typ and δ (Δ Vp, v50)-=Δ Vp, v50typ-(Δ Vp, v50-),

The design load of optimal opposite electrode potential difference δ Vcom, opt, i.e. design optimal opposite electrode potential difference δ Vcom, typ It is expressed as formula (3A)

δ Vcom, typ=(α Δ Vp, v50typ+ β) γ ... (3A)

The optimal opposite electrode potential difference δ Vcom that the variable quantity of 50% punch through voltage Δ Vp, v50 is corresponding, the variable quantity of opt Schedule of proportion be shown as η, α, β, γ are the coefficient that formula described later is tried to achieve respectively, it is characterised in that δ (Δ Vp, v50)+and δ (Δ Vp, v50)-be respectively set as meeting formula (5A) and formula (6A).

δ (Δ Vp, v50)+{ (ξ-)-(α Δ Vp, v50typ+ β) γ }/η ... (5A)

δ (Δ Vp, v50)-{ (α Δ Vp, v50typ+ β) γ-(ξ+) }/η ... (6A)

Display device is that in the case of the non-compensation of break-through drives, α, β, γ, η can be given by.

α=A exp (-1/ (B μ eff))+0.2

A={0.58exp (-1/Vgh)-0.591}Vth+{7.924exp (-1/Vgh)-7.23}

B=Ba{exp (Bb (Vgh-14))-1}+Bc

Ba=15exp (-0.455Vth)

Bb=0.00667Vth+0.01

Bc=1.2exp (-0.35Vth)-0.47

β=C exp (-1/ (D μ eff))-0.19

C=-0.002Vth+0.337exp (-1/Vgh)-0.148

D={0.06exp (-Vgh+14)+0.00042}exp (Vth)-0.0051Vgh+0.362

γ={ E exp (-F/ τ g)+G τ g} ν c

E={-0.00032 μ eff+0.01 (exp (-1.17/Vth)+1) } Vgh+0.008 μ eff+0.722exp (- 0.101Vth)

F={2.71exp (-0.0272 μ eff)+0.597exp (-1.37/Vth) }/Vgh+ (0.0667Vth+0.3) exp (-0.268μeff)

G={-0.0479 μ eff+1.4exp (-1.35/Vth)+1.75}/Vgh+0.0012 μ eff+0.0701exp (- 0.301Vth)-0.1

ν c=0.620exp (0.0353Vgh) (-Vgl) ^ (-0.0203Vgh+0.275)

η=η 0 γ 0

η 0=P exp (-1/ Δ Vp, vntyp)+Q

P={0.115exp (-0.164Vgh) exp (Vth)-0.00610Vgh+0.460} μ eff^ (-0.559)

Q=exp (-1/ (μ eff+Qa))+Qb

Qa=0.128Vgh-0.005exp (0.2Vth+4.70)+0.350

Qb=(0.0008Vth+0.0183) Vgh-0.0554Vth-1.88

γ 0=ν e κ (τ g)/κ (τ g=2.5)

κ (τ g)=exp (-R/ τ g)+S τ g+T

R=Ra1 exp (Ra2 μ eff) exp (-1/ (Vgh-10))+0.5exp (-Rc2/ μ eff)+Rc3

Ra1=0.214exp (-1.37/Vth)+0.351

Ra2=0.153exp (-1.37/Vth)-0.216

Rc2=1.29exp (0.388Vth)

Rc3=0.544exp (0.0147Vth)-1

S={0.000376loge (μ eff)-0.0000667Vth-0.00123}Vgh+Sb

Sb=(0.00237Vth+0.0345) exp (Sb2 μ eff)

Sb2=0.00258exp (0.388Vth)-0.05

T=Ta1 Vgh μ eff^Ta2+Tb1 loge (μ eff)+Tb2

Ta1=0.007exp (-1.60/Vth)+0.0258

Ta2=0.0223exp (0.265Vth)-0.1

Tb1=-0.0001Vth+0.0597

Tb2=0.847exp (-0.0966Vth)-3.00

ν e=(-0.0242Vgh+1.17) (-Vgl) ^ (0.0006Vgh^1.96)

Here, Vth, Vgh, Vgl and Δ Vp, the unit of vntyp is [V], and the unit of μ eff is [cm2/Vs], the list of τ g Position is [μ s].Additionally κ (τ g) represents that κ is the function of τ g, and " ^ " represents the symbol of power.Further, loge represents natural logrithm.

Break-through compensates in the case of driving, and α, β, η can be given by.

α=A μ eff+B

A=0.00001 [4exp (-0.462Vth)-15}Vgh+20.2exp (0.0361Vth)]

B=0.0001{ (4.33Vth+25.2) Vgh-203Vth+852}

β=C loge (μ eff)+D

C=0.0001 (16.2Vgh-0.6Vth-108)

D=-(0.0118Vth+0.105) loge (Vgh)+0.0374Vth+0.0625

η=η 0 γ 0

η 0=P exp (Δ Vp, vntyp)+Q

P=-Pa1 Vgh^ (Pa2) μ eff^ (Pb1 Vgh+Pb2)

Pa1=4exp (1.12Vth)+109

Pa2=-5exp (-1/ (0.0916Vth))-2.57

Pb1=0.00007Vth+0.0096

Pb2=-0.0146Vth-0.204

Q=-{ (0.0001Vth-0.0123) Vgh+0.0238Vth+1.08} μ eff^Qb

Qb=(4.46Vth+43.0) Vgh^ (-0.0289Vth-2.16)+0.0118Vth-0.185

γ 0=ν e κ (τ g)/κ (τ g=2.5)

κ (τ g)=exp (-R/ τ g)+S τ g+T

R=Ra1 exp (Ra2 μ eff) exp (-1/ (Vgh-10))+0.5exp (-Rc2/ μ eff)+Rc3

Ra1=0.214exp (-1.37/Vth)+0.351

Ra2=0.153exp (-1.37/Vth)-0.216

Rc2=1.29exp (0.388Vth)

Rc3=0.544exp (0.0147Vth)-1

S={0.000376loge (μ eff)-0.0000667Vth-0.00123}Vgh+Sb

Sb=(0.00237Vth+0.0345) exp (Sb2 μ eff)

Sb2=0.00258exp (0.388Vth)-0.05

T=Ta1 Vgh μ eff^Ta2+Tb1 loge (μ eff)+Tb2

Ta1=0.007exp (-1.6/Vth)+0.0258

Ta2=0.0223exp (0.265Vth)-0.1

Tb1=-0.0001Vth+0.0597

Tb2=0.847exp (-0.0966Vth)-3.00

ν e=(-0.0242Vgh+1.17) (-Vgl) ^ (0.0006Vgh^1.96)

Here, Vth and Vgh, Vgl and Δ Vp, the unit of vntyp is [V], and the unit of μ eff is [cm2/Vs], τ g's Unit is [μ s].Additionally κ (τ g) represents that κ is the function of τ g, and " ^ " represents the symbol of power.Further, loge represents nature pair Number.

The display device of active array type can be liquid crystal indicator or organic EL display.It addition, η's is absolute Value can be set to less than 2.Semiconductor layer can use unbodied metal-oxide or Organic substance.Use organic EL display dress When putting, the 2T1C type that a pixel is made up of 2 TFT and 1 electric capacity, or there is multiple TFT and the electricity of multiple electric capacity composition Road, still with the pixel of organic EL display during 2T1C type equivalence, can be with the pixel of liquid crystal indicator is on circuit Equivalence, meets formula (5) and the composition of formula (6) of above-mentioned restrictive condition.In the present invention, can be applicable to show by above-mentioned design techniques The manufacture method of showing device.

Invention effect

Pass through the present invention, it is provided that the active matrix type display of a kind of high display quality.Further, by this Bright, to having the active matrix type display of the transistor that field effect mobility scope is 1cm2/Vs to 70cm2/Vs, energy Improve its display quality.Further, the present invention is passed through, it is provided that the manufacture method of this active matrix type display.

Accompanying drawing explanation

Fig. 1 is the roughly equivalent circuit diagram of the structure representing liquid crystal indicator.

Fig. 2 is the roughly equivalent circuit diagram of the dot structure representing liquid crystal indicator.

Fig. 3 is driving potential waveform and the sequential chart of pixel potential of the principle representing overcharge effect.

Fig. 4 is to represent flicker rate and optimal opposite electrode current potential Vcom, the concept map of relation between opt.

Fig. 5 is the optimal opposite electrode potential difference δ Vcom corresponding to increase representing field effect mobility, and opt pushes away The analog result moved.

Fig. 6 is to represent parasitic capacitance Cgs between the amorphous silicon TFT and grid source thereof used in existing liquid crystal indicator The figure in region.

Fig. 7 is to represent in the comparative example that amorphous silicon is corresponding, the relation of the chargeable load capacitance that raceway groove width W is corresponding with And punch through voltage Δ Vp corresponding to raceway groove width W is reduced to the analog result of relation of the necessary load capacitance of below reference value.

Fig. 8 is to represent in the comparative example that amorphous silicon is corresponding, and 50% punch through voltage Δ Vp, v50 are from designing 50% break-through electricity Optimal opposite electrode potential difference δ Vcom during pressure Δ Vp, v50typ change, the analog result of the change of opt.

Fig. 9 is to represent in comparative example corresponding to TAOS, the relation of the chargeable load capacitance that raceway groove width W is corresponding and ditch Punch through voltage Δ Vp corresponding for road width W is reduced to the analog result of the relation of the necessary load capacitance of below reference value.

Figure 10 is to represent in comparative example corresponding to TAOS, and 50% punch through voltage Δ Vp, v50 are from designing 50% punch through voltage Δ Optimal opposite electrode potential difference δ Vcom during Vp, v50typ change, the analog result of the change of opt.

Figure 11 is to represent to have carried out the contrast in the case of break-through compensates driving in amorphous silicon by Cs on Gate In example, design 50% punch through voltage Δ Vp, v50typ and design optimal opposite electrode potential difference δ Vcom, the relation of typ, and 50% punch through voltage Δ Vp, v50 optimal opposite electrode potential difference δ from designing 50% punch through voltage Δ Vp, during v50typ change The analog result of the variation relation of Vcom, opt.

Figure 12 is for illustrating the relational expression of the present invention of suppression overcharge effect, represents design 50% break-through Voltage Δ Vp, v50typ and relation and the 50% punch through voltage Δ Vp designing optimal opposite electrode potential difference δ Vcom, typ, V50 from designing 50% punch through voltage Δ Vp, v50typ change time optimal opposite electrode potential difference δ Vcom, the variation relation of opt And optimal opposite electrode potential difference δ Vcom, the concept map of the tolerable limit value of opt.

Figure 13 is to represent in the embodiment being suitable for restrictive condition based on relational expression of the present invention in TAOS, designs 50% punch through voltage Δ Vp, v50typ and design optimal opposite electrode potential difference δ Vcom, the relation of typ, and 50% break-through electricity Δ Vp, v50 are from designing 50% punch through voltage Δ Vp for pressure, optimal opposite electrode potential difference δ Vcom during v50typ change, opt's The figure of variation relation.

Figure 14 is to represent that 50% wears in the embodiment being suitable for restrictive condition based on relational expression of the present invention in TAOS Logical voltage Δ Vp, v50, from designing 50% punch through voltage Δ Vp, allow variable quantity δ (Δ when the direction that v50typ reduces migrates Vp, v50)-and design 50% punch through voltage Δ Vp, the figure of the relation between v50typ.

Figure 15 is to represent in the embodiment being suitable for restrictive condition based on relational expression of the present invention in TAOS, allows spelling Close departure δ di and design 50% punch through voltage Δ Vp, the figure of the relation between v50typ.

Figure 16 is to represent to carry out being suitable for based on relation of the present invention when break-through compensates and drives by Cs on Gate in TAOS In one embodiment of the restrictive condition of formula, design 50% punch through voltage Δ Vp, v50typ and design optimal opposite electrode current potential Difference δ Vcom, the relation of typ, and 50% punch through voltage Δ Vp, v50 is from designing 50% punch through voltage Δ Vp, during v50typ change Optimal opposite electrode potential difference δ Vcom, the figure of the variation relation of opt.

Figure 17 is to represent to carry out being suitable for based on relation of the present invention when break-through compensates and drives by Cs on Gate in TAOS In one embodiment of the restrictive condition of formula, 50% punch through voltage Δ Vp, v50 are from designing 50% punch through voltage Δ Vp, v50typ Reduce direction and increase direction on migrate time respective allow variable quantity δ (Δ Vp, v50)-, δ (Δ Vp, v50)+and design 50% punch through voltage Δ Vp, the figure of the relation between v50typ.

Figure 18 is to represent to carry out being suitable for based on relation of the present invention when break-through compensates and drives by Cs on Gate in TAOS In one embodiment of the restrictive condition of formula, 50% punch through voltage Δ Vp, v50 are from designing 50% punch through voltage Δ Vp, v50typ Reduce direction and increase direction on migrate time respective allow split departure δ di-, δ di+ and design 50% punch through voltage Δ Vp, the figure of the relation between v50typ.

Figure 19 is to represent that amorphous silicon and TAOS are respectively break-through compensation driving and non-break-through compensates when driving, the present invention's The slope η of the straight line that formula (4) represents and 50% punch through voltage Δ Vp, the figure of the relation between the design load of v50.

Figure 20 is the outline equivalent circuit diagram of the pixel of basic organic EL display.

Figure 21 is the outline equivalent circuit diagram of organic EL display, is used for representing the picture of basic organic EL display Element is with the pixel equivalence of liquid crystal indicator.

Figure 22 is for the relation between optimal opposite electrode potential difference and gray level display voltage, by the relational expression of the present invention The figure compared with the result tried to achieve of simulation.

Figure 23 is the change of the optimal opposite electrode potential difference that the variable quantity of the punch through voltage by each gray level display voltage is corresponding The ratio of change amount, the figure that the result tried to achieve by the relational expression of the present invention and simulation is compared.

Figure 24 is for the relation between optimal opposite electrode potential difference and field effect mobility, by the relation of the present invention The figure that the result that formula and simulation are tried to achieve compares.

Figure 25 is for the relation between optimal opposite electrode potential difference and field effect mobility, by the relation of the present invention The difference of the optimal opposite electrode potential difference that formula and simulation are tried to achieve, the figure represented relative to each field effect mobility.

Description of reference numerals:

11a-11c scan signal line

13a-13c display signal line

15a thin film transistor (TFT) (TFT)

17a liquid crystal layer

19a pixel electrode

21a opposite electrode

25a auxiliary capacitance line

Clc liquid crystal capacitance

Cs auxiliary capacitor

Cgs parasitic capacitance

Cload load capacitance

Cload, max maximum load electric capacity

Vp pixel electrode current potential

Δ Vp punch through voltage (pixel electrode potential drop low amounts)

Δ Vp, v50 50% punch through voltage

Δ Vp, v50typ design 50% punch through voltage

Vcom opposite electrode current potential

Vcom1 supply voltage

Vcom, opt optimal opposite electrode current potential

δ Vcom opposite electrode potential difference

δ Vcom, opt optimal opposite electrode potential difference

δ Vcom, typ design opposite electrode potential difference

Vcs auxiliary capacitance electrode current potential

Vg scan signal line current potential

Δ Vg scan signal line potential change amount

Vs source electrode current potential

Vd drain electrode current potential

Vds source-drain voltage

Vgs gate-source voltage

The gate electrode potential of Vgh ON state

The gate electrode potential of Vgl OFF state

Vsig display signal line current potential

Detailed description of the invention

Non-compensation drives

For the TFT being made up of the TAOS that field effect mobility is 10cm2/Vs, referring to the drawings, to be suitable for based on The embodiment during design techniques of relational expression of the present invention illustrates.In the present embodiment, individual parameters is, scan signal line Timeconstantτ g=2.5 μ s, gate electrode potential Vgh=15V of threshold voltage vt h=0V, ON state, the gate electrode of OFF state Current potential Vgl=-2V, field effect mobility [mu] eff=10cm2/Vs of semiconductor layer.That is, these parameters are as with reference to Fig. 9, Figure 10 As Suo Shuoming, in existing design techniques, by optimal opposite electrode potential difference δ Vcom, opt control tolerable limit value with Under be highly difficult, but use the present invention maneuver, even if using these parameters also can carry out the design of liquid crystal indicator. Therefore, W-Cload characteristic and W-Δ Vp, the figure of max characteristic and W-d (Δ Vp) max characteristic is as Fig. 9.

Figure 13 is to represent the 50% punch through voltage Δ Vp tried to achieve by the relational expression of the present invention, the optimal opposed electricity that v50 is corresponding Electrode potential difference δ Vcom, the figure of the relation of opt.L is the figure tried to achieve by formula (3), represents that TFT is manufactured into posting when design is consistent The design 50% punch through voltage Δ Vp of raw electric capacity Cgs, design corresponding for v50typ optimal opposite electrode potential difference δ Vcom, typ.

" M (0V) "~" M (1.5V) " is the figure tried to achieve by formula (4) respectively, represents imagination design 50% punch through voltage Δ Vp, The situation that when v50typ is 0V~1.5V, parasitic capacitance Cgs changes from design load due to split deviation etc., thus 50% break-through electricity Δ Vp, v50 are from designing 50% punch through voltage Δ Vp for pressure, and v50typ is with optimal opposite electrode potential difference δ during ± 0.5V change Vcom,opt.By optimal opposite electrode potential difference δ Vcom, the tolerable limit of opt is set to ξ +=0.2V, ξ-=-0.2V, then Δ Vp in Figure 13, v50 > 0.2V region in, obviously have with reference to Figure 12 δ (Δ Vp, v50)-< δ (Δ Vp, v50)+, compared to increasing Time big, the 50% punch through voltage Δ Vp allowed when reducing, the variable quantity of v50 is less, to having designed dominating role.It addition, fall Low 50% punch through voltage Δ Vp, during v50, auxiliary capacitor Cs increases, and aperture opening ratio can be caused to reduce, the most do not consider Δ Vp, v50 < The region of 0.2V, only considers the region of Δ Vp, v50 > 0.2V.

With reference to Figure 12, Figure 13, in the region of Δ Vp, v50 > 0.2V, optimal opposite electrode potential difference δ Vcom to be examined, Opt than ξ+little δ (Δ Vp, v50)-.With reference to as described in Fig. 9, Figure 10, the pixel candidate obtained from existing design techniques is ditch Road width W=Wmin-u, maximum load electric capacity Cload, max=0.477pF, design 50% punch through voltage Δ Vp, v50typ= 0.67V, but be intended to set to little to the size that can not implement the management value of split precision, the most not best pixel.This Embodiment is based on Figure 13, to the maneuver finding out the best pixel that can the management value of split precision be set to enforceable scope Illustrate.

Figure 14 is to try to achieve to design 50% punch through voltage Δ Vp in Figure 13,50% punch through voltage that each value of v50typ is corresponding Allow variable quantity δ (Δ Vp, v50)-figure.In order to the management value of split precision is set to enforceable scope, need By bigger for the variable quantity δ (Δ Vp, v50) of the design load of punch through voltage-be set to.That is, with reference to the comparative example described in Fig. 9, Figure 10 In, design 50% punch through voltage Δ Vp, when v50typ is 0.67V, allow that split deviation is the least, be only equivalent to 0.506 σ, therefore Allow split departure as enforceable, according to Figure 14, design 50% punch through voltage Δ Vp, v50typ are set smaller than 0.67V.Therefore, according to the relational expression of the punch through voltage shown in formula (1), by the 50% load electricity of wide for fixing raceway groove W=Wmin-u Hold Cload, v50 as a parameter to represent design 50% punch through voltage Δ Vp, v50typ.Raceway groove width W is fixed as Wmin-u, is Bigger in order to avoid load capacitance is set to when raceway groove width W is bigger than Wmin-u, the auxiliary being thus made up of light-proofness electrode Electric capacity increases, and aperture opening ratio reduces.Accordingly, the design 50% punch through voltage Δ Vp shown in Figure 14, v50typ and the appearance of punch through voltage Permitted variable quantity δ (Δ Vp, v50)-between relation, could alternatively be the appearance of 50% load capacitance Cload, v50 and punch through voltage Permitted variable quantity δ (Δ Vp, v50)-between relation.50% load capacitance Cload of gained, v50 and punch through voltage allow change Change amount δ (Δ Vp, v50)-between relation, formula (1) can be reused, replace with 50% load capacitance Cload, v50 and grid Parasitic capacitance Cgs between the grid source of the relation gained allowed between variable quantity δ Cgs of parasitic capacitance Cgs between source allow change Change amount δ Cgs, can be inclined from the split with reference to the unit-area capacitance between grid source and parasitic capacitance Cgs between the grid source described in Fig. 6 Change area caused by difference, transforms to and allows split departure δ di.

Figure 15 is to represent from the design 50% punch through voltage Δ Vp, v50typ of Figure 14 gained and allow split departure δ di Between the figure of relation.The direct split departure δ d of 3 σ and indirectly split departure δ i that is equivalent to shown in Fig. 6 distinguishes Be set to 2 μm and 3 μm, then synthesis split departure δ di is 3.6 μm.According to Figure 15, it is known that when design 50% punch through voltage Δ Vp, v50typ are to allow during 0.539V that split departure δ di is 3.6 μm.It addition, try to achieve the maximum load electric capacity that this state is corresponding Cload, max are 0.570pF, according to Fig. 9, even if it is known that raceway groove width W is Wmin-u, are also the electricity being sufficient to charging Hold, and be positioned at W-Δ Vp, the top of the figure of the figure of max characteristic and W-d (Δ Vp) max characteristic.That is, will design 50% break-through Voltage Δ Vp, when v50typ is set as 0.539V, the surplus corresponding in order to have the synthesis split departure being equivalent to 3 σ, meet Existing break-through restrictive condition, i.e. maximum punch through voltage Δ Vp, max 1.7V and maximum punch through voltage difference d (Δ Vp) max 0.35V, and optimal opposite electrode potential difference δ Vcom will be designed, typ controls below allowable limit, by necessary auxiliary electricity The value held controls, in minimum, to become best pixel.

Compensate and drive

The feelings driven are compensated for the break-through that uses of Cs on Gate in TAOS that field effect mobility is 10cm2/Vs Under condition, referring to the drawings, embodiment when being suitable for design techniques based on relational expression of the present invention is illustrated.This reality Executing individual parameters in example is, scan signal line timeconstantτ g=2.5 μ s, the gate electrode electricity of threshold voltage vt h=0V, ON state Position Vgh=15V, gate electrode potential Vgl=-2V of OFF state, field effect mobility [mu] eff=10cm2/Vs.That is, with unreal Execute the parameter being suitable in embodiments of the invention when break-through compensates driving the same.It addition, it is ON shape to TFT that break-through compensates driving In the period of state, the impact of the charging of load capacitance Cload is less, even if even ignoring here.Therefore, the W-of the present embodiment Cload characteristic and W-Δ Vp, max characteristic and W-d (Δ Vp) max characteristic are as Fig. 9.

Figure 16 is to represent the 50% punch through voltage Δ Vp tried to achieve by the relational expression of the present invention, the optimal opposed electricity that v50 is corresponding Electrode potential difference δ Vcom, the figure of the relation of opt.L is the figure tried to achieve by formula (3), represents and is manufactured into designing posting of consistent TFT The design 50% punch through voltage Δ Vp of raw electric capacity Cgs, design corresponding for v50typ optimal opposite electrode potential difference δ Vcom, typ. " M (0V) "~" M (3V) " is the figure tried to achieve by formula (4) respectively, represents imagination design 50% punch through voltage Δ Vp, and v50typ is 0V ~during 3V parasitic capacitance Cgs owing to split deviation etc. is from the situation of design load change, thus 50% punch through voltage Δ Vp, v50 from Designing 50% punch through voltage Δ Vp, v50typ is with the optimal opposite electrode potential difference δ Vcom, opt during ± 0.5V change.

In Figure 16, represent design 50% punch through voltage Δ Vp, design corresponding for v50typ optimal opposite electrode potential difference δ The slope of the straight line L of Vcom, typ, situation about driving with the non-compensation of the break-through of Figure 14 is compared little.This is that break-through compensation driving is led The result of the effective punch through voltage reduction caused, is produced by overcharge current reduces.But, represent 50% punch through voltage Δ The optimal opposite electrode potential difference δ Vcom of the change correspondence of Vp, v50, the slope of the straight line M of the change of opt, with the non-compensation of break-through Situation about driving is compared and is wanted big, further to designing 50% punch through voltage Δ Vp, and the increase of v50typ, the slope of straight line M Absolute value increases.This is caused by break-through compensation condition, is because according to formula (2), and break-through compensates parasitic capacitance Cgs driven Have to be certain with the ratio of auxiliary capacitor Cs.

Now, straight line L, at design 50% punch through voltage Δ Vp, intersects with transverse axis when v50typ is 1.41V, at this moment 50% wears When logical voltage Δ Vp, v50 increase and reduce respective 50% punch through voltage allow variable quantity δ (Δ Vp, v50)+and δ (Δ Vp, V50)-equal, 50% punch through voltage allows that variable quantity is maximum.But, even if 50% punch through voltage allow that variable quantity is Greatly, the split departure δ di allowed is the most maximum.From formula (1), this is due to the parasitism between punch through voltage and grid source Ratio between electric capacity Cgs and load capacitance Cload is proportional.In the case of amorphous silicon is suitable for break-through compensation driving, 50% punch through voltage allows that the areas adjacent that variable quantity is maximum is designed, this is because less for field effect mobility Amorphous silicon, also can somewhat increase aperture opening ratio.To this, it is an object of the invention to use bigger partly the leading of field effect mobility The raising of image quality during body.Therefore, for the optimized maneuver seeking pixel based on Figure 16 in the present embodiment, referring to attached Figure illustrates.

The situation being suitable for the comparative example that break-through compensates driving in amorphous silicon with described in reference Figure 11 is identical, as this reality Execute break-through in example and compensate the mitigation of the restrictive condition relevant with break-through driven, not to maximum punch through voltage Δ Vp, max and maximum Punch through voltage difference d (Δ Vp) higher limit corresponding for max is set.That is, the optimized condition seeking pixel is, the most opposed Difference in Electrode Potential δ Vcom, opt are controlled in permissible range, and the management value of split precision is set in enforceable scope, And aperture opening ratio is maximum.

Figure 17 is to try to achieve to design 50% punch through voltage Δ Vp in Figure 16, each value of v50typ corresponding at 50% break-through electricity Direction that pressure reduces and the direction of increase allow variable quantity δ (Δ Vp, v50)-and δ (Δ Vp, v50)+figure.With using figure 14, Figure 15 illustrates break-through is non-, and to compensate situation about driving the same, allows variable quantity δ from 50% punch through voltage shown in Figure 17 (Δ Vp, v50)-and δ (Δ Vp, v50)+and design 50% punch through voltage Δ Vp, the relation between v50typ, try to achieve and allow split Departure δ di and design 50% punch through voltage Δ Vp, the relation between v50typ.

That is, raceway groove width W is fixed as W=Wmin-u, according to the relational expression of the punch through voltage shown in formula (1), negative by 50% Carry electric capacity Cload, v50 as a parameter to represent design 50% punch through voltage Δ Vp, v50typ.Raceway groove width W is fixed as Wmin- U, is bigger in order to avoid load capacitance to be set to when raceway groove width W is bigger than Wmin-u, is thus made up of light-proofness electrode Auxiliary capacitor increases, and aperture opening ratio reduces.Accordingly, the punch through voltage shown in Figure 17 allow variable quantity δ (Δ Vp, v50)-and δ (Δ Vp, v50)+and design 50% punch through voltage Δ Vp, the relation between v50typ, could alternatively be punch through voltage allows change Measure δ (Δ Vp, v50)-and δ (Δ Vp, v50)+and 50% load capacitance Cload, the relation between v50.

50% punch through voltage of gained allow variable quantity δ (Δ Vp, v50)-and δ (Δ Vp, v50)+and 50% load Electric capacity Cload, the relation between v50, formula (1) can be reused, replace with parasitic capacitance Cgs between grid source allows change Amount δ Cgs and 50% load capacitance Cload, the relation between v50.Parasitic capacitance Cgs between the grid source of gained allow variable quantity δ Cgs, can the unit-area capacitance between reference grid source and the split deviation institute of parasitic capacitance Cgs between the grid source described in Fig. 6 The change area caused, transforms to and allows split departure δ di.Especially, by 50% punch through voltage from designing 50% break-through electricity 50% punch through voltage in the direction that pressure reduces allow variable quantity δ (Δ Vp, v50)-correspondence allow that split departure is expressed as δ Di-, by 50% punch through voltage from design 50% punch through voltage increase direction 50% punch through voltage allow variable quantity δ (Δ Vp, v50)+corresponding allow that split departure is expressed as δ di+.

Figure 18 is to represent from 50% punch through voltage of Figure 17 gained from designing the 50% of the direction that 50% punch through voltage reduces Punch through voltage allow variable quantity δ (Δ Vp, v50)-correspondence allow split departure δ di-, and 50% punch through voltage is from setting Count the direction that 50% punch through voltage increases 50% punch through voltage allow variable quantity δ (Δ Vp, v50)+correspondence allow split Departure δ di+, and design 50% punch through voltage Δ Vp, the figure of the relation between v50typ.Figure 17 illustrates design 50% wear Logical voltage Δ Vp, the δ (Δ Vp, v50) near v50typ=2V+and for maximum, on the other hand, in Figure 18, δ di+ monotone decreasing is Because raceway groove width W is fixed as W=Wmin-u, to each design 50% punch through voltage Δ Vp, 50% load capacitance that v50 tries to achieve Cload, v50 are relative to designing 50% punch through voltage Δ Vp, and v50typ is the degree of monotone decreasing, than δ (Δ Vp, v50)+increasing The degree added wants big.Result is, allows split departure δ di-and δ di+ relative to designing 50% punch through voltage Δ Vp, v50typ All in monotone decreasing.

The direct split departure δ d of 3 σ and indirectly split departure δ i that is equivalent to shown in Fig. 6 is set to 2 μm With 3 μm, then synthesis split departure δ di is 3.6 μm.According to Figure 18, allow the design that split departure δ di is more than 3.6m μm 50% punch through voltage Δ Vp, the region of v50typ, is below 1.25V to δ di-, is below 0.425V to δ di+.That is, as Δ Vp, During v50typ 0.425V, δ di-and δ di+ is more than 3.6 μm.In order to make aperture opening ratio maximum, needs will be by light-proofness electrode structure The auxiliary capacitor become is set as the Min. of necessity, if the engineering management of split precision can be implemented with 3 σ, will allow for In split departure δ di-and δ di+, the value of a reigning side is set as 3 σ.

That be equivalent to 3 σ in the present embodiment is design 50% punch through voltage Δ Vp, the state of v50=0.425V.? Heavy load electric capacity Cload, max are 0.698pF, even if being Wmin-u according to Fig. 9 raceway groove width W, are also the electricity that enough can charge Hold.More than according to, the optimal pixel status of the present embodiment is, raceway groove width W=Wmin-u, maximum load electric capacity Cload, max For 0.698pF, design 50% punch through voltage Δ Vp, v50=0.425V.It addition, with fitting with reference to the amorphous silicon described in Figure 11 The split precision compensated when driving with break-through is equally 2.37 σ, this allowing, split departure δ di is 1.98 μm, allows split Departure is to be arranged by δ di+, and design 50% punch through voltage Δ Vp, v50typ are set as 1.53V.

Here, the break-through that carries out described in the present embodiment compensates design 50% punch through voltage that best pixel when driving is corresponding The value of Δ Vp, v50typ, ratio uses the TAOS's that illustrates of Figure 13-Figure 15 to be suitable for the non-best pixel compensated when driving of break-through Corresponding design 50% punch through voltage Δ Vp, the value of v50typ is little.That is, both raceway groove width W are the same, and thus design 50% is worn Logical voltage Δ Vp, the difference of the value of v50typ means the difference of the auxiliary capacitor Cs being made up of light-proofness electrode, if being suitable for break-through If non-compensation drives, aperture opening ratio can improve, and this is the new discovery obtained by the present invention.This is because, with reference to Figure 13 and Tu The slope of the M that the formula (4) according to the present invention described in 16 is tried to achieve, i.e. 50% punch through voltage Δ Vp, corresponding to the change of v50 The absolute value of the ratio η of good opposite electrode potential difference δ Vcom, opt, when break-through compensates and drives, than break-through, non-compensation is wanted when driving Greatly.

Winking

It follows that illustrate using the invention to reduce winking referring to the drawings.Figure 19 is to represent, by comparative example And the liquid crystal display dress that the amorphous silicon described in embodiments of the invention and TAOS use as the semiconductor layer of pixel TFT In putting, represent 50% punch through voltage Δ Vp, optimal opposite electrode potential difference δ Vcom, the opt change corresponding to the change of v50 The design 50% punch through voltage Δ Vp of the slope η of the straight line M represented by formula (4) of ratio, the figure of v50typ interdependence.

I.e., respectively with the slope of each straight line M in Fig. 8 and Figure 11 of being tried to achieve by simulation in amorphous silicon and logical in TAOS The slope crossing Figure 13 and Figure 16 cathetus M that the relational expression (4) of the present invention is tried to achieve is mapped.Figure 19 (A) is to represent the non-benefit of break-through Repay the situation of driving, add parameter Vgh=15V and Vgl=-2V used in embodiment in TAOS, represent Vgh=12V and Vgl Dashed line view during=-2V and Vgh=12V and Vgl=-6V.Equally, Figure 19 (B) is to represent that break-through compensates situation about driving, and adds Parameter Vgh=15V used in embodiment in upper TAOS and Vgl=-2V, represent Vgh=12V and Vgl=-2V and Vgh= Dashed line view during 12V and Vgl=-6V.

The non-situation compensating driving of break-through shown in Figure 19 (A), along with increase and the reduction of Vgl of Vgh, represents 50% Punch through voltage Δ Vp, the absolute value of the η of optimal opposite electrode potential difference δ Vcom, the opt change ratio corresponding to the change of v50 Increase, but its increase is the least, controls with the 0.6~0.7 of amorphous silicon same degree.The non-break-through of amorphous silicon compensates and drives Time dynamic, winking is the slightest, it is difficult to recognized by naked eyes, it is taken as that winking is the slightest in TAOS.

To this, the break-through shown in Figure 19 (B) compensates when driving, and the η's corresponding to the increase of Vgh and the reduction of Vgl is exhausted Relatively big to the increase of value, the absolute value of η sometimes than amorphous silicon time big.Amorphous silicon is suitable for break-through and compensates driving The practical situation of winking during situation is the degree that can be substantially recognized by naked eyes, it is taken as that the absolute value of η allow pole Limit is 1.5~about 2.0, preferably needs suppression in less than the 0.7 of break-through non-compensation driving level.That is, it needs to when design Optimal opposite electrode potential difference is controlled within tolerable limit, and the absolute value of η is controlled below 2.0.

Organic EL

Hereinafter the situation that the present invention is used for organic EL display is illustrated.Figure 20 is that most basic organic EL shows The outline equivalent circuit diagram of the pixel of showing device 100.The gate electrode of the TFT115 of first is connected to scan signal line 111, electric leakage Pole is connected to display signal line 113, and source electrode is connected to store the gate electrode of the TFT117 of electric capacity Cst and second.Second The drain electrode of TFT117 is connected to supply voltage Vcom1, and source electrode is connected to organic EL element i.e. LED119.That is, so-called by 2 The 2T1C type that individual TFT and 1 electric capacity are constituted.

During the selection of scan signal line 111, the TFT115 of first is ON state, is charged storage electric capacity Cst, The source electrode current potential (hereinafter referred to as pixel electrode current potential Vp1) of the TFT115 when first is with charging knot when drain electrode current potential is equal Bundle.At this moment being ON state due to pixel electrode current potential Vp1, the TFT117 of second, LED119 is applied in forward bias voltage drop, produces electricity Stream, produces EL luminous.Even if after ending during the selection of scan signal line 111, because storage electric capacity Cst, pixel electrode current potential Vp1 is kept, and the TFT117 of second maintains ON state, and electric current continues to flow into LED119.

At this moment, in order to make certain electric current continue to flow into LED119, the drain electrode current potential i.e. power supply electricity of the TFT117 of second Need in pressing Vcom1 during keeping to remain certain, but the independent value controlling supply voltage Vcom1 can make in each pixel Pixel structure complicates, and causes yield rate reduction etc., is therefore highly difficult.Therefore, power so that power supply electricity from external power source Pressure Vcom1 is generally certain at picture, controls to flow through LED119 by the most only controlling pixel electrode current potential Vp1 Current value.As a result, the electric current flowing through LED119 is controlled by the gate electrode potential of the TFT117 of second, its current value relative to Pixel electrode current potential Vp1 change is very sensitive.That is, the homogeneity and the stability that improve pixel electrode current potential Vp1 are extremely important.

The inhomogenous reason of pixel electrode current potential Vp1 is the display device of electric current inflow type, the most particularly second TFT117 is often ON state, and voltage stress can cause the migration of threshold voltage vt h.As countermeasure, having kind of a method is at each picture Element configures the compensation circuit being made up of multiple TFT and multiple electric capacity, this is proposed various circuit.But, compensate The importing of circuit result in the complication of pixel structure, therefore has reduction of causing the restriction in light extraction direction and yield rate etc. no Profit factor.Further, with in liquid crystal indicator, break-through compensates situation about driving, because being the compensation of capacitive junctions mould assembly, The value of each electric capacity due to split deviation etc. technique change and when design load migrates, sometimes can obtain intended compensation Effect, reduces the inner evenness of brightness on the contrary.

Further, as the situation of liquid crystal indicator, overcharge effect also brings along pixel electrode current potential Vp1 not Uniformity.Figure 21 is, owing to two electrodes of the parasitic capacitance between the grid leak of the TFT115 of first are respectively by scanning signal in Figure 20 The current electrode of line 111 and display signal line 113 carrys out applied voltage, therefore omits pixel electrode current potential Vp1 without impact, by the The raceway groove of the TFT117 of two and LED119 replace with variable resistance Rtft and Rel respectively.Figure 21 and expression liquid crystal indicator 10 Fig. 2 of equivalent circuit of pixel compare, the viewpoint that load capacitance is charged by the ON electric current of the TFT115 according to first, Ke Yizhi The pixel of road 2T1C type organic EL display and the pixel of liquid crystal indicator are equivalent.Based on same viewpoint, joining Put in the pixel compensating circuit being made up of multiple TFT and multiple electric capacity, if TFT is replaced to what electric capacity merged Words, then with the equivalence of 2T1C type.

It addition, eliminate in order to avoid figure complicates in figure 21, but scan signal line 111 and display signal line 113, and the power-supplying patch of variable resistance Rtft is still respectively provided with resistance, pixel region is formed rectangular, respectively joins Line crosses one another formation electric capacity.Therefore, it is added to the change of the signal potential of the current electrode of each distribution, due to the respective time Constant and distortion ground propagate.Therefore, in organic EL display also due to break-through and produce overcharge, as overcharge imitate Should, create inhomogeneities in the face of pixel electrode current potential Vp1.

In sum, with the situation of liquid crystal indicator 10 is identical or more very, in organic EL display, will connect The pixel electrode current potential Vp1 having the node of the gate electrode of the source electrode of the TFT115 of first and the TFT117 of second controls uniformly And the value of regulation is critically important.In order to reduce the reason of pixel electrode current potential Vp1 inhomogeneities, threshold that i.e. voltage stress causes The migration of threshold voltage Vth, enrolls the maneuver in pixel by extensive concern by compensating circuit, it is proposed that various circuit.

But, compensate the importing of circuit, have the yield rate caused with the complication of pixel structure and reduce and limit The unfavorable factor in light extraction direction etc., the most also has the composition compensating circuit caused by technique change and is unsatisfactory for compensating bar Part, causes the uniformity of pixel electrode current potential Vp1 to reduce.To this, to overcharge effect not implementation measure, using TAOS as pixel When TFT uses, the inhomogeneities of pixel electrode potential Vp1 may increase further.

In this case, the design techniques of the present invention does not results in the complication of pixel structure, and can realize overcharge The suppression of effect, by being used together the uniformity that can improve all pixel electrode current potential Vp1 with compensation circuit.Below to inciting somebody to action The present invention illustrates for the situation of organic EL display.

For liquid crystal indicator, it is desirable to be directed to the opposite electrode current potential Vcom of pixel electrode current potential Vp, improve brightness Uniformity.In the case of organic EL display, it is provided that supply voltage Vcom1, controlled by pixel electrode current potential Vp1 The ON electric current of the TFT117 of system second and the electric current being flowed into LED119.That is, for the supply voltage Vcom1 set, suitably Provide pixel electrode current potential Vp1, thus may decide that variable resistance Rtft and Rel and second TFT117 source electrode electricity Position Vq.The ON electric current of the TFT117 of second is determined by grid, source, the relative value of each electrode potential of leakage, is therefore conceived to power supply The change of voltage Vcom1, is equivalent to be conceived to the change of pixel electrode current potential Vp1.

Therefore, the pixel electrode current potential Vp1 in organic EL display is replaced to the picture for liquid crystal indicator 10 Element electrode potential Vp, it is stipulated that the pixel electricity in the relational expression relevant with opposite electrode current potential Vcom described in liquid crystal indicator 10 Electrode potential Vp.Here, the impact on image quality that the inhomogeneities of pixel electrode current potential Vp1 is caused is brightness irregularities etc. and quilt Naked eyes are recognized, its visibility in middle tone can improve.Therefore, by the pixel electrode current potential Vp table of maximum display brightness 50% It is shown as Vp, v50, it is desirable to the overcharge of suppression Vp, v50.

In the case of organic EL display, will not exist with the applied voltage polarity inversion of load capacitance The optimum of the opposite electrode current potential Vcom of local as liquid crystal indicator.Therefore, for the confession from scan signal line 111 The Vp, v50 (near) of the pixel that electricity electrode is nearest and the Vp of farthest pixel, v50 (far), if δ Vp is δ Vp=Vp, v50 (far)-Vp, v50 (near), by δ Vp and 50% punch through voltage Δ Vp, the relational expression of v50 is copied formula (3), is obtained formula (7).

δ Vp=(α Δ Vp, v50+ β) γ ... (7)

Here, 50% punch through voltage Δ Vp, v50 is expressed from the next.

Δ Vp, v50=(Cgs1, v50/Cload, v50) Δ Vg

Δ Vg=Vgh-Vgl

Cgs1, v50 and Cload, v50 be respectively picture brightness be the gate electrode of the TFT117 of the second of high-high brightness 50% The load capacitance corresponding for TFT115 of electric capacity Cgs1 and first between the grid source of the TFT115 of the first of current potential V50, Cload, v50 by Following formula represents.

Cload, v50=Cgs1, v50+Cst+Cgs2, v50+Cgd2, v50+Cother

As fixed capacity, storage electric capacity Cst is certain, parasitic capacitance Cgs between grid source and the parasitic electricity between grid leak Holding Cgd, according to the voltage of the parasitic capacitance of the TFT being applied to have MIS structure, its capacitance can change.Therefore V50 is corresponding Value is expressed as Cgs2, v50, Cgd2, v50, if the change that TFT is the capacitance corresponding to ON state applied voltage is relatively Little, can be regarded as certain value.Cother is all of electrode with pixel electrode current potential Vp same potential and be configured at its week The summation of the coupling electric capacity formed between the distribution enclosed and electrode etc..

Then, designing 50% punch through voltage Δ Vp, δ Vp corresponding for v50typ is expressed as δ Vp, typ, then Δ Vp, v50's Formula (4) is copied in the change of the δ Vp corresponding to change, formula (8) represent.

δ Vp=η (Δ Vp, v50-Δ Vp, v50typ)+δ Vp, typ... (8)

η is 50% punch through voltage Δ Vp, the ratio of the change of the δ Vp corresponding to the change of v50.

The higher limit allowing change of δ Vp is expressed as ξ+, lower limit be expressed as ξ-, 50% punch through voltage Δ Vp, v50 from The direction that the design load Δ Vp, v50typ of 50% punch through voltage reduce allow variable quantity δ (Δ Vp, v50)-, and Δ Vp, v50 Variable quantity δ (Δ Vp, v50)+be expressed as is allowed from the direction that Δ Vp, v50typ increase

δ (Δ Vp, v50)-=Δ Vp, v50typ-(Δ Vp, v50-) > 0

δ (Δ Vp, v50) +=(Δ Vp, v50+)-Δ Vp, v50typ > 0

With the situation of liquid crystal indicator is identical, if if being designed as meeting formula (5) and formula (6), overcharge causes Within the change of pixel electrode current potential Vp1 can be controlled in permissible range.Aforesaid formula (5) and formula (6) are expressed as follows again.

δ(δVp,v50)+≦{(ξ-)-(α·ΔVp,v50typ+β)γ}/η...(5)

δ(δVp,v50)-≦{(α·ΔVp,v50typ+β)γ-(ξ+)}/η...(6)

Here, ξ+with ξ-be is by meeting the value determined with product specifications that the inner evenness of brightness is relevant, each system Product are all different.

By using formula (5) and formula (6), even if the display device of active array type has field effect mobility it is More than 1cm2/Vs and the transistor of below 70cm2/Vs, it is also possible to the photoresist being designed in existing manufacturing process Manufacture under position split precision.Specifically, whether Δ Vp, v50typ that checking initially sets up meet formula (5), (6), are unsatisfactory for If then change Δ Vp, the control parameter of v50typ, i.e. gate electrode potential Vgh of ON state, the gate electrode potential of OFF state Any one in Vgl, parasitic capacitance Cgs and load capacitance Cload or multiple combination, so that its convergence.At this moment, Gate electrode potential Vgl of OFF state be technological parameter be therefore fixing, gate electrode potential Vgh of ON state cannot be critically Change, is therefore typically change parasitic capacitance Cgs and load capacitance Cload.

Now, organic EL display is proposed a lot of compensation driving methods, within the pixel and with compensate circuit and Not and with compensating circuit etc., kind has a lot.The most more is by the correction of the uniformity of the display picture brightness that is used for making corrections Current potential is appended to show signal potential, high limit of tolerance corresponding for difference δ Vp in thus can increasing the face of pixel electrode current potential Vp Value ξ+and lower limit ξ-respective absolute value, the driving method of this class all can cause cost to increase.Pixel electrode current potential Vp's Inhomogeneities is the biggest, or the picture brightness uniformity as product specifications is the highest, and correction current potential generative circuit can complicate, because of This makes cost increase.Increase to reduce cost, need to improve pixel electrode by the technology improving design and manufacturing process The uniformity of current potential Vp.At this moment, no matter either with or without and with compensation circuit, even implementing the picture brightness uniformity that makes corrections Current potential is appended to show the organic EL display compensating driving of signal potential, it is also possible to be not carried out compensating the state of driving Under by meeting formula (5), (6), or the absolute value of the η in formula (5), (6) is set in less than 2, thus improves pixel electrode The uniformity of current potential Vp, it is apparent that the present invention can be suitable for.

Further, used as described in Figure 21, at the TFT by first to load capacitance charging on this point, organic The pixel of EL display device is equivalent with the pixel of liquid crystal indicator, by the uniformity of the display picture brightness that is used for making corrections Liquid crystal indicator can also be suitable for for driving from principle by the compensation that correction current potential is appended on display signal potential.Cause This, even the correction current potential implementing the uniformity by the display picture brightness that is used for making corrections is appended to show on signal potential Compensate the liquid crystal indicator driven, when be not carried out compensating drive by meeting formula (5), (6), or exhausted by η To value design below 2, thus improve the uniformity of pixel electrode current potential, can suppress to be driven by compensation the cost caused to increase Add, it is apparent that the present invention can be suitable for.

Additionally further, the most independently control pixel electrode and right even having Putting the liquid crystal indicator of the structure of electrode, the inhomogeneities increase of pixel electrode current potential Vp can make generation opposite electrode current potential Circuit high pressureization and complication etc., cause cost to increase and yield rate reduces, and the most preferably pixel electrode current potential Vp has Relatively high uniformity.Therefore, even having and the most independently controlling pixel electrode and opposed The liquid crystal indicator of the structure of electrode, with under the state that all of opposite electrode is powered by same electric potential signal by meeting formula (5), (6), or the absolute value of η is designed below 2, thus can improve the uniformity of pixel electrode current potential Vp, therefore show So the present invention can be suitable for.

The above-mentioned specific embodiment as depicted to the present invention is illustrated, but the present invention be not limited in as Embodiment shown in figure, as long as the effect of the present invention can be realized, can use all known structures of the prior art.Enter One step, the relational expression providing α, β, γ, η in formula (3), formula (4), formula (7), formula (8) is not limited in the shape shown in this specification State, as long as the effect of the present invention can be realized, can use other different forms.

Claims (22)

1. a liquid crystal indicator, it is characterised in that: multi-strip scanning holding wire and a plurality of display signal line are mutually by insulation Film configure, that surrounded by described scan signal line and display signal line, be configured in rectangular each pixel region, tool Have: transistor, its include gate electrode that source electrode is connected with described scan signal line and with described display signal line phase The drain electrode connected, the field effect mobility of its semiconductor layer is more than or equal to 1cm2/ Vs and less than or equal to 70cm2/Vs;Picture Element electrode, it is connected with described source electrode;Auxiliary capacitance line, it configures substantially in parallel with described scan signal line;First Substrate, it contains auxiliary capacitor, described auxiliary capacitor by dielectric film at described pixel electrode, the extension of described pixel electrode And and the electrode that is electrically connected of described pixel electrode in any one and described auxiliary capacitance line between intersection region in, or Intersection region between person and adjacent epimere or the described scan signal line of hypomere is constituted;Second substrate, it is configured to Liquid crystal layer is clamped together with this first substrate;Opposite electrode, it clamps described liquid crystal layer with described together with described pixel electrode Pixel electrode is the most opposed and is configured on described first substrate or second substrate;
In the liquid crystal indicator of such active array type,
The current potential of described opposite electrode is expressed as Vcom, and described transistor gate electrode potential under ON state and OFF state is divided Not being expressed as Vgh and Vgl, between the grid source of described transistor, electric capacity and load capacitance are expressed as Cgs and Cload, now Punch through voltage Δ Vp is expressed as formula (1A),
Δ Vp=(Cgs/Cload) (Vgh-Vgl) ... (1A)
Picture brightness is that liquid crystal layer applied voltage during high-high brightness n% is expressed as Vn, the now punch through voltage table corresponding to Vn Being shown as Δ Vp, vn, the design load of this Δ Vp, vn is expressed as Δ Vp, vntyp, the flicker of Vn on the optional position on display picture Vcom time minimum is expressed as Vcom, opt, subtracts from the Vcom, opt of the farthest pixel of the current electrode from described scan signal line Removing the Vcom of nearest pixel, the value after opt is expressed as δ Vcom, opt, this δ Vcom, the design load of opt i.e. δ Vcom, typ table Being shown as formula (1B), wherein α, β, γ are respectively coefficient,
δ Vcom, typ=(α Δ Vp, vntyp+ β) γ ... (1B)
The higher limit allowing excursion of δ Vcom, opt and lower limit be expressed as ξ+and ξ-, described ξ+and ξ-correspondence Δ Vp, vn are expressed as Δ Vp, vn-and Δ Vp, vn+,
When the schedule of proportion of the variable quantity of δ Vcom, opt that the variable quantity of Δ Vp, vn is corresponding is shown as η, it meets formula (1C) and formula (1D),
(Δ Vp, vn+)-Δ Vp, vntyp { (ξ-)-(α Δ Vp, vntyp+ β) γ }/η ... (1C)
Δ Vp, vntyp-(Δ Vp, vn-) { (α Δ Vp, vntyp+ β) γ-(ξ+) }/η ... (1D),
The absolute value of described η is less than 2.
Liquid crystal indicator the most according to claim 1, it is characterised in that: described n is 50, and described Vn is V50, described Δ Vp, vntyp are Δ Vp, v50typ.
Liquid crystal indicator the most according to claim 1, it is characterised in that: the field effect mobility of described semiconductor layer More than or equal to 1.5cm2/ Vs and less than or equal to 50cm2/Vs。
Liquid crystal indicator the most according to claim 1, it is characterised in that: described semiconductor layer is unbodied metal oxygen Compound.
Liquid crystal indicator the most according to claim 1, it is characterised in that: described semiconductor layer is Organic substance.
Liquid crystal indicator the most according to claim 1, it is characterised in that: described liquid crystal indicator is not implemented break-through and is mended When repaying driving, the threshold voltage of described transistor is expressed as Vth, described Vth, Vgh, Vgl and Δ Vp, and the unit of vntyp is [V], the unit of field effect mobility [mu] eff is [cm2/ Vs], the unit of the timeconstantτ g of described scan signal line is [μ S], κ (τ g) represents that κ is the function of τ g, and " ^ " represents Exponentiation Sign, and loge represents that natural logrithm, described α, β, γ, η are
α=A exp (-1/ (B μ eff))+0.2
A={0.58exp (-1/Vgh)-0.591}Vth+{7.924exp (-1/Vgh)-7.23}
B=Ba{exp (Bb (Vgh-14))-1}+Bc
Ba=15exp (-0.455Vth)
Bb=0.00667Vth+0.01
Bc=1.2exp (-0.35Vth)-0.47
β=C exp (-1/ (D μ eff))-0.19
C=-0.002Vth+0.337exp (-1/Vgh)-0.148
D={0.06exp (-Vgh+14)+0.00042}exp (Vth)-0.0051Vgh+0.362
γ={ E.exp (-F/ τ g)+G τ g} ν c
E={-0.00032 μ eff+0.01 (exp (-1.17/Vth)+1) } Vgh+0.008 μ eff+0.722exp (-0.101Vth)
F={2.71exp (-0.0272 μ eff)+0.597exp (-1.37/Vth) }/Vgh+ (0.0667Vth+0.3) exp (- 0.268μeff)
G={-0.0479 μ eff+1.4exp (-1.35/Vth)+1.75}/Vgh+0.0012 μ eff+0.0701exp (- 0.301Vth)-0.1
ν c=0.620exp (0.0353Vgh) (-Vgl) ^ (-0.0203Vgh+0.275)
η=η 0 γ 0
η 0=P exp (-1/ Δ Vp, vntyp)+Q
P={0.115exp (-0.164Vgh) exp (Vth)-0.0061Vgh+0.460} μ eff^ (-0.559)
Q=exp (-1/ (μ eff+Qa))+Qb
Qa=0.128Vgh-0.005exp (0.2Vth+4.7)+0.35
Qb=(0.0008Vth+0.0183) Vgh-0.0554Vth-1.88
γ 0=ν e κ (τ g)/κ (τ g=2.5)
κ (τ g)=exp (-R/ τ g)+S τ g+T
R=Ra1 exp (Ra2 μ eff) exp (-1/ (Vgh-10))+0.5exp (-Rc2/ μ eff)+Rc3
Ra1=0.214exp (-1.37/Vth)+0.351
Ra2=0.153exp (-1.37/Vth)-0.216
Rc2=1.29exp (0.388Vth)
Rc3=0.544exp (0.0147Vth)-1
S={0.000376loge (μ eff)-0.0000667Vth-0.00123}Vgh+Sb
Sb=(0.00237Vth+0.0345) exp (Sb2 μ eff)
Sb2=0.00258exp (0.388Vth)-0.05
T=Ta1 Vgh μ eff^Ta2+Tb1 loge (μ eff)+Tb2
Ta1=0.007exp (-1.6/Vth)+0.0258
Ta2=0.0223exp (0.265Vth)-0.1
Tb1=-0.0001Vth+0.0597
Tb2=0.847exp (-0.0966Vth)-3.00
ν e=(-0.0242Vgh+1.17) (-Vgl) ^ (0.0006Vgh^1.96).
Liquid crystal indicator the most according to claim 1, it is characterised in that: described liquid crystal indicator is implemented break-through and is compensated During driving, the threshold voltage of described transistor is expressed as Vth, described Vth, Vgh, Vgl and Δ Vp, and the unit of vntyp is [V], the unit of field effect mobility [mu] eff is [cm2/ Vs], the unit of scan signal line timeconstantτ g is [μ s], κ (τ g) Representing that κ is the function of τ g, " ^ " represents Exponentiation Sign, and loge represents that natural logrithm, described α, β, η are
α=A μ eff+B
A=0.00001 [4exp (-0.462Vth)-15}Vgh+20.2exp (0.0361Vth)]
B=0.0001{ (4.33Vth+25.2) Vgh-203Vth+852}
β=C loge (μ eff)+D
C=0.0001 (16.2Vgh-0.6Vth-108)
D=-(0.0118Vth+0.105) loge (Vgh)+0.0374Vth+0.0625
η=η 0 γ 0
η 0=P exp (Δ Vp, vntyp)+Q
P=-Pa1 Vgh^ (Pa2) μ eff^ (Pb1 Vgh+Pb2)
Pa1=4exp (1.12Vth)+109
Pa2=-5exp (-1/ (0.0916Vth))-2.57
Pb1=0.00007Vth+0.0096
Pb2=-0.0146Vth-0.204
Q=-{ (0.0001Vth-0.0123) Vgh+0.0238Vth+1.08} μ eff^Qb
Qb=(4.46Vth+43.0) Vgh^ (-0.0289Vth-2.16)+0.0118Vth-0.185
γ 0=ν e κ (τ g)/κ (τ g=2.5)
κ (τ g)=exp (-R/ τ g)+S τ g+T
R=Ra1 exp (Ra2 μ eff) exp (-1/ (Vgh-10))+0.5exp (-Rc2/ μ eff)+Rc3
Ra1=0.214exp (-1.37/Vth)+0.351
Ra2=0.153exp (-1.37/Vth)-0.216
Rc2=1.29exp (0.388Vth)
Rc3=0.544exp (0.0147Vth)-1
S={0.000376loge (μ eff)-0.0000667Vth-0.00123}Vgh+Sb
Sb=(0.00237Vth+0.0345) exp (Sb2 μ eff)
Sb2=0.00258exp (0.388Vth)-0.05
T=Ta1 Vgh μ eff^Ta2+Tb1 loge (μ eff)+Tb2
Ta1=0.007exp (-1.6/Vth)+0.0258
Ta2=0.0223exp (0.265Vth)-0.1
Tb1=-0.0001Vth+0.0597
Tb2=0.847exp (-0.0966Vth)-3.00
ν e=(-0.0242Vgh+1.17) (-Vgl) ^ (0.0006Vgh^1.96).
8. an organic EL display, it is characterised in that: multi-strip scanning holding wire and a plurality of display on the substrate of insulating properties Holding wire is configured by dielectric film mutually, that surrounded by described scan signal line and display signal line, be configured to rectangular Each pixel region in, be configured with by the field effect mobility of semiconductor layer more than or equal to 1cm2/ Vs and being less than or equal to 70cm2The first transistor of/Vs, transistor seconds, storage electric capacity, power supply wiring and the LED element of organic material composition, described The gate electrode of the first transistor is connected with described scan signal line and display signal line respectively with drain electrode, described first crystal The source electrode of pipe is connected with the electrode of one end of described storage electric capacity and the gate electrode of described transistor seconds, and described second The electrode of the drain electrode of transistor and the other end of described storage electric capacity is connected with described power supply wiring, described second crystal The source electrode of pipe is connected with described LED element, in the organic EL display of such active array type,
The current potential of described power supply wiring is expressed as Vcom, the described scanning under ON state and OFF state of the described the first transistor The current potential of holding wire is expressed as Vgh and Vgl, and between the grid source of described the first transistor, electric capacity and load capacitance are expressed as Cgs and Cload, punch through voltage Δ Vp now are expressed as formula (2A),
Δ Vp=(Cgs/Cload) (Vgh-Vgl) ... (2A)
Picture brightness when being the n% of high-high brightness the gate electrode potential of described transistor seconds be expressed as Vp, vn, with this Vp, vn Corresponding punch through voltage is expressed as Δ Vp, vn, and the design load of this Δ Vp, vn is expressed as Δ Vp, vntyp, from from described scanning letter The Vp, vn of the pixel that the current electrode of number line is farthest deducts the Vp of nearest pixel, and the value after vn is expressed as δ Vp, and this δ Vp sets Evaluation i.e. δ Vp, typ are expressed as formula (2B), and wherein α, β, γ are respectively constant,
δ Vp, typ=(α Δ Vp, vntyp+ β) γ ... (2B)
The higher limit allowing excursion of δ Vp and lower limit be expressed as ξ+and ξ-, described ξ+and the Δ Vp, vn of ξ-correspondence Being expressed as Δ Vp, vn-and Δ Vp, vn+, the schedule of proportion of the variable quantity of the δ Vp that the variable quantity of described Δ Vp, vn is corresponding is shown as During η, it meets formula (2C) and formula (2D),
(Δ Vp, vn+)-Δ Vp, vntyp { (ξ-)-(α Δ Vp, vntyp+ β) γ }/η ... (2C)
Δ Vp, vntyp-(Δ Vp, vn-) { (α Δ Vp, vntyp+ β) γ-(ξ+) }/η ... (2D),
The absolute value of described η is less than 2.
Organic EL display the most according to claim 8, it is characterised in that: described n is 50, and described Δ Vp, vn are Δ Vp, v50, described Δ Vp, vntyp are Δ Vp, v50typ.
Organic EL display the most according to claim 8, it is characterised in that: the semiconductor layer of described the first transistor Field effect mobility more than or equal to 1.5cm2/ Vs and less than or equal to 50cm2/Vs。
11. organic EL displays according to claim 8, it is characterised in that: the semiconductor layer of described the first transistor For unbodied metal-oxide.
12. organic EL displays according to claim 8, it is characterised in that: the semiconductor layer of described the first transistor For Organic substance.
13. organic EL displays according to claim 8, it is characterised in that: described organic EL display is not implemented Break-through compensates when driving, and the threshold voltage of described the first transistor is expressed as Vth, described Vth, Vgh, Vgl and Δ Vp, The unit of vntyp is [V], and the unit of field effect mobility [mu] eff is [cm2/ Vs], the timeconstantτ of described scan signal line The unit of g is [μ s], and κ (τ g) represents that κ is the function of τ g, and " ^ " represents Exponentiation Sign, and loge represents natural logrithm, described α, β, γ, η are
α=A exp (-1/ (B μ eff))+0.2
A={0.58exp (-1/Vgh)-0.591}Vth+{7.924exp (-1/Vgh)-7.23}
B=Ba{exp (Bb (Vgh-14))-1}+Bc
Ba=15exp (-0.455Vth)
Bb=0.00667Vth+0.01
Bc=1.2exp (-0.35Vth)-0.47
β=C exp (-1/ (D μ eff))-0.19
C=-0.002Vth+0.337exp (-1/Vgh)-0.148
D={0.06exp (-Vgh+14)+0.00042}exp (Vth)-0.0051Vgh+0.362
γ={ E exp (-F/ τ g)+G τ g} ν c
E={-0.00032 μ eff+0.01 (exp (-1.17/Vth)+1) } Vgh+0.008 μ eff+0.722exp (-0.101Vth)
F={2.71exp (-0.0272 μ eff)+0.597exp (-1.37/Vth) }/Vgh+ (0.0667Vth+0.3) exp (- 0.268μeff)
G={-0.0479 μ eff+1.4exp (-1.35/Vth)+1.75}/Vgh+0.0012 μ eff+0.0701exp (- 0.301Vth)-0.1
ν c=0.620exp (0.0353Vgh) (-Vgl) ^ (-0.0203Vgh+0.275)
η=η 0 γ 0
η 0=P exp (-1/ Δ Vp, vntyp)+Q
P={0.115exp (-0.164Vgh) exp (Vth)-0.00610Vgh+0.460} μ eff^ (-0.559)
Q=exp (-1/ (μ eff+Qa))+Qb
Qa=0.128Vgh-0.005exp (0.2Vth+4.7)+0.35
Qb=(0.0008Vth+0.0183) Vgh-0.0554Vth-1.88
γ 0=ν e κ (τ g)/κ (τ g=2.5)
κ (τ g)=exp (-R/ τ g)+S τ g+T
R=Ra1 exp (Ra2 μ eff) exp (-1/ (Vgh-10))+0.5exp (-Rc2/ μ eff)+Rc3
Ra1=0.214exp (-1.37/Vth)+0.351
Ra2=0.153exp (-1.37/Vth)-0.216
Rc2=1.29exp (0.388Vth)
Rc3=0.544exp (0.0147Vth)-1
S={0.000376loge (μ eff)-0.0000667Vth-0.00123}Vgh+Sb
Sb=(0.00237Vth+0.0345) exp (Sb2 μ eff)
Sb2=0.00258exp (0.388Vth)-0.05
T=Ta1 Vgh μ eff^Ta2+Tb1 loge (μ eff)+Tb2
Ta1=0.007exp (-1.6/Vth)+0.0258
Ta2=0.0223exp (0.265Vth)-0.1
Tb1=-0.0001Vth+0.0597
Tb2=0.847exp (-0.0966Vth)-3.00
ν e=(-0.0242Vgh+1.17) (-Vgl) ^ (0.0006Vgh^1.96).
14. organic EL display according to claim 8, it is characterised in that: described organic EL display is implemented to wear When logical compensation drives, the threshold voltage of described the first transistor is expressed as Vth, described Vth, Vgh, Vgl and Δ Vp, vntyp Unit be [V], the unit of field effect mobility [mu] eff is [cm2/ Vs], the list of the timeconstantτ g of described scan signal line Position is [μ s], and κ (τ g) represents that κ is the function of τ g, and " ^ " represents Exponentiation Sign, and loge represents that natural logrithm, described α, β, η are
α=A. μ eff+B
A=0.00001 [4exp (-0.462Vth)-15}Vgh+20.2exp (0.0361Vth)]
B=0.0001{ (4.33Vth+25.2) Vgh-203Vth+852}
β=C loge (μ eff)+D
C=0.0001 (16.2Vgh-0.6Vth-108)
D=-(0.0118Vth+0.105) loge (Vgh)+0.0374Vth+0.0625
η=η 0 γ 0
η 0=P exp (Δ Vp, vntyp)+Q
P=-Pa1 Vgh^ (Pa2) μ eff^ (Pb1 Vgh+Pb2)
Pa1=4exp (1.12Vth)+109
Pa2=-5exp (-1/ (0.0916Vth))-2.57
Pb1=0.00007Vth+0.0096
Pb2=-0.0146Vth-0.204
Q=-{ (0.0001Vth-0.0123) Vgh+0.0238Vth+1.08} μ eff^Qb
Qb=(4.46Vth+43.0) Vgh^ (-0.0289Vth-2.16)+0.0118Vth-0.185
γ 0=ν e κ (τ g)/κ (τ g=2.5)
κ (τ g)=exp (-R/ τ g)+S τ g+T
R=Ra1 exp (Ra2 μ eff) exp (-1/ (Vgh-10))+0.5exp (-Rc2/ μ eff)+Rc3
Ra1=0.214exp (-1.37/Vth)+0.351
Ra2=0.153exp (-1.37/Vth)-0.216
Rc2=1.29exp (0.388Vth)
Rc3=0.544exp (0.0147Vth)-1
S={0.000376loge (μ eff)-0.0000667Vth-0.00123}Vgh+Sb
Sb=(0.00237Vth+0.0345) exp (Sb2 μ eff)
Sb2=0.00258exp (0.388Vth)-0.05
T=Ta1 Vgh μ eff^Ta2+Tb1 loge (μ eff)+Tb2
Ta1=0.007exp (-1.6/Vth)+0.0258
Ta2=0.0223exp (0.265Vth)-0.1
Tb1=-0.0001Vth+0.0597
Tb2=0.847exp (-0.0966Vth)-3.00
ν e=(-0.0242Vgh+1.17) (-Vgl) ^ (0.0006Vgh^1.96).
The manufacture method of the liquid crystal indicator of 15. 1 kinds of active array types, it is characterised in that: the liquid crystal of described active array type Display device is: multi-strip scanning holding wire and a plurality of display signal line are configured by dielectric film mutually, by described scanning signal That line and described display signal line are surrounded, be configured in rectangular each pixel region, have: transistor, its contain active electrical Gate electrode that pole is connected with described scan signal line and the drain electrode being connected with described display signal line, its semiconductor layer Field effect mobility is more than or equal to 1cm2/ Vs and less than or equal to 70cm2/Vs;Pixel electrode, it is connected with described source electrode; Auxiliary capacitance line, it configures substantially in parallel with described scan signal line;First substrate, it contains auxiliary capacitor, described auxiliary Electric capacity is being electrically connected by described pixel electrode, the extension of described pixel electrode and with described pixel electrode by dielectric film Electrode in any one and described auxiliary capacitance line between intersection region in, or and adjacent epimere or hypomere Intersection region between described scan signal line is formed;Second substrate, it is configured to together with described first substrate clamp liquid Crystal layer;Opposite electrode, it is the most opposed with described pixel electrode and configure that it clamps described liquid crystal layer together with described pixel electrode On described first substrate or described second substrate;
Described manufacture method comprises the following steps:
Current potential at described opposite electrode is expressed as Vcom, described transistor gate electrode potential under ON state and OFF state It is expressed as Vgh and Vgl, when between the grid source of described transistor, electric capacity and load capacitance are expressed as Cgs and Cload, logical Cross formula (1A) and determine the step of punch through voltage Δ Vp;
The punch through voltage that liquid crystal layer applied voltage is expressed as corresponding to Vn, Vn when the n% that picture brightness is high-high brightness represents For Δ Vp, vn, the design load of this Δ Vp, vn is expressed as Δ Vp, vntyp, and on the optional position on display picture, the flicker of Vn is Hour Vcom is expressed as Vcom, opt, deducts recently from the Vcom, opt of the farthest pixel of the current electrode from described scanning signal The Vcom of pixel, the value after opt is expressed as δ Vcom, when opt, α, β, γ are respectively coefficient, is determined described by formula (1B) The step of the design load of δ Vcom, opt i.e. δ Vcom, typ;
The higher limit allowing excursion of δ Vcom, opt and lower limit be expressed as ξ+and ξ-, described ξ+and ξ-correspondence Δ Vp, vn be expressed as Δ Vp, vn-and Δ Vp, vn+, the change of δ Vcom, opt that the variable quantity of described Δ Vp, vn is corresponding When the schedule of proportion of change amount is shown as η, it is judged that whether it meets formula (1C) and the step of formula (1D);
When being unsatisfactory for formula (1C) and formula (1D), the value to each parameter changes, and again judges whether to meet formula (1C) and formula (1D) step;
Wherein, formula (1A), formula (1B), formula (1C) and formula (1D) are respectively as follows:
Δ Vp=(Cgs/Cload) (Vgh-Vgl) ... (1A)
δ Vcom, typ=(α Δ Vp, vntyp+ β) γ ... (1B)
(Δ Vp, vn+)-Δ Vp, vntyp { (ξ-)-(α Δ Vp, vntyp+ β) γ }/η ... (1C)
Δ Vp, vntyp-(Δ Vp, vn-) { (α Δ Vp, vntyp+ β) γ-(ξ+) }/η ... (1D),
The absolute value of described η is less than 2.
16. manufacture method according to claim 15, it is characterised in that: described again judging whether meets formula (1C) and formula (1D) step contains the step of the value of change Cgs and Cload.
The manufacture method of the organic EL display of 17. 1 kinds of active array types, it is characterised in that: having of described active array type Machine EL display device is: on the substrate of insulating properties, multi-strip scanning holding wire and a plurality of display signal line are joined by dielectric film mutually Put, described scan signal line and described display signal line that surrounded, be configured in rectangular each pixel region, it is configured with By the field effect mobility of semiconductor layer more than or equal to 1cm2/ Vs and less than or equal to 70cm2The first transistor of/Vs, second Transistor, storage electric capacity, power supply wiring and the LED element of organic material composition, the gate electrode of described the first transistor and electric leakage Pole is connected with described scan signal line and display signal line respectively, the source electrode of described the first transistor and described storage electric capacity The electrode of one end and the gate electrode of described transistor seconds be connected, the drain electrode of described transistor seconds and described in deposit The electrode of the other end of storage electric capacity is connected with described power supply wiring, the source electrode of described transistor seconds and described LED element It is connected;
This manufacture method comprises the following steps:
Current potential at described power supply wiring is expressed as Vcom, sweeps described in when described the first transistor is under ON state and OFF state The current potential retouching holding wire is expressed as Vgh and Vgl, and between the grid source of described the first transistor, electric capacity and load capacitance represent respectively During for Cgs and Cload, determined the step of punch through voltage Δ Vp by formula (2A);
When the n% that picture brightness is high-high brightness, the gate electrode potential of described transistor seconds is expressed as Vp, vn, this Vp, vn Corresponding punch through voltage is expressed as Δ Vp, vn, and the design load of this Δ Vp, vn is expressed as Δ Vp, vntyp, from from described scanning letter The Vp, vn of the pixel that the current electrode of number line is farthest deducts the Vp of nearest pixel, and the value after vn is expressed as δ Vp, and α, β, γ divide Not Wei constant time, determined the step of the design load i.e. δ Vp of δ Vp, typ by formula (2B);
The higher limit allowing excursion of δ Vp and lower limit be expressed as ξ+and ξ-, described ξ+and the Δ Vp of ξ-correspondence, Vn is expressed as Δ Vp, vn-and Δ Vp, vn+, and the schedule of proportion of the variable quantity of the δ Vp that the variable quantity of this Δ Vp, vn is corresponding is shown as During η, it may be judged whether meet formula (2C) and the step of formula (2D);
When being unsatisfactory for formula (2C) and formula (2D), the value to each parameter changes, and again judges whether to meet formula (2C) and formula (2D) step;
Described formula (2A), formula (2B), formula (2C) and formula (2D) are respectively as follows:
Δ Vp=(Cgs/Cload) (Vgh-Vgl) ... (2A)
δ Vp, typ=(α Δ Vp, vntyp+ β) γ ... (2B)
(Δ Vp, vn+)-Δ Vp, vntyp { (ξ-)-(α Δ Vp, vntyp+ β) γ }/η ... (2C)
Δ Vp, vntyp-(Δ Vp, vn-) { (α Δ Vp, vntyp+ β) γ-(ξ+) }/η ... (2D),
The absolute value of described η is less than 2.
18. manufacture method according to claim 17, it is characterised in that: described again judging whether meets formula (2C) and formula (2D) step contains the step of the value of change Cgs and Cload.
19. according to the manufacture method described in any one of claim 15-18, it is characterised in that: described n is in the range of 15-70.
20. according to the manufacture method described in any one of claim 15-18, it is characterised in that: the electric field effect of described semiconductor layer Mobility is answered to be more than or equal to 1.5cm2/ Vs and less than or equal to 50cm2/Vs。
21. according to the manufacture method described in any one of claim 15-18, it is characterised in that: described semiconductor layer is amorphous Metal-oxide.
22. according to the manufacture method described in any one of claim 15-18, it is characterised in that: described semiconductor layer is Organic substance.
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