CN103762183B - Manufacturing technology for fan-out-type square chip level packaging - Google Patents

Manufacturing technology for fan-out-type square chip level packaging Download PDF

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Publication number
CN103762183B
CN103762183B CN201410045900.8A CN201410045900A CN103762183B CN 103762183 B CN103762183 B CN 103762183B CN 201410045900 A CN201410045900 A CN 201410045900A CN 103762183 B CN103762183 B CN 103762183B
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chip
resin
coating
chips
photosensitive resin
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CN103762183A (en
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陈�峰
耿菲
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The invention provides a manufacturing technology for fan-out-type square chip level packaging. The manufacturing technology comprises the steps of providing rectangular carrier chips with the larger size, coating the carrier chips with adhesive glue, sticking chips to the adhesive glue in a positive mode, coating the chips with second-kind insulating resin, filling a gap between the chips with the second-kind insulating resin, coating the chips with first-class photosensitive resin, covering the chips, forming a via hole leading to a chip bonding pad in the first-class photosensitive resin, depositing a seed layer, coating the seed layer with photoresist, forming an electroplating circuit electrically connected with the chip bonding pad in a graphics area exposed out of the photoresist, coating the carrier chips with a layer of solder resist ink which is made to cover the electroplating circuit, then exposing a metal bonding pad on the electroplating circuit out of the solder resist ink, and forming a solder ball on the metal bonding pad. According to the manufacturing technology for fan-out-type square chip level packaging, the manufacturing cost can be reduced, manufacturing difficulty in the technological process is reduced, and the surface uniformity of coated resin is improved.

Description

The manufacture craft of fan-out square chip level package
Technical field
The present invention relates to microelectronic package method, especially a kind of manufacture craft of fan-out square chip level package.
Background technology
With electronic product multifunction and the trend of miniaturization, high density microelectronic mounting technology is produced in electronics of new generation Main flow is increasingly becoming on product.In order to coordinate the development of electronic product of new generation, especially smart mobile phone, palm PC, ultrabook Deng the development of product, the size of chip is to density is higher, speed faster, the more low direction of smaller, cost develops.Fan-out-type The appearance of square piece level encapsulation technology (Fanout Panel Level Package, FOPLP), as fan-out-type wafer-level packaging skill The upgrade technique of art (Fanout Wafer Level Package, FOWLP), possesses broader development prospect.
Japanese J-Devices companies give a kind of fan-out-type wafer-level packaging in US20110309503A1 patents Preparation method, as shown in Figure 1.The patent main technique of J-Devices companies is as follows：
The first step：Tack coat is formed on substrate at certain intervals using binding agent；
Second step：Chip is placed with adhesive glue；
3rd step：The first insulating resin is coated, and window is outputed on resin, the pad on exposed chip；
4th step：By graphic plating and the method for photoetching, make and reroute layer（Redistribution Layer, RDL）, the pad on chip is drawn；
5th step：The second insulating barrier is made, and does opening and expose the metal for rerouting layer；
6th step：Over the second dielectric face makes soldered ball or salient point.
The technology is disadvantageous in that, the first insulating resin is coated in the 3rd step of technique, due to usual chip thickness More than 50 microns, so the thickness of coating insulating resin is wayward, it is unfavorable for the making of fine-line.And indivedual resins （Such as PBO, BCB）Price is higher, is unfavorable for cost control.
The content of the invention
It is an object of the invention to provide a kind of manufacture craft of fan-out square chip level package, can reduce manufacturing cost, And manufacture difficulty is reduced in technical process and the surface uniformity of coated with resins is improved.The technical solution used in the present invention It is that a kind of manufacture craft of fan-out square chip level package comprises the steps：
Step one, there is provided carrying tablet, pastes adhesive glue on carrying tablet；
Step 2, chip is just being attached in adhesive glue；
Step 3, posts coating Equations of The Second Kind insulating resin, Equations of The Second Kind insulating resin in the side of chip on carrying tablet Groove between filling chip, the height of Equations of The Second Kind insulating resin is not higher than the height at the top of chip；
Step 4, posts coating first kind photosensitive resin, first kind photosensitive resin in the side of chip on carrying tablet Chip is covered；
Step 5, forms the via for leading to chip bonding pad in first kind photosensitive resin；
Step 6, deposits one layer of Seed Layer in via and on first kind photosensitive resin；Photoetching is coated on the seed layer Glue, then causes to manifest the figure for making electroplating line on photoresist, using electric plating method, in the figure for manifesting The electroplating line of electrical connection chip bonding pad is formed in region；
Step 7, removes the Seed Layer of photoresist and photoresist bottom, retains the Seed Layer of electroplating line bottom；Carrying One layer of solder mask is coated on piece so that solder mask covers electroplating line；Then electroplating line is manifested on solder mask On metal pad.
Step 8, forms soldered ball on metal pad.
Further, in the step one, carrying tablet is rectangle, and material is glass, metallic plate or organic substrate.
Further, in the step 3, Equations of The Second Kind insulating resin is comprising epoxy resin, acryl resin, phenolic aldehyde tree The increasing layer material of fat or cyanate resin composition, bottom filler or capsulation material.
Further, in the step 3, coating Equations of The Second Kind insulating resin adopts the technology that serigraphy, slit are applied Cover, inkjet printing, vacuum pressing-combining, dispensing or impressing.
Further, in the step 3, Equations of The Second Kind insulating resin top is less than 0～15 micron at the top of chip.
Further, in the step 4, first kind photosensitive resin includes BCB, PBO, PSPI, polyimides, photosensitive type Epoxy resin or dry film.
Further, in the step 4, coat the technique that first kind photosensitive resin adopts include spin coating, spraying, roller coating, Serigraphy, slot coated, inkjet printing, rolling or vacuum pressing-combining.
Further, in the step 6, by splash-proofing sputtering metal or electroless copper plating technique, with first kind sense in via Deposited seed layer on photopolymer resin.
Further, in the step 8, by planting ball, printing, plating or chemical plating process soldered ball is formed.
Advantages of the present invention：
1). high performance chipses are fanned out to that technique is most of all to use first kind photosensitive resin, the resinoid include BCB, PBO、PSPI（Light-sensitive polyimide）, the material such as polyimides.First kind photosensitive resin has high resolution, is adapted to high frequency operation The features such as, have the disadvantage cost intensive.The present invention is epoxy resin, acryl resin, phenolic resin, triazine tree using main component , used as the filler of chip chamber, first kind photosensitive resin makes circuit and is fanned out to for the increasing layer material of fat etc., bottom filler or capsulation material Layer, while packaging technology precision is ensured, reduces manufacturing cost.
2). the present invention adopts two step gluing modes, can effectively improve the uniformity of resin coating.First by Equations of The Second Kind Groove between insulating resin filling chip, substantially can fill and lead up groove, and after filling, Equations of The Second Kind insulating resin top is less than core 0～15 micron of piece top, relative to thickness of the thickness after chip paster more than 50 microns, due to the coating of Equations of The Second Kind insulating resin The reduction of difference in height is coated afterwards, and when subsequently carrying out the coating of first kind photosensitive resin, manufacture difficulty is substantially reduced, and resin surface is uniform Property is greatly improved.
3). the relatively round blade technolgy of square piece technique has bigger production capacity, lower cost.The disk size of current main flow in the world It is the disk of 300mm diameters, about 113 square inches；The PCB substrate size of main flow for 500X600mm square piece, about 480 squares Inch；Sizes of the LCD 4 with line substrate for 650X830mm square piece, about 836 square inches.As can be seen here, using PCB substrate Some processes, processing dimension is 4.25 times of wafer；Using some processes of the LCD 4 with line, processing dimension is the 7.4 of wafer Times.The lifting of production capacity, can be greatly lowered manufacturing cost.
Description of the drawings
Fig. 1 is a kind of preparation method schematic diagram of fan-out-type wafer-level packaging of Japanese J-Devices companies.
Fig. 2 is to paste adhesive glue schematic diagram on the carrying tablet of the present invention.
Fig. 3 is the adhering chip schematic diagram of the present invention.
Fig. 4 is the coating Equations of The Second Kind insulating resin schematic diagram of the present invention.
Fig. 5 is the coating first kind photosensitive resin of the present invention and chip is covered into schematic diagram.
Fig. 6 A are the making via schematic diagram of the present invention.
Fig. 6 B are the via of the present invention less than schematic diagram during chip bonding pad.
Fig. 6 C are the via of the present invention more than schematic diagram during chip bonding pad.
Fig. 7 is the making Seed Layer and electroplating line schematic diagram of the present invention.
Fig. 8 is the coating solder mask of the present invention, and the metal pad manifested on solder mask on electroplating line is illustrated Figure.
Fig. 9 is the making soldered ball schematic diagram of the present invention.
Figure 10 is the flow chart of the present invention.
Specific embodiment
With reference to concrete drawings and Examples, the invention will be further described.
The manufacture craft of fan-out square chip level package proposed by the invention, specifically includes following step：
Step one, as shown in Figure 2, there is provided carrying tablet 101, pastes adhesive glue 102 on carrying tablet 101；
In this step, due to the side's of carrying out chip size package, therefore the carrying tablet of the larger rectangle of the preferred dimension of carrying tablet 101, The material of carrying tablet 101 is the flat boards such as glass, metallic plate or organic substrate；Specifically can be by serigraphy or dispensing, hot pressing, narrow The techniques such as seam coating, inkjet printing, vacuum pressing-combining, rolling, paste adhesive glue 102.
Step 2, as shown in figure 3, chip 103 is just being attached in adhesive glue 102 by chip mounter, i.e. the back side of chip 103 Fit with adhesive glue 102.
Step 3, as shown in figure 4, posting on carrying tablet 101 coat in the side of chip 103 Equations of The Second Kind insulating resin 104, the groove between the filling chip 103 of Equations of The Second Kind insulating resin 104；Equations of The Second Kind insulating resin 104 includes increasing layer material （Build-up）, bottom filler（Underfill）Or capsulation material；The height of Equations of The Second Kind insulating resin 104 is not higher than chip 103 and pushes up The height in portion, it is preferable that the top of Equations of The Second Kind insulating resin 104 is less than 0～15 micron at the top of chip 103；
In this step, the predominantly inexpensive resin with insulating effect of Equations of The Second Kind insulating resin 104, main component can Being the compositions such as epoxy resin, acryl resin, phenolic resin, cyanate resin, or with the addition of the fillers such as silica, ceramic powder Above-mentioned resin or modified resin.Product includes increasing layer material, bottom filler（Underfill）Or capsulation material.Coating processes can Being the techniques such as serigraphy, slot coated, inkjet printing, vacuum pressing-combining, dispensing, impressing.
Step 4, as shown in figure 5, posting on carrying tablet 101 coat in the side of chip 103 first kind photosensitive resin 107, first kind photosensitive resin 107 includes that the photosensitive polyamides of BCB benzocyclobutenes, PBO polyparaphenylene's benzo dioxazoles, PSPI is sub- The high-res photosensitive materials such as amine, polyimides, photosensitive type epoxy resin, dry film；First kind photosensitive resin 107 is by chip 103 Cover；Coating processes can be spin coating, spraying, roller coating, serigraphy, slot coated, inkjet printing, rolling, vacuum pressing-combining Etc. technique.
Step 5, as shown in Fig. 6 A, Fig. 6 B, Fig. 6 C, forms in first kind photosensitive resin 107 and leads to chip bonding pad 106 Via 108；
As shown in Figure 6A, first kind photosensitive resin 107（It is BCB, PBO, PSPI, polyimides, photosensitive type epoxy resin, dry The materials such as film）Through techniques such as photoetching, development, solidifications, the via 108 for leading to chip bonding pad 106 is formed wherein.
Show in Fig. 6 B, when the size of chip bonding pad 106 is than larger, be easy to form the via for leading to chip bonding pad 106 108, the diameter of via 108 is less than the diameter of chip bonding pad 106.Chip protection layer 105 is that chip 103 to be packaged is carried （Chip producer has made chip protection layer 105）.
Show in Fig. 6 C, when the size of chip bonding pad 106 is smaller, forms via 108 in the range of chip bonding pad 106 and compare It is more difficult, then consider via 108 bottom size be more than chip bonding pad 106, via 108 with diameter greater than chip bonding pad 106 diameter.
Step 6, as shown in fig. 7, depositing one layer of Seed Layer 109 in via 108 and on first kind photosensitive resin 107； Photoresist 110 is coated in Seed Layer 109, then causes to manifest the figure for making electroplating line 111 on photoresist 110 Shape, using electric plating method, forms the electroplating line 111 of electrical connection chip bonding pad 106 in the graphics field for manifesting；
In this step, splash-proofing sputtering metal can be passed through（Material can be Al, Au, Cr, Co, Ni, Cu, Mo, Ti, Ta, Ni-Cr, The alloy material of the materials such as Co-Ni, Co-Cr, W or more material）Or the technique such as electroless copper plating, in the neutralization of via 108 the Deposited seed layer 109 on one class photosensitive resin 107.Then in the applied atop photoresist 110 of Seed Layer 109（Photoresist can be It is liquid, or film-form）, contraposition exposure is carried out in litho machine by using egative film, make through techniques such as developments Obtain and the figure for making electroplating line 111 is manifested on photoresist 110.Using electric plating method, in the graphics field for manifesting Form electroplating line 111（Reroute structure）, the electrical connection chip bonding pad 106 of electroplating line 111.
Step 7, as shown in figure 8, removing the Seed Layer 109 of photoresist 110 and photoresist bottom, retains electroplating line 111 The Seed Layer 109 of bottom；One layer of solder mask 113 is coated on carrying tablet 101 so that solder mask 113 covers electroplating line 111；
Then contraposition exposure is carried out in litho machine using egative film, through techniques such as developments, is appeared on solder mask 113 The metal pad 112 gone out on electroplating line 111.
Step 8, as shown in figure 9, forming weldering by planting the techniques such as ball, printing, plating, chemical plating on metal pad 112 Ball 114.

Claims (1)

1. a kind of manufacture craft of fan-out square chip level package, it is characterised in that comprise the steps：
Step one, there is provided carrying tablet (101), pastes adhesive glue (102) on carrying tablet (101)；
Step 2, chip (103) is just being attached in adhesive glue (102)；
Step 3, posts on carrying tablet (101) and coat in the side of chip (103) Equations of The Second Kind insulating resin (104), and second Groove between class insulating resin (104) filling chip (103), the height of Equations of The Second Kind insulating resin (104) is not higher than chip (103) height at the top of；
Step 4, posts on carrying tablet (101) and coat in the side of chip (103) first kind photosensitive resin (107), and first Class photosensitive resin (107) covers chip (103)；
Step 5, forms the via (108) for leading to chip bonding pad (106) in first kind photosensitive resin (107)；
Step 6, deposits one layer of Seed Layer (109) on via (108) neutralization first kind photosensitive resin (107)；In Seed Layer (109) photoresist (110) is coated on, then causes to manifest the figure for making electroplating line (111) on photoresist (110) Shape, using electric plating method, forms the electroplating line (111) of electrical connection chip bonding pad (106) in the graphics field for manifesting；
Step 7, removes the Seed Layer (109) of photoresist (110) and photoresist bottom, retains the kind of electroplating line (111) bottom Sublayer (109)；One layer of solder mask (113) is coated on carrying tablet (101) so that solder mask (113) covers electroplating line (111)；
Then the metal pad (112) on electroplating line (111) is manifested on solder mask (113)；
Step 8, forms soldered ball (114) on metal pad (112)；
In the step one, carrying tablet (101) is rectangle, and material is glass, metallic plate or organic substrate；
In the step 3, Equations of The Second Kind insulating resin (104) top is less than 0～15 micron at the top of chip (103)；
In the step 3, Equations of The Second Kind insulating resin (104) is comprising epoxy resin, acryl resin, phenolic resin or triazine The increasing layer material of resinous principle, bottom filler or capsulation material；
In the step 3, coating Equations of The Second Kind insulating resin (104) adopts the technology that serigraphy, slot coated, ink-jet are beaten Print, vacuum pressing-combining, dispensing or impressing；
In the step 6, by splash-proofing sputtering metal or electroless copper plating technique, in via (108) first kind photosensitive resin is neutralized (107) deposited seed layer (109) on；
In the step 4, first kind photosensitive resin (107) includes BCB, PBO, PSPI, polyimides, photosensitive type epoxy resin Or dry film；
In the step 4, coating the technique of first kind photosensitive resin (107) employing includes spin coating, spraying, roller coating, screen printing Brush, slot coated, inkjet printing, rolling or vacuum pressing-combining；
In the step 8, by planting ball, printing, plating or chemical plating process soldered ball (114) is formed.
CN201410045900.8A 2014-02-08 2014-02-08 Manufacturing technology for fan-out-type square chip level packaging Active CN103762183B (en)

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CN113161249A (en) * 2021-03-31 2021-07-23 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113380638A (en) * 2021-05-21 2021-09-10 苏州通富超威半导体有限公司 Method for setting through hole on packaging body and method for preparing packaging body

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TWI245350B (en) * 2004-03-25 2005-12-11 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer
US9196509B2 (en) * 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging

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