CN103745965B - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN103745965B CN103745965B CN201310656037.5A CN201310656037A CN103745965B CN 103745965 B CN103745965 B CN 103745965B CN 201310656037 A CN201310656037 A CN 201310656037A CN 103745965 B CN103745965 B CN 103745965B
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- Prior art keywords
- metal coupling
- pin
- semiconductor chip
- metal
- opening
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A packaging structure comprises: a plurality of separated pins, wherein an opening is formed between adjacent pins; first metal protrusion blocks arranged on the surfaces of the pins; solder layers covering the tops and side walls of the first metal protrusion blocks; and a semiconductor chip, wherein the surface of the semiconductor chip is provided with bonding pads. Each bonding pad is provided with a second metal protrusion block. The semiconductor chip is inversely arranged above the pins. The second metal protrusion blocks on the semiconductor chip are welded with the first metal protrusion blocks on the pins through the solder layers. The integration level of the packaging structure is high.
Description
Technical field
The present invention relates to field of semiconductor package, particularly to a kind of semiconductor package.
Background technology
Towards miniaturization, portable, the ultrathin with electronic product such as mobile phone, notebook computer etc., multimedization and
The inexpensive direction meeting public demand is developed, the packing forms of high density, high-performance, high reliability and low cost and its assembling
Technology has obtained quick development.Compared with the packing forms such as expensive bga (ball grid array), in recent years soon
The novel encapsulated technology of speed development, such as four side flat non-pin qfn (quad flat no-leadpackage) encapsulation, due to it
There is good hot property and electrical property, size be little, low cost and high production rate etc. are numerous, caused microelectronics envelope
One new revolution of dress technical field.
Fig. 1 is the structural representation of existing qfn encapsulating structure, and described qfn encapsulating structure includes: semiconductor chip 14,
On described semiconductor chip 14, there is pad 15；Pin 16 (lead frame), described pin 16 is around described semiconductor chip 14
Surrounding arrangement；Plain conductor 17, plain conductor 17 is by the pad 15 of semiconductor chip 14 and around described semiconductor chip 14
Pin 16 electrically connect；Capsulation material 18, semiconductor chip 15, metal wire 17 and pin 16 are sealed by described capsulation material 18,
The surface exposure of pin 16 in the bottom surface of capsulation material, realizes being electrically connected of semiconductor chip 14 and external circuit by pin 16
Connect.
The volume that existing encapsulating structure occupies is larger, is unfavorable for the raising of encapsulating structure integrated level.
Content of the invention
The problem that the present invention solves is how to reduce the volume that encapsulating structure occupies.
For solving the above problems, the present invention provides a kind of forming method of encapsulating structure, comprising: provide leadframe metal
Layer；Etch described leadframe metal layer, form some discrete pins, there is between adjacent leads opening；Surface in pin
Form the first metal coupling；Form solder layer at the top of the first metal coupling and sidewall surfaces；Semiconductor chip is provided, described
The surface of semiconductor chip is formed with pad, and described pad is formed with the second metal coupling；Semiconductor chip is inverted in drawing
Above foot, the second metal coupling on semiconductor chip and the solder layer of the first metal lug surface are welded together.
Optionally, the forming process of described pin is: described leadframe metal layer includes first surface and and first surface
Relative second surface, the first surface of etch lead frame metal level, form some first openings in leadframe metal layer；Carve
The second surface of erosion leadframe metal layer, forms some second openings, the first opening and the second opening in leadframe metal layer
Mutually run through, the first opening and the second opening constitute opening, be pin between adjacent apertures.
Optionally, before forming the first opening or the second opening, also include: in the first table of described leadframe metal layer
Face forms the first patterned mask layer；Form the mask layer of second graphical in the second surface of described leadframe metal layer.
Optionally, the width of described first opening is less than the width of the second opening, and described first metal coupling is located at pin
First surface on.
Optionally, etch the surface of pin, form groove in pin, form the first metal coupling in groove, described
The top surface of the first metal coupling is higher than the surface of slot opening.
Optionally, the width of described first metal coupling is less than the width of groove.
Optionally, described solder layer also covers side wall and the lower surface of the groove of the first metal coupling both sides.
Optionally, described solder layer also covers side wall and lower surface, the Yi Jiyin of the groove of the first metal coupling both sides
The part surface of foot.
Optionally, the technique forming described solder layer is screen printing.
Optionally, described second metal coupling is soldered ball or metal column, or the weldering including metal column and metal column top
Ball.
Optionally, the solder layer of the second metal coupling on semiconductor chip and the first metal lug surface is welded on one
The technique rising is reflux technique.
Optionally, also include: formed and seal described semiconductor chip, the first metal coupling, the second metal coupling and fill
The plastic packaging layer of full gate mouth.
Present invention also offers a kind of encapsulating structure, comprising: some discrete pins, there is between adjacent leads opening；
The first metal coupling on the surface of described pin；Cover the solder layer of described first metal coupling top and side wall；Half
Conductor chip, the surface of described semiconductor chip has and has pad, and described pad has the second metal coupling, semiconductor chip
It is inverted in above pin, the second metal coupling on semiconductor chip is welded by solder layer with the first metal coupling on pin
Together.
Optionally, described opening includes the first opening mutually running through and the second opening, and the width of described first opening is little
Width in the second opening.
Optionally, described first metal coupling is located on the end surface away from the second opening of pin.
Optionally, the surface of described pin has groove, and the first metal coupling is located in groove, described first metal coupling
Top surface be higher than groove open surfaces.
Optionally, the width of described first metal coupling is less than the width of groove.
Encapsulating structure as claimed in claim 17 is it is characterised in that described solder layer also covers the first metal coupling two
The side wall of the groove of side and lower surface.
Optionally, described solder layer also covers side wall and lower surface, the Yi Jiyin of the groove of the first metal coupling both sides
The part surface of foot.
Optionally, also include: seal described semiconductor chip, the first metal coupling, the second metal coupling and fill full gate
The plastic packaging layer of mouth.
Compared with prior art, technical scheme has the advantage that
The encapsulation of the present invention, semiconductor chip is inverted in above pin, by the first metal coupling, solder layer and the second gold medal
Pad on semiconductor chip is electrically connected with the pin and is by the attachment structure belonging to projection composition, is arranged on pin with respect to existing
The encapsulating structure being connected by plain conductor pad semiconductor chip on around semiconductor chip and then with pin, the present invention
The horizontal area that the encapsulating structure of embodiment occupies reduces, the small volume of whole encapsulating structure.In addition, being formed on pin
First metal coupling, in encapsulation process, on the one hand, the presence of the first metal coupling, when being inverted in drawing semiconductor chip
When on foot, described metal coupling can play the effect of positioning, and on the other hand, the presence of the first metal coupling, compared to will partly lead
The second metal coupling on body chip is directly welded on pin, after forming the first metal coupling, is being welded on pin
When, the gradient steepening of the attachment structure between semiconductor chip and pin, the area of the pin surface that attachment structure occupies reduces,
Another further aspect, the presence of the first metal coupling is so that the distance between semiconductor chip and pin increase, described forming sealing
When semiconductor chip, the plastic packaging layer of the first metal coupling, solder layer and the second metal coupling, prevent in semiconductor chip and pin
Between plastic packaging layer in form the defect such as space.
Further, described opening includes the first opening and the second opening, and the width of the first opening is less than the width of the second opening
Degree, the area of the first surface of the pin of formation is more than the area of second surface, during encapsulation, in the first table of pin
Form metal coupling on face, because the area of the first surface of pin is larger, the first metal is being formed using lead key closing process
During projection, the first surface of pin can bear larger pressure and have larger contact area, reduce and adopt wire bonding
Technique formed the first metal coupling difficulty, the area of the second surface of pin less so that adjacent leads second surface it
Between distance larger, when the second surface of pin is connected with external circuit (such as pcb plate circuit), prevent between adjacent leads
Short circuit.
Further, the surface in pin formed fluted, described first metal coupling be located at groove in, described first metal
The top surface of projection is higher than the open surfaces of groove, and the width of the first metal coupling is less than the width of groove so that the first gold medal
The both sides belonging to projection have part recess not covered by the first metal coupling, during encapsulation, at the first metal coupling top
When forming solder layer with side wall, solder layer can cover the side wall of the groove of the first metal coupling both sides and lower surface so that
Solder layer is increased with the contact area of pin and the first metal coupling, improves formation between Subsequent semiconductor chip and pin
Adhesion and mechanical stability between attachment structure and pin.
Brief description
Fig. 1 is the cross-sectional view of prior art encapsulating structure；
Fig. 2～Fig. 8 is the cross-sectional view of embodiment of the present invention encapsulating structure forming process.
Specific embodiment
The integrated level of existing encapsulating structure is relatively low, refer to Fig. 1, and the pin 16 in existing encapsulating structure is cincture
It is arranged in semiconductor chip 14 around, the pad 15 on semiconductor chip 14 needs the pin by plain conductor 17 and surrounding
16 electrical connections, so that the volume that entirely encapsulating structure occupies is larger, are unfavorable for the raising of encapsulating structure integrated level.
The invention provides a kind of encapsulating structure, semiconductor chip is inverted in above pin, second on semiconductor chip
Metal coupling is welded together by solder layer with the first metal coupling on pin, and the volume that encapsulating structure occupies reduces, and carries
The high integrated level of encapsulating structure.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiment of the present invention in detail, for purposes of illustration only, schematic diagram can disobey general ratio
Make partial enlargement, and described schematic diagram is example, its here should not limit the scope of the invention.Additionally, in reality
The three-dimensional space of length, width and depth should be comprised in making.
Fig. 2～Fig. 8 is the cross-sectional view of embodiment of the present invention encapsulating structure forming process.
First, refer to Fig. 2, leadframe metal layer 100 is provided.
Described leadframe metal layer 100 is subsequently formed pin, described leadframe metal layer 100 have first surface 11 and with
The relative second surface of first surface 11 12.
The material of described leadframe metal layer 100 is metal or alloy.The material of described leadframe metal layer 100 can be
In w, al, cu, ti, ag, au, pt, ni one or more.
Described leadframe metal layer 100 can be the metal of monolayer or the stacked structure of multiple layer metal.
Described leadframe metal layer 100 includes some lead areas, and around the outer peripheral areas of described lead areas, (in figure is not
Illustrate), described lead areas is subsequently formed some discrete pins, and described outer peripheral areas are used for fixing and supporting some discrete
Pin, the side of pin is contacted with outer peripheral areas, and other three sides of pin are hanging, subsequently after forming encapsulating structure, by cutting
Prescind except the outer peripheral areas of lead metal level 100, discharge some discrete pin of encapsulating structure.Then, refer to Fig. 3,
Etch described leadframe metal layer 100 (with reference to Fig. 2), form some discrete pins 103, have out between adjacent leads 103
Mouthful.
The forming process of described pin 103 is: forms the first figure on the first surface 11 of described leadframe metal layer 100
The mask layer (not shown) of shape；With the described first patterned mask layer as mask, etch lead frame metal level 100
First surface 11, forms some first openings 102 in leadframe metal layer 100；In described leadframe metal layer 100 second
The mask layer (not shown) of second graphical is formed on surface 12；With the mask layer of described second graphical as mask, carve
The second surface 12 of erosion leadframe metal layer 100, forms some second openings 101, the first opening in leadframe metal layer 100
102 and second opening 101 mutually run through, the first opening 102 and the second opening 101 constitute opening, are pin between adjacent apertures
103.
The material of the mask layer of described first patterned mask layer or second graphical can for epoxide-resin glue or its
His suitable material.The formation process of the mask layer of the first patterned mask layer or second graphical is patch dry film technique or pressure
Print technique.The formation process of the mask layer of described first patterned mask layer or second graphical can also be spraying or spin coating
Technique.
The width of described first opening 102 be less than the second opening 101 width so that formed pin 103 the first table
The area in face 11 is more than the area of second surface 12, subsequently forms metal coupling on the first surface of pin 103, due to pin
The area of 103 first surface 11 is larger, when the first metal coupling is formed using lead key closing process, the first of pin 103
Surface energy is born larger pressure and is had larger contact area, reduces convex using lead key closing process formation the first metal
The difficulty of block, the area of the second surface 12 of pin 103 less so that the distance between second surface 12 of adjacent leads 103
Larger, when subsequently the second surface 12 of pin 103 being connected with external circuit (such as pcb plate circuit), prevent adjacent leads 103
Between short circuit, in addition, the width of the first opening 102 and the second opening 101 is different, subsequently in the first opening 102 and second
Fill during full capsulation material the increasing number so that pin 103 and the contact surface of plastic packaging layer in opening 101, pin be not easy from
Come off in capsulation material.It should be noted that described first opening 102 can the second opening 101 formed before or after shape
Become.
Also include: the surface of etching pin 103 (is subsequently formed on the surface of metal coupling or the first surface of pin
11), form groove 105 in pin 103.Described groove 105 can the first opening 102 formed before or formed after shape
Become.Before forming groove 105, the first surface 11 of described pin 103 forms the 3rd patterned mask layer, with described
3rd patterned mask layer is the first surface 11 of pin 103 described in mask etching, forms groove 105.Subsequently in groove 105
Interior formation the first metal coupling.
In other embodiments of the invention, after forming the first opening 102 and the second opening 101, can also be in institute
State one layer of dry film thin film of formation on the second surface 12 of pin 103, the second surface 12 of pin 103 is covered by described dry film thin film
Lid, when subsequently filling capsulation material in the opening, prevents the flash of the lower surface to pin 103 for the capsulation material, subsequently in shape
After becoming plastic packaging layer, described dry film thin film is removed.
Then, refer to Fig. 4, form the first metal coupling 107 on the surface of pin 103.
In the present embodiment, form the first metal coupling 107, described first metal coupling in the first surface 11 of pin 103
107 are located in groove 105, and the top surface of described first metal coupling 107 is higher than the open surfaces of groove 105, the first metal
The width of projection 107 is less than the width of groove 105 so that the both sides of the first metal coupling 107 have part recess 105 not to be coated to
Lid, subsequently when solder layer is formed on the first metal coupling 107 top and side wall, solder layer can cover the first metal coupling 107
The side wall of the groove 105 of both sides and lower surface are so that the contact area of solder layer and pin 103 and the first metal coupling 107
Increase, improve adhesion and machinery between the attachment structure being formed between Subsequent semiconductor chip and pin and pin 103 steady
Qualitative.
The material of described first metal coupling 107 can be in aluminum, nickel, stannum, tungsten, platinum, copper, titanium, chromium, tantalum, gold, silver
Plant or several.
Form described first metal coupling 107 and can adopt lead key closing process or typography.The present invention other
In embodiment, described metal coupling 107 can also be formed using other suitable techniques.
In the embodiment of the present invention, the first metal coupling 107, in follow-up encapsulation process, a side are formed on pin 103
Face, the presence of the first metal coupling 107, when when semiconductor chip is inverted on pin, described first metal coupling 107 energy
Play the effect of positioning, on the other hand, the presence of the first metal coupling 107, compared to by the second metal on semiconductor chip
Projection is directly welded on pin 103, after the first metal coupling 107 is formed on pin 103, when being welded, quasiconductor
The gradient steepening of the attachment structure between chip and pin 103, the area on pin 103 surface that attachment structure occupies reduces, then
On the one hand, the presence of the first metal coupling 107, so that the distance between semiconductor chip and pin 103 increase, is forming sealing
When described semiconductor chip, the plastic packaging layer of the first metal coupling 107, solder layer 103 and the second metal coupling, prevent in quasiconductor
Form the defects such as space in plastic packaging layer between chip and pin.
The detailed process that wire bonding forms the first metal coupling 107 is: metal wire is passed through the bonding head of bonding apparatus
(or chopper capillary tube in bonding head) reaches its top；Produce electric spark by oxyhydrogen flame or electrical system to make to stretch in bonding head
The metal wire melting going out forms metal coupling；Metal coupling is pressed together on the first surface 11 of pin 103 bonding head；Bonding head
In chopper cut-out metal wire so that metal coupling is retained on the first surface of pin 103, formed the first metal coupling 107.
The metal coupling being formed by lead key closing process, process is simple, efficiency is higher, and will not bring pollution.
Using the process that typography forms the first metal coupling 107 it is: by with meshed web plate laminating pin 103
First surface 11, mesh exposes the part first surface 11 of pin 103；Mesh is brushed as metal filled material (such as: scolding tin
Deng)；Then, remove web plate, the first metal coupling 107 is formed on the first surface 11 of pin 103.
Then, refer to Fig. 5, form solder layer 108 in the side wall of described first metal coupling 107 and top surface.
When subsequently semiconductor chip being inverted in pin 103 top, by solder layer 108 by the pad of semiconductor chip
The second metal coupling weld together with the first metal coupling 107 on pin 103.
In the present embodiment, described solder layer 108 also covers the groove 105 (with reference to Fig. 4) of the first metal coupling 107 both sides
Side wall and lower surface, because groove 105 has bottom and side wall, solder layer covers the groove of the first metal coupling 107 both sides
The side wall of 105 (with reference to Fig. 4) with during lower surface so that solder layer 105 contact with the first metal coupling 107 and pin 103
Area increases, and is subsequently formed with the first metal coupling, solder layer and the second metal coupling between semiconductor chip and pin 103
During the attachment structure constituting, improve adhesion between the attachment structure being formed between semiconductor chip and pin and pin 103
And mechanical stability.
In the other embodiment of the present invention, described solder layer except cover the first metal coupling both sides groove side wall and
Lower surface, described solder layer also covers the part surface of the pin of the first metal coupling both sides, when forming attachment structure, makes
Obtain adhesion and mechanical stability between attachment structure and pin 103 to improve further.
The formation process of described solder layer 108 is screen printing, and detailed process is: will carry meshed web plate laminating pin
103 first surface, mesh is corresponding with the position of groove, and the first metal coupling 107 is located in mesh, the not necessarily forming of pin
The surface of solder layer is covered by web plate；Then brush into solder(ing) paste in mesh；Then remove web plate.Other enforcements in the present invention
In example, described solder layer 108 can also be formed using other techniques.
The material of described solder layer 108 be stannum or tin alloy, described tin alloy be stannum silver, tin-lead, SAC, stannum silver-colored zinc,
Stannum zinc, stannum bismuth indium, stannum indium, Sillim, stannum copper, stannum zinc indium or stannum silver one of antimony or multiple.
Then, refer to Fig. 6, semiconductor chip 200 is provided, the surface of described semiconductor chip 200 is formed with pad
201, described pad 201 is formed with the second metal coupling 203.
There is in described semiconductor chip 200 integrated circuit (not shown), the pad on semiconductor chip 200 surface
201 are electrically connected with the integrated circuit in semiconductor chip, described pad 201 as the integrated circuit in semiconductor chip 200 with
The port of external electrical connections.The material of described pad 201 is the metal such as copper or aluminum.
On described semiconductor chip 200, also there is passivation layer or the polymeric layer covering described semiconductor chip 200 surface,
There is in described passivation layer or polymeric layer the opening exposing pad 201 surface, described passivation layer or polymeric layer are used for protecting
Semiconductor chip 200 is simultaneously isolated by semiconductor chip with external environment condition.
Described second metal coupling 203 can be metal column, and described second metal coupling 203 can also be soldered ball, described
Second metal coupling 203 can also include metal column and the soldered ball being located at metal column top on pad 201.Described gold
The material belonging to post can be w, al, cu, ti, ag, au, pt or ni, and the material of described soldered ball is stannum or tin alloy.The present embodiment
In, described second metal coupling 203 is soldered ball.
The formation process of described second metal coupling 203 is: forms one layer in semiconductor chip 200 and pad 201 surface
Metal level, described metal level is as the conductive layer being subsequently formed during solder layer and as the second metal coupling 203 and pad 201
Between adhesion layer, described metal layer material is one or more of nickel, platinum, titanium or tantalum；Light is formed on described metal level
Photoresist mask, described photoresist mask has the opening exposing the metal level on pad 201；Using electroplating technology in described opening
Middle filling solder, forms the second metal coupling 203；Remove described photoresist mask layer；With described second metal coupling 203 for covering
Film, etching removes the metal level of the second metal coupling 203 both sides, forms convex lower metal layer 202.
In the present embodiment, after forming the second metal coupling 203, the second metal coupling 203 can also be carried out with the work that flows back
Skill, the second metal coupling 203 making formation is in ball-type.In the other embodiment of the present invention, forming the second metal coupling 203
Afterwards, reflux technique can not be carried out, subsequently directly the second metal coupling 203 and the solder layer on pin be welded together, section
Save processing step, reduce heat budget.
Then, with reference to Fig. 7, semiconductor chip 200 is inverted in above pin 103, by second on semiconductor chip 200
Metal coupling 203 is welded together with the solder layer 108 on the first metal coupling 107 surface.
Specifically, first semiconductor chip 200 is inverted in pin 103 top so that on semiconductor chip 200 second
Metal coupling 203 is contacted with the solder layer 108 on the first metal coupling 107 surface on pin 103；To described solder layer 108
Carry out reflux technique so that solder layer 108 melts welds together the second metal coupling 203 and the first metal coupling 107；Right
Whole encapsulating structure is cooled down.
In the embodiment of the present invention, because the material of the second metal coupling 203 is identical with the material of solder layer 108, carrying out
During backflow, the second metal coupling 203 and solder layer 108 fusion are integrated.Second metal coupling in other embodiments of the invention
When the material of 203 material and solder layer 108 differs, the second metal coupling 203 passes through solder layer 108 and the first metal coupling
107 weld together.
Because solder layer 108 is contacted with the bottom of the groove of the first metal coupling 107 both sides and side wall, pin 103
Material is metal, and when being flowed back, the side wall of groove can have draw to solder layer so that the solder layer after backflow still can
Cover the side wall of the groove of the first metal coupling 107 both sides and the bottom of groove.
Semiconductor chip 200 is inverted in above pin 103, by the first metal coupling 107, solder layer 108 and second
Pad 201 on semiconductor chip 200 is electrically connected, with respect to existing by the attachment structure that metal coupling 203 is constituted with pin 103
Pin is arranged on around semiconductor chip and then by plain conductor, the pad on semiconductor chip is connected with pin
The forming method of encapsulating structure, it is horizontal that the encapsulating structure that the forming method of the encapsulating structure of the embodiment of the present invention is formed occupies
Area reduces, the small volume of whole encapsulating structure, and the forming method of this encapsulating structure enables the crystalline substance of lead frame structure
The encapsulation of circle level, improves the integrated level of encapsulating structure.
With reference to Fig. 8, formed and seal described semiconductor chip 200, the first metal coupling 107, the second metal coupling 203 and fill out
Plastic packaging layer 204 full of opening.
Described plastic packaging layer 204 surrounds the first table of described semiconductor chip 200, filling semiconductor chip 200 and pin 103
Region between face 11, plastic packaging layer 204 also fills up the opening (the first opening and the second opening) between full pin 103, plastic packaging layer
204 bottom-exposed go out pin away from the first metal coupling 107 1 side surface (second surface 12).During filling plastic packaging layer 204,
Due to the space between the opening between pin 103 and semiconductor chip 200 and semiconductor chip 200 and pin 103 the
Space between one surface 11 communicates, and improves the mobility of capsulation material, thus preventing from producing sky in plastic packaging layer 208
The defects such as gap.In addition it is by the on semiconductor chip 200 to the filling of the capsulation material of the opening between adjacent leads 103
Carry out after the first metal coupling 107 welding on two metal couplings 203 and pin 103, prevent before welding in the opening
In advance filling capsulation material after, when carrying out reflux technique to opening in capsulation material damage.
Described plastic packaging layer 204 is used for protection and insulation package structure, and the material of described plastic packaging layer 204 is resin, described tree
Fat can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin；Described resin can also be
For polybutylene terephthalate, Merlon, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, poly- ammonia
Ester, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol；Described plastic packaging layer 204
Can also be other suitable capsulation materials.
The formation process of described plastic packaging layer 204 be Shooting Technique or turn mould technique (transfer molding).Described mould
The formation process of sealing 204 can also be other suitable techniques.
After forming plastic packaging layer 204, also include, the outer unnecessary leadframe metal layer of plastic packaging layer 204 is removed using cutting technique
(outer peripheral areas), discharge each discrete pin 103.
The encapsulating structure that said method is formed, refer to Fig. 8, comprising:
Some discrete pins 103, have opening between adjacent leads 103；
The first metal coupling 107 on the surface of described pin 103；
Cover the solder layer 108 of described first metal coupling 107 top and side wall；
Semiconductor chip 200, the surface of described chip 200 has and has pad 201, and described pad 201 has the second gold medal
Belong to projection 203, semiconductor chip 203 is inverted in above pin 103, the second metal coupling 203 on semiconductor chip 200 with draw
The first metal coupling 107 on foot is welded together by solder layer 108.
Specifically, described opening includes the first opening mutually running through and the second opening, and the width of described first opening is little
In the width of the second opening, described first metal coupling 107 is located at the end surface (first away from the second opening of pin 103
Surface 11) on.
The surface (first surface 11) of described pin 107 has groove, and the first metal coupling 107 is located in groove, described
The top surface of the first metal coupling 107 is higher than the surface (first surface 11) of pin 103, described first metal coupling 107
Width is less than the width of groove, and described solder layer 108 also covers side wall and the bottom table of the groove of the first metal coupling 107 both sides
Face.
In other embodiments of the invention, described solder layer is except covering the side wall of the groove of the first metal coupling both sides
And lower surface, described solder layer also covers the part surface of the pin of the first metal coupling both sides.
Also include: seal described semiconductor chip 200, the first metal coupling 107, the second metal coupling 203 and fill full
The plastic packaging layer 204 of opening.
To sum up, the forming method of the encapsulating structure of the embodiment of the present invention and its encapsulating structure, semiconductor chip is inverted in
Above pin, the attachment structure consisting of the first metal coupling, solder layer and the second metal coupling is by semiconductor chip
Pad is electrically connected with the pin and is so that the small volume of whole encapsulating structure, and the forming method of this encapsulating structure enables to draw
The encapsulation of the wafer scale of wire frame structure, improves the integrated level of encapsulating structure.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope limiting is defined.
Claims (6)
1. a kind of encapsulating structure is it is characterised in that include:
Some discrete pins, have opening between adjacent leads；
Positioned at the groove of described pin surface, the first metal coupling is located in groove, the top surface of described first metal coupling
Higher than the open surfaces of groove, and the width of described first metal coupling is less than the width of groove；
Cover the solder layer of described first metal coupling top and side wall；
Semiconductor chip, the surface of described semiconductor chip has and has pad, described pad has the second metal coupling, partly leads
Above pin, the second metal coupling on semiconductor chip passes through solder with the first metal coupling on pin to body flip-chip
Layer welds together.
2. encapsulating structure as claimed in claim 1 is it is characterised in that described opening includes the first opening mutually running through and
Two openings, the width of described first opening is less than the width of the second opening.
3. encapsulating structure as claimed in claim 2 it is characterised in that described first metal coupling be located at pin away from second
On the end surface of opening.
4. encapsulating structure as claimed in claim 1 is it is characterised in that described solder layer also covers the first metal coupling both sides
The side wall of groove and lower surface.
5. encapsulating structure as claimed in claim 1 is it is characterised in that described solder layer also covers the first metal coupling both sides
The side wall of groove and the part surface of lower surface and pin.
6. encapsulating structure as claimed in claim 1 is it is characterised in that also include: seals described semiconductor chip, the first metal
Projection, the second metal coupling simultaneously fill the plastic packaging layer of full gate mouth.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310656037.5A CN103745965B (en) | 2013-12-05 | 2013-12-05 | Packaging structure |
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| CN201310656037.5A CN103745965B (en) | 2013-12-05 | 2013-12-05 | Packaging structure |
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| CN103745965B true CN103745965B (en) | 2017-02-01 |
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| US10269672B2 (en) * | 2017-08-24 | 2019-04-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1744308A (en) * | 2004-09-04 | 2006-03-08 | 三星Techwin株式会社 | Flip chip semiconductor device and manufacturing method thereof |
| CN102496585A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Novel wafer level packaging method |
| CN102543907A (en) * | 2011-12-31 | 2012-07-04 | 北京工业大学 | Package and manufacture method for thermal enhanced quad flat no-lead flip chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8669137B2 (en) * | 2011-04-01 | 2014-03-11 | International Business Machines Corporation | Copper post solder bumps on substrate |
| CN202948918U (en) * | 2011-10-20 | 2013-05-22 | 先进封装技术私人有限公司 | Package substrate and package structure of semiconductor component |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1744308A (en) * | 2004-09-04 | 2006-03-08 | 三星Techwin株式会社 | Flip chip semiconductor device and manufacturing method thereof |
| CN102496585A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Novel wafer level packaging method |
| CN102543907A (en) * | 2011-12-31 | 2012-07-04 | 北京工业大学 | Package and manufacture method for thermal enhanced quad flat no-lead flip chip |
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