CN103745965A - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN103745965A CN103745965A CN201310656037.5A CN201310656037A CN103745965A CN 103745965 A CN103745965 A CN 103745965A CN 201310656037 A CN201310656037 A CN 201310656037A CN 103745965 A CN103745965 A CN 103745965A
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- metal coupling
- pin
- semiconductor chip
- metal
- opening
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A packaging structure comprises: a plurality of separated pins, wherein an opening is formed between adjacent pins; first metal protrusion blocks arranged on the surfaces of the pins; solder layers covering the tops and side walls of the first metal protrusion blocks; and a semiconductor chip, wherein the surface of the semiconductor chip is provided with bonding pads. Each bonding pad is provided with a second metal protrusion block. The semiconductor chip is inversely arranged above the pins. The second metal protrusion blocks on the semiconductor chip are welded with the first metal protrusion blocks on the pins through the solder layers. The integration level of the packaging structure is high.
Description
Technical field
The present invention relates to semiconductor packages field, particularly a kind of semiconductor package.
Background technology
Along with electronic product is if mobile phone, notebook computer etc. are towards miniaturization, portable, ultrathin, multimedization and meet the low cost future development of public demand, high density, high-performance, high reliability and cheaply packing forms and packaging technology thereof have obtained development fast.With expensive BGA(Ball Grid Array) etc. compared with packing forms, fast-developing novel encapsulated technology in recent years, as four limit flat non-pin QFN(Quad Flat No-leadPackage) encapsulation, because it has advantages of good hot property and electrical property, size is little, cost is low and high production rate etc. is numerous, caused a new revolution in microelectronic packaging technology field.
Fig. 1 is the structural representation of existing QFN encapsulating structure, and described QFN encapsulating structure comprises: semiconductor chip 14, has pad 15 on described semiconductor chip 14; Pin 16(lead frame), described pin 16 is arranged around the surrounding of described semiconductor chip 14; Plain conductor 17, plain conductor 17 is electrically connected the pad of semiconductor chip 14 15 with the pin 16 around described semiconductor chip 14; Capsulation material 18, described capsulation material 18 seals semiconductor chip 15, metal wire 17 and pin 16, and the surface exposure of pin 16 is in the bottom surface of capsulation material, by pin 16, realizes being electrically connected of semiconductor chip 14 and external circuit.
The volume that existing encapsulating structure occupies is larger, is unfavorable for the raising of encapsulating structure integrated level.
Summary of the invention
The problem that the present invention solves is how to reduce the volume that encapsulating structure occupies.
For addressing the above problem, the invention provides a kind of formation method of encapsulating structure, comprising: leadframe metal layer is provided; Leadframe metal layer described in etching, forms some discrete pins, has opening between adjacent leads; On the surface of pin, form the first metal coupling; Top and sidewall surfaces at the first metal coupling form solder layer; Semiconductor chip is provided, and the surface of described semiconductor chip is formed with pad, is formed with the second metal coupling on described pad; Semiconductor chip upside-down mounting, above pin, is welded together the solder layer of the second metal coupling on semiconductor chip and the first metal lug surface.
Optionally, the forming process of described pin is: described leadframe metal layer comprises first surface and the second surface relative with first surface, and the first surface of etching leadframe metal layer forms some the first openings in leadframe metal layer; The second surface of etching leadframe metal layer forms some the second openings in leadframe metal layer, and the first opening and the second opening run through mutually, and the first opening and the second opening form opening, are pin between adjacent apertures.
Optionally, before forming the first opening or the second opening, also comprise: at the first surface of described leadframe metal layer, form the first patterned mask layer; At the second surface of described leadframe metal layer, form the mask layer of second graphical.
Optionally, the width of described the first opening is less than the width of the second opening, and described the first metal coupling is positioned on the first surface of pin.
Optionally, the surface of etching pin forms groove in pin, forms the first metal coupling in groove, and the top surface of described the first metal coupling is higher than the surface of slot opening.
Optionally, the width of described the first metal coupling is less than the width of groove.
Optionally, described solder layer also covers sidewall and the lower surface of the groove of the first metal coupling both sides.
Optionally, described solder layer also covers the sidewall of groove and the part surface of lower surface and pin of the first metal coupling both sides.
Optionally, the technique that forms described solder layer is screen printing.
Optionally, described the second metal coupling is soldered ball or metal column, or comprises the soldered ball at metal column and metal column top.
Optionally, the technique solder layer of the second metal coupling on semiconductor chip and the first metal lug surface being welded together is reflux technique.
Optionally, also comprise: form the plastic packaging layer that seals described semiconductor chip, the first metal coupling, the second metal coupling and fill full gate mouth.
The present invention also provides a kind of encapsulating structure, comprising: some discrete pins, have opening between adjacent leads; Be positioned at lip-deep first metal coupling of described pin; Cover the solder layer of described the first metal coupling top and sidewall; Semiconductor chip, the surface of described semiconductor chip has and has pad, on described pad, have the second metal coupling, semiconductor chip upside-down mounting is above pin, and the first metal coupling on the second metal coupling and pin on semiconductor chip welds together by solder layer.
Optionally, described opening comprises the first opening and the second opening that mutually run through, and the width of described the first opening is less than the width of the second opening.
Optionally, described the first metal coupling is positioned on the end surfaces away from the second opening of pin.
Optionally, the surface of described pin has groove, and the first metal coupling is positioned at groove, and the top surface of described the first metal coupling is higher than the open surfaces of groove.
Optionally, the width of described the first metal coupling is less than the width of groove.
Encapsulating structure as claimed in claim 17, is characterized in that, described solder layer also covers sidewall and the lower surface of the groove of the first metal coupling both sides.
Optionally, described solder layer also covers the sidewall of groove and the part surface of lower surface and pin of the first metal coupling both sides.
Optionally, also comprise: seal described semiconductor chip, the first metal coupling, the second metal coupling and fill the plastic packaging layer of full gate mouth.
Compared with prior art, technical scheme of the present invention has the following advantages:
Encapsulation of the present invention, semiconductor chip upside-down mounting is above pin, the syndeton consisting of the first metal coupling, solder layer and the second metal coupling is electrically connected the pad on semiconductor chip with pin, with respect to existing, pin is arranged on to then semiconductor chip is connected the pad on semiconductor chip by plain conductor encapsulating structure with pin around, the horizontal area that the encapsulating structure of the embodiment of the present invention occupies reduces, the small volume of whole encapsulating structure.In addition, on pin, form the first metal coupling, in encapsulation process, on the one hand, the existence of the first metal coupling, when by semiconductor chip upside-down mounting on pin time, described metal coupling can play the effect of location, on the other hand, the existence of the first metal coupling, than the second metal coupling on semiconductor chip is directly welded on pin, on pin, form after the first metal coupling, when welding, the gradient steepening of the syndeton between semiconductor chip and pin, the area on the pin surface that syndeton occupies reduces, again on the one hand, the existence of the first metal coupling, distance between semiconductor chip and pin is increased, forming the described semiconductor chip of sealing, the first metal coupling, during the plastic packaging layer of solder layer and the second metal coupling, prevent from forming the defects such as space in the plastic packaging layer between semiconductor chip and pin.
Further, described opening comprises the first opening and the second opening, the width of the first opening is less than the width of the second opening, the area of the first surface of the pin forming is greater than the area of second surface, in the process of encapsulation, on the first surface of pin, form metal coupling, because the area of the first surface of pin is larger, when adopting lead key closing process to form the first metal coupling, the first surface of pin can bear larger pressure and have larger contact area, reduced to adopt lead key closing process to form the difficulty of the first metal coupling, the area of the second surface of pin is less, make the distance between the second surface of adjacent leads larger, when the second surface of pin is connected with external circuit (such as pcb board circuit), prevent the short circuit between adjacent leads.
Further, surface at pin is formed with groove, described the first metal coupling is positioned at groove, the top surface of described the first metal coupling is higher than the open surfaces of groove, the width of the first metal coupling is less than the width of groove, make the both sides of the first metal coupling have part groove by the first metal coupling, not covered, in the process of encapsulation, when the first metal coupling top and sidewall formation solder layer, solder layer can cover sidewall and the lower surface of the groove of the first metal coupling both sides, the contact area of solder layer and pin and the first metal coupling is increased, improved adhesion and mechanical stability between the syndeton that forms between follow-up semiconductor chip and pin and pin.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of prior art encapsulating structure;
Fig. 2～Fig. 8 is the cross-sectional view of embodiment of the present invention encapsulating structure forming process.
Embodiment
The integrated level of existing encapsulating structure is lower, please refer to Fig. 1, pin 16 in existing encapsulating structure be around be arranged in semiconductor chip 14 around, pad 15 on semiconductor chip 14 need to be electrically connected with pin 16 around by plain conductor 17, the volume that whole encapsulating structure is occupied is larger, is unfavorable for the raising of encapsulating structure integrated level.
The invention provides a kind of encapsulating structure, semiconductor chip upside-down mounting is above pin, the first metal coupling on the second metal coupling and pin on semiconductor chip welds together by solder layer, and the volume that encapsulating structure occupies reduces, and has improved the integrated level of encapsulating structure.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.Describing in detail during the embodiment of the present invention, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
Fig. 2～Fig. 8 is the cross-sectional view of embodiment of the present invention encapsulating structure forming process.
First, please refer to Fig. 2, leadframe metal layer 100 is provided.
The follow-up formation pin of described leadframe metal layer 100, described leadframe metal layer 100 has first surface 11 and the second surface 12 relative with first surface 11.
The material of described leadframe metal layer 100 is metal or alloy.The material of described leadframe metal layer 100 can be one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
Described leadframe metal layer 100 can be the metal of individual layer or the stacked structure of multiple layer metal.
Described leadframe metal layer 100 comprises the outer peripheral areas (not shown) of some lead-in wires region around described lead-in wire region, the some discrete pins of the follow-up formation in described lead-in wire region, described outer peripheral areas is for fixing and support some discrete pins, one side of pin contacts with outer peripheral areas, other three sides of pin are unsettled, follow-up formation after encapsulating structure, removes the outer peripheral areas of the metal level 100 that goes between by cutting, discharge the some discrete pin of encapsulating structure.Then, please refer to Fig. 3, leadframe metal layer 100(is with reference to 2 described in etching), form some discrete pins 103, between adjacent leads 103, there is opening.
The forming process of described pin 103 is: on the first surface 11 of described leadframe metal layer 100, form the first patterned mask layer (not shown); Take described the first patterned mask layer as mask, the first surface 11 of etching leadframe metal layer 100, at some the first openings 102 of the interior formation of leadframe metal layer 100; On the second surface 12 of described leadframe metal layer 100, form the mask layer (not shown) of second graphical; Take the mask layer of described second graphical as mask, the second surface 12 of etching leadframe metal layer 100, at some the second openings 101 of the interior formation of leadframe metal layer 100, the first opening 102 and the second opening 101 run through mutually, the first opening 102 and the second opening 101 form opening, are pin 103 between adjacent apertures.
The material of the mask layer of described the first patterned mask layer or second graphical can be epoxide-resin glue or other suitable materials.The formation technique of the mask layer of the first patterned mask layer or second graphical is for pasting dry film technique or imprint process.The formation technique of the mask layer of described the first patterned mask layer or second graphical can be also spraying or spin coating proceeding.
The width of described the first opening 102 is less than the width of the second opening 101, make the area of the first surface 11 of the pin 103 forming be greater than the area of second surface 12, follow-uply on the first surface of pin 103, form metal coupling, because the area of the first surface 11 of pin 103 is larger, when adopting lead key closing process to form the first metal coupling, the first surface of pin 103 can bear larger pressure and have larger contact area, reduced to adopt lead key closing process to form the difficulty of the first metal coupling, the area of the second surface 12 of pin 103 is less, make the distance between the second surface 12 of adjacent leads 103 larger, it is follow-up when the second surface of pin 103 12 is connected with external circuit (such as pcb board circuit), prevent the short circuit between adjacent leads 103, in addition, the width of the first opening 102 and the second opening 101 is different, follow-up filling in the first opening 102 and the second opening 101 while expiring capsulation material, pin 103 and the quantity of the contact-making surface of plastic packaging layer are increased, pin is not easy to come off from capsulation material.It should be noted that, described the first opening 102 can form before or after the second opening 101 forms.
Also comprise: the surface (the follow-up surface of metal coupling or the first surface of pin 11 of forming thereon) of etching pin 103, at the interior formation groove 105 of pin 103.Can or forming after formation before the first opening 102 forms of described groove 105.Before forming groove 105, on the first surface 11 of described pin 103, form the 3rd patterned mask layer, the first surface 11 take described the 3rd patterned mask layer as pin described in mask etching 103, forms groove 105.Follow-up at interior formation the first metal coupling of groove 105.
In other embodiments of the invention, after forming the first opening 102 and the second opening 101, can also on the second surface of described pin 103 12, form one deck dry film film, described dry film film covers the second surface of pin 103 12, follow-up while filling capsulation material in opening, prevent the flash of capsulation material to the lower surface of pin 103, follow-up forming after plastic packaging layer, described dry film film is removed.
Then, please refer to Fig. 4, on the surface of pin 103, form the first metal coupling 107.
In the present embodiment, at the first surface 11 of pin 103, form the first metal coupling 107, described the first metal coupling 107 is positioned at groove 105, the top surface of described the first metal coupling 107 is higher than the open surfaces of groove 105, the width of the first metal coupling 107 is less than the width of groove 105, make the both sides of the first metal coupling 107 have part groove 105 not capped, follow-up when the first metal coupling 107 tops and sidewall formation solder layer, solder layer can cover sidewall and the lower surface of the groove 105 of the first metal coupling 107 both sides, the contact area of solder layer and pin 103 and the first metal coupling 107 is increased, improved adhesion and mechanical stability between the syndeton that forms between follow-up semiconductor chip and pin and pin 103.
The material of described the first metal coupling 107 can be one or more in aluminium, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, silver.
Form described the first metal coupling 107 and can adopt lead key closing process or typography.In other embodiments of the invention, described metal coupling 107 can also adopt other suitable techniques to form.
In the embodiment of the present invention, on pin 103, form the first metal coupling 107, in follow-up encapsulation process, on the one hand, the existence of the first metal coupling 107, when by semiconductor chip upside-down mounting on pin time, described the first metal coupling 107 can play the effect of location, on the other hand, the existence of the first metal coupling 107, than the second metal coupling on semiconductor chip is directly welded on pin 103, on pin 103, form after the first metal coupling 107, when welding, the gradient steepening of the syndeton between semiconductor chip and pin 103, the area on pin 103 surfaces that syndeton occupies reduces, again on the one hand, the existence of the first metal coupling 107, distance between semiconductor chip and pin 103 is increased, forming the described semiconductor chip of sealing, the first metal coupling 107, during the plastic packaging layer of solder layer 103 and the second metal coupling, prevent from forming the defects such as space in the plastic packaging layer between semiconductor chip and pin.
The detailed process that Bonding forms the first metal coupling 107 is: metal wire is reached to its top through the bonding head of bonding apparatus (or in bonding head chopper capillary); By oxyhydrogen flame or electrical system, producing electric spark makes the metal wire melting of stretching out in bonding head form metal coupling; Bonding head is pressed together on metal coupling on the first surface 11 of pin 103; Chopper in bonding head cuts off metal wire, and metal coupling is retained on the first surface of pin 103, forms the first metal coupling 107.The metal coupling forming by lead key closing process, technique is simple, and efficiency is higher, and can not bring pollution.
The process that adopts typography to form the first metal coupling 107 is: by the first surface 11 with meshed web plate laminating pin 103, mesh exposes the part first surface 11 of pin 103; Brush as metal filled material in mesh (such as: scolding tin etc.); Then, remove web plate, on the first surface 11 of pin 103, form the first metal coupling 107.
Then, please refer to Fig. 5, at sidewall and the top surface of described the first metal coupling 107, form solder layer 108.
Follow-up semiconductor chip upside-down mounting above pin 103 time, is welded together the first metal coupling 107 on the second metal coupling on the pad of semiconductor chip and pin 103 by solder layer 108.
In the present embodiment, described solder layer 108 also covers the groove 105(of the first metal coupling 107 both sides with reference to figure 4) sidewall and lower surface, because groove 105 has bottom and sidewall, solder layer covers the groove 105(of the first metal coupling 107 both sides with reference to figure 4) sidewall and during lower surface, the contact area of solder layer 105 and the first metal coupling 107 and pin 103 is increased, follow-uply between semiconductor chip and pin 103, be formed with the first metal coupling, during syndeton that solder layer and the second metal coupling form, improved adhesion and mechanical stability between the syndeton that forms between semiconductor chip and pin and pin 103.
In other embodiment of the present invention, described solder layer is except covering sidewall and the lower surface of groove of the first metal coupling both sides, described solder layer also covers the part surface of the pin of the first metal coupling both sides, forming during syndeton, adhesion and mechanical stability between syndeton and pin 103 are further improved.
The formation technique of described solder layer 108 is screen printing, detailed process is: by the first surface with meshed web plate laminating pin 103, mesh is corresponding with the position of groove, and the first metal coupling 107 is positioned at mesh, and the surface without forming solder layer of pin is covered by web plate; Then in mesh, brush into solder(ing) paste; Then remove web plate.In other embodiments of the invention, described solder layer 108 can also adopt other technique to form.
The material of described solder layer 108 is tin or ashbury metal, and described ashbury metal is one or more in tin silver, tin lead, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony.
Then, please refer to Fig. 6, semiconductor chip 200 is provided, the surface of described semiconductor chip 200 is formed with pad 201, is formed with the second metal coupling 203 on described pad 201.
In described semiconductor chip 200, there is integrated circuit (not shown), the pad 201 on semiconductor chip 200 surfaces is electrically connected with the integrated circuit in semiconductor chip, and described pad 201 is as the integrated circuit in semiconductor chip 200 and the outside port being electrically connected.The material of described pad 201 is the metals such as copper or aluminium.
On described semiconductor chip 200, also there is the passivation layer or the polymeric layer that cover described semiconductor chip 200 surfaces; in described passivation layer or polymeric layer, have the opening on exposed pad 201 surfaces, described passivation layer or polymeric layer are for the protection of semiconductor chip and by semiconductor chip 200 and external environment condition isolation.
Described the second metal coupling 203 can be metal column, and described the second metal coupling 203 can be also soldered ball, and described the second metal coupling 203 can also comprise the soldered ball that is positioned at the metal column on pad 201 and is positioned at metal column top.The material of described metal column can be W, Al, Cu, Ti, Ag, Au, Pt or Ni, and the material of described soldered ball is tin or ashbury metal.In the present embodiment, described the second metal coupling 203 is soldered ball.
The formation technique of described the second metal coupling 203 is: at semiconductor chip 200 and pad 201 surfaces, form layer of metal layer, the conductive layer of described metal level during as follow-up formation solder layer and as the adhesion layer between the second metal coupling 203 and pad 201, described metal layer material is one or more in nickel, platinum, titanium or tantalum; On described metal level, form photoresist mask, described photoresist mask has the opening of the metal level in exposed pad 201; Adopt electroplating technology to fill scolder in described opening, form the second metal coupling 203; Remove described photoresist mask layer; Take described the second metal coupling 203 as mask, etching is removed the metal level of the second metal coupling 203 both sides, forms protruding lower metal layer 202.
In the present embodiment, forming after the second metal coupling 203, can also carry out reflux technique to the second metal coupling 203, make the second metal coupling 203 forming be ball-type.In other embodiment of the present invention, forming after the second metal coupling 203, can not carry out reflux technique, follow-uply directly the second metal coupling 203 and the solder layer on pin be welded together, save processing step, reduce heat budget.
Then,, with reference to figure 7, semiconductor chip 200 upside-down mountings, above pin 103, are welded together the solder layer 108 on the second metal coupling 203 on semiconductor chip 200 and the first metal coupling 107 surfaces.
Concrete, first by semiconductor chip 200 upside-down mountings above pin 103, the second metal coupling 203 on semiconductor chip 200 is contacted with the solder layer 108 on the first metal coupling 107 surfaces on pin 103; Described solder layer 108 is carried out to reflux technique, solder layer 108 is melted the second metal coupling 203 and the first metal coupling 107 are welded together; To whole encapsulating structure, carry out cooling.
In the embodiment of the present invention, because the material of the second metal coupling 203 is identical with the material of solder layer 108, when refluxing, the second metal coupling 203 is integrated with solder layer 108 fusions.When the material of the material of the second metal coupling 203 and solder layer 108 is not identical in other embodiments of the invention, the second metal coupling 203 welds together by solder layer 108 and the first metal coupling 107.
Because solder layer 108 contacts with bottom and the sidewall of the groove of the first metal coupling 107 both sides, the material of pin 103 is metal, when refluxing, the sidewall of groove can have draw to solder layer, makes the solder layer after refluxing still can cover sidewall and the bottom of the groove of the first metal coupling 107 both sides of groove.
By semiconductor chip 200 upside-down mountings above pin 103, by the first metal coupling 107, the syndeton that solder layer 108 and the second metal coupling 203 form is electrically connected the pad on semiconductor chip 200 201 with pin 103, with respect to the existing formation method that pin is arranged on to the encapsulating structure then by plain conductor, the pad on semiconductor chip being connected with pin around semiconductor chip, the horizontal area that the encapsulating structure that the formation method of the encapsulating structure of the embodiment of the present invention forms occupies reduces, the small volume of whole encapsulating structure, and the formation method of this encapsulating structure can realize the encapsulation of the wafer scale of lead frame structure, improved the integrated level of encapsulating structure.
With reference to figure 8, form the plastic packaging layer 204 that seals described semiconductor chip 200, the first metal coupling 107, the second metal coupling 203 and fill full gate mouth.
Described plastic packaging layer 204 surrounds the region between the first surface 11 of described semiconductor chip 200, filling semiconductor chip 200 and pin 103, plastic packaging layer 204 is also filled the opening (the first opening and the second opening) between full pin 103, the bottom-exposed of plastic packaging layer 204 go out pin away from the first metal coupling 107 1 side surfaces (second surface 12).While filling plastic packaging layer 204, because the space between the space between the opening between pin 103 and semiconductor chip 200 and semiconductor chip 200 and the first surface 11 of pin 103 communicates, improved the mobility of capsulation material, thereby prevented from producing the defects such as space in plastic packaging layer 208.The filling of the capsulation material to the opening between adjacent leads 103 is to carry out after the first metal coupling 203 on the second metal coupling 107 on semiconductor chip 200 and pin 103 is welded in addition, prevent from opening, filling in advance after capsulation material before welding, when carrying out reflux technique to opening in the damage of capsulation material.
Described plastic packaging layer 204 for the protection of with insulation package structure, the material of described plastic packaging layer 204 is resin, described resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described resin also can be for being polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; Described plastic packaging layer 204 can also be other suitable capsulation materials.
The formation technique of described plastic packaging layer 204 is Shooting Technique or turns and mould technique (transfer molding).The formation technique of described plastic packaging layer 204 can also be other suitable techniques.
Form after plastic packaging layer 204, also comprise, adopt cutting technique to remove plastic packaging layer 204 outer unnecessary leadframe metal layer (outer peripheral areas), discharge each discrete pin 103.
The encapsulating structure that said method forms, please refer to Fig. 8, comprising:
Some discrete pins 103, have opening between adjacent leads 103;
Be positioned at lip-deep first metal coupling 107 of described pin 103;
Cover the solder layer 108 of described the first metal coupling 107 tops and sidewall;
Concrete, described opening comprises the first opening and the second opening that mutually run through, and the width of described the first opening is less than the width of the second opening, and described the first metal coupling 107 is positioned on the end surfaces away from the second opening (first surface 11) of pin 103.
The surface (first surface 11) of described pin 107 has groove, the first metal coupling 107 is positioned at groove, the top surface of described the first metal coupling 107 is higher than the surface (first surface 11) of pin 103, the width of described the first metal coupling 107 is less than the width of groove, and described solder layer 108 also covers sidewall and the lower surface of the groove of the first metal coupling 107 both sides.
In other embodiments of the invention, described solder layer is except covering sidewall and the lower surface of groove of the first metal coupling both sides, and described solder layer also covers the part surface of the pin of the first metal coupling both sides.
Also comprise: seal described semiconductor chip 200, the first metal coupling 107, the second metal coupling 203 and fill the plastic packaging layer 204 of full gate mouth.
To sum up, the formation method of the encapsulating structure of the embodiment of the present invention and encapsulating structure thereof, by semiconductor chip upside-down mounting above pin, the syndeton consisting of the first metal coupling, solder layer and the second metal coupling is electrically connected the pad on semiconductor chip with pin, make the small volume of whole encapsulating structure, and the formation method of this encapsulating structure can realize the encapsulation of the wafer scale of lead frame structure, improved the integrated level of encapsulating structure.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. an encapsulating structure, is characterized in that, comprising:
Some discrete pins, have opening between adjacent leads;
Be positioned at lip-deep first metal coupling of described pin;
Cover the solder layer of described the first metal coupling top and sidewall;
Semiconductor chip, the surface of described semiconductor chip has and has pad, on described pad, have the second metal coupling, semiconductor chip upside-down mounting is above pin, and the first metal coupling on the second metal coupling and pin on semiconductor chip welds together by solder layer.
2. encapsulating structure as claimed in claim 1, is characterized in that, described opening comprises the first opening and the second opening that mutually run through, and the width of described the first opening is less than the width of the second opening.
3. encapsulating structure as claimed in claim 2, is characterized in that, described the first metal coupling is positioned on the end surfaces away from the second opening of pin.
4. encapsulating structure as claimed in claim 1, is characterized in that, the surface of described pin has groove, and the first metal coupling is positioned at groove, and the top surface of described the first metal coupling is higher than the open surfaces of groove.
5. encapsulating structure as claimed in claim 4, is characterized in that, the width of described the first metal coupling is less than the width of groove.
6. encapsulating structure as claimed in claim 5, is characterized in that, described solder layer also covers sidewall and the lower surface of the groove of the first metal coupling both sides.
7. encapsulating structure as claimed in claim 5, is characterized in that, described solder layer also covers the sidewall of groove and the part surface of lower surface and pin of the first metal coupling both sides.
8. encapsulating structure as claimed in claim 1, is characterized in that, also comprises: seal described semiconductor chip, the first metal coupling, the second metal coupling and fill the plastic packaging layer of full gate mouth.
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| CN201310656037.5A CN103745965B (en) | 2013-12-05 | 2013-12-05 | Packaging structure |
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| CN109216310A (en) * | 2017-08-24 | 2019-01-15 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
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| CN103745965B (en) | 2017-02-01 |
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