CN103744813A - Time sequence determination method for guaranteeing 1553B bus communication time sequence correctness - Google Patents

Time sequence determination method for guaranteeing 1553B bus communication time sequence correctness Download PDF

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CN103744813A
CN103744813A CN201310751624.2A CN201310751624A CN103744813A CN 103744813 A CN103744813 A CN 103744813A CN 201310751624 A CN201310751624 A CN 201310751624A CN 103744813 A CN103744813 A CN 103744813A
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communication
subaddressing
time
subaddressings
bus
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CN103744813B (en
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顾斌
綦艳霞
杨孟飞
董晓刚
陈尧
王政
关小川
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Beijing Institute of Control Engineering
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Beijing Institute of Control Engineering
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Abstract

Disclosed is a time sequence determination method for guaranteeing 1553B bus communication time sequence correctness. According to communication modes and characteristics of sub-addresses of a 1553B bus, communication time sequence requirements are determined, and bus communication time sequence correctness is guaranteed. The time sequence determination method solves the problem of incomplete time requirements in traditional analysis. Communication time and communication time interval requirements of communication functions are identified, and more systematic and comprehensive factors are provided for analysis. The sequence and the time requirements of different communication functions are analyzed, and time sequence problems needing to be considered are given when a plurality of communications jointly complete the same system function, so that uncertainty of software system behaviors is decreased.

Description

A kind of sequential of the 1553B of guarantee bus communication sequential correctness is determined method
Technical field
The present invention relates to a kind of analytical approach of the 1553B of guarantee bus communication sequential correctness, can, by being applied in the analysis of 1553B bus software systems communication succession, ensure rationality and the correctness of sequential.Mainly in spacecraft control communication function, use, belong to embedded system technology field.
Background technology
The full name of 1553B is MIL-STD-1553B, it is a kind of serial data bus standard, be to be the development that adapts to aircraft in late 1970s, the standard of the interior of aircraft electronic system being proposed by U.S. networking, because its high reliability and dirigibility are widely applied in aircraft industry.1553B bus is also widely applied on the spacecrafts such as domsat, airship at present.1553B bus realizes the communication between Attitude and orbit control system and data handling subsystem in control system, and swap data, to realize star and contact and manual intervention to satellite.Therefore its communication succession correctness is directly connected to reliability and the function realization of whole star ship.
In 1553B communication, the subaddressing multiple timings complexity of communication, and use common storage area, this has just caused a lot of timing conflicts and data access collision problem, occurred the phenomenon of losing communication instruction or having processed wrong instruction, these have all affected the realization of dynamic time sequence correctness.
Traditional analytical approach lacks for the comprehensive time series analysis of 1553B communication succession system, just with regard to several main communication subfunctions or clear and definite sequential relationship, analyze, this analysis has the following disadvantages: the time requirement that (1) provides is not comprehensive, this is unfavorable for communication succession comprehensively to analyze, due to the omission of these constraints, may cause the not corresponding foundation of design and generation mistake;
(2) time series analysis between each communication subfunction lacks, and the sequential relationship between them does not clearly provide, and some implicit temporal constraint do not pay close attention to, and causes the sequential of communication uncertain;
Along with adopting the more and more of 1553B bus communication in control system, and the subfunction of communication is also complicated various, and also more and more stricter to the requirement of communication succession, traditional sequential determines that method cannot meet the correctness requirement to communication succession already.
Summary of the invention
Technical matters solved by the invention is: overcome the deficiencies in the prior art, a kind of definite method of the 1553B of guarantee bus communication sequential correctness is provided, reduced the uncertainty of software systems behaviors.
The technology of the present invention solution: many command function differences of multiple subaddressings, guarantee real-time and the correctness of communication the opportunity of generation in the situation different with processing mode.During embedded software running, frequency, the interruption processing time of each instruction are different, no matter which kind of instruction, all can affect normal communication as long as its generation opportunity or processing procedure produce to conflict with other instruction, causes the problem of Communications failure and instruction loss.
For guaranteeing the correctness of communication, its gordian technique is to guarantee that timing coordination between the instruction of each subaddressing is without conflict.The present invention, according to the communication succession requirement of analyzing each subaddressing, has designed a kind of definite technical scheme of communication succession correctness sequential that guarantees for this reason, and main contents comprise:
(1) 1553B bus comprises that 32 receive subaddressing and 32 transmission subaddressings, determine the communication modes of subaddressing: single message mode or circular buffering mode according to the byte number of data transmission;
(2) according to the communication modes obtaining in step 1, the time needing while determining the communication of each subaddressing;
(3) by bus command communication subaddressing, can complete antenna communication, side-sway control and synchronous serial interface switch control functions, belong to the situation of the same subaddressing of multiple multiplexing functions, according to the data processing time of the communication time obtaining in step 2 and the transmission of multiple function, determine the time interval requirement between the subaddressing communication being re-used;
(4) injecting command function need to be by injecting instruction 1 subaddressing, inject instruction 2 subaddressings, inject 3 instruction subaddressings, inject instruction 4 subaddressings and injection complete these 5 subaddressings, subaddressing and jointly complete, according to functional requirement, first determine the sequencing of each subaddressing communication, the communication time of these subaddressings of then determining according to step 2, the time interval that obtains these twice communications in subaddressing is wanted;
(5) sequential of all subaddressings is determined
Step (3) and step (4) have been determined the time interval requirement of bus command and injection twice communication in command function subaddressing, and the time interval of twice communication of all the other subaddressings is defined as communication time and adds bus minimum message interval.
The present invention's beneficial effect is compared with prior art:
(1) the invention solves the incomplete problem of time requirement in traditional analysis.The present invention identifies time interval requirement between the communication time of each communication function and communication, for the more comprehensive factor of system that provides is provided.
(2) the present invention has provided time series analysis between the communication function with dependence.The sequential that traditional analysis has only provided each communication subfunction requires and analyzes, and does not consider the dependence between them.The present invention not only analyzes between different communication functions sequencing and time requirement, when giving multiple communications and jointly completing same system function, needs the sequence problem of considering.Reduced like this uncertainty of software systems behaviors.
Accompanying drawing explanation
Fig. 1 is the definite process flow diagram of communication succession of the present invention.
Embodiment
As shown in Figure 1, specific embodiment of the invention step is as follows:
(1) 1553B bus comprises that 32 receive subaddressing and 32 transmission subaddressings, determine the communication modes of subaddressing: single message mode or circular buffering mode according to the byte number of data transmission;
If it is single message mode that data length is less than or equal to 64 bytes; Being greater than 64 bytes is circular buffering mode, and the message number of communication is that data length rounds greatly divided by 64 bytes are backward;
(2) according to the communication modes obtaining in step 1, the time needing while determining the communication of the each subaddressing of 1553B bus;
To each subaddressing, single message mode if, communication time is that single byte communication time takes advantage of 64, is designated as T1; Circular buffering mode if, communication time is comprised of four parts, and the message number that Part I is communication is multiplied by the communication time T1 of single message.Be designated as T2_1; The second part is the number that the message interval that is spaced apart bus minimum between message is multiplied by communication message, is designated as T2_2; The 3rd communication time that part is synchronization message, owing to being circular buffering mode, have a synchronous message to make the pointer of circular buffering get back to initial position, and this communication modes is single message, and communication time is also T2_3=T1; The 4th part is the time interval of communication message and synchronization message, is designated as T2_4=bus minimum message interval T; The communication time T2=T2_1+T2_2+T2_3+T2_4 of circular buffering communication modes;
(3) by bus command communication subaddressing, can complete antenna communication, side-sway control and synchronous serial interface switch control functions, belong to the situation of the same subaddressing of multiple multiplexing functions, according to the data processing time of the communication time obtaining in step 2 and the transmission of multiple function, determine the time interval requirement between the subaddressing communication being re-used;
The data processing time of antenna communication is 500ms, and the data processing time and the synchronous serial interface switch control processing time that are designated as TP_1, side-sway control are all the control cycle time of 1 control computing machine, are designated as TP_2 and TP_3.The time interval between twice communication in subaddressing is set to maximal value between TP_1 and TP_2 and TP_3 and adds the communication time of subaddressing.
(4) injecting command function need to be by injecting instruction 1 subaddressing, inject instruction 2 subaddressings, inject instruction 3 subaddressings, inject instruction 4 subaddressings and injection complete these 5 subaddressings, subaddressing and jointly complete, according to functional requirement, first determine the sequencing of each subaddressing communication, the communication time of these subaddressings of then determining according to step 2, the time interval that obtains these twice communications in subaddressing is wanted;
The sequencing that injects these 5 subaddressings of command function is to inject instruction 1, injection instruction 2, injection instruction 3, injection instruction 4 and injection to complete, and is labeled as 1 ..5; The communication time of each subaddressing is drawn by step 2: be designated as TC_1 ... TC_5.Message interval between these subaddressings is bus minimum message interval T, and to these subaddressings, the time interval between twice communication is TC_1+TC_2+...+TC_5+5*T;
(5) sequential of all subaddressings is determined
Step (3) and step (4) have been determined the time interval requirement of bus command and injection twice communication in command function subaddressing, and the time interval of twice communication of all the other subaddressings is defined as communication time and adds bus minimum message interval.
In a word, the present invention is applicable in embedded system 1553B communication.Therefore adopt the method can determine at the software development initial stage time index of reasonable, avoided mistake to be incorporated into the problem in subsequent design, improved the credibility of software.

Claims (1)

1. the sequential that ensures 1553B bus communication sequential correctness is determined a method, it is characterized in that performing step is as follows:
(1) 1553B bus comprises that 32 receive subaddressing and 32 transmission subaddressings, determine the communication modes of subaddressing: single message mode or circular buffering mode according to the byte number of data transmission;
(2) according to the communication modes obtaining in step 1, the time needing while determining the communication of each subaddressing;
(3) by bus command communication subaddressing, complete antenna communication, side-sway control and synchronous serial interface switch control functions, belong to the situation of the same subaddressing of multiple multiplexing functions, according to the data processing time of the communication time obtaining in step (2) and the transmission of these functions, determine the time interval requirement between the subaddressing communication being re-used;
(4) injecting command function need to be by injecting instruction 1 subaddressing, inject instruction 2 subaddressings, inject 3 instruction subaddressings, inject instruction 4 subaddressings and injection complete these 5 subaddressings, subaddressing and jointly complete, according to functional requirement, first determine the sequencing of each subaddressing communication, the communication time of these subaddressings of then determining according to step (2), obtains the time interval requirement of these twice communications in subaddressing;
(5) sequential of all subaddressings is determined
Step (3) and step (4) have been determined the time interval requirement of bus command and injection twice communication in command function subaddressing, and the time interval of twice communication of all the other subaddressings is defined as communication time and adds bus minimum message interval.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106411675A (en) * 2016-09-19 2017-02-15 北京控制工程研究所 Centralized bus timing control method based on time slice planning
CN111541595A (en) * 2020-04-16 2020-08-14 上海航天计算机技术研究所 1553B bus data communication method and system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089953A (en) * 1987-12-28 1992-02-18 Sundstrand Corporation Control and arbitration unit
CN201707588U (en) * 2010-05-06 2011-01-12 北京航天自动控制研究所 Control system integrated controller based on 1553B bus
CN102141971A (en) * 2011-01-13 2011-08-03 哈尔滨工业大学 1553B hardware timed communication module with high-capacity storage function

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089953A (en) * 1987-12-28 1992-02-18 Sundstrand Corporation Control and arbitration unit
CN201707588U (en) * 2010-05-06 2011-01-12 北京航天自动控制研究所 Control system integrated controller based on 1553B bus
CN102141971A (en) * 2011-01-13 2011-08-03 哈尔滨工业大学 1553B hardware timed communication module with high-capacity storage function

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
陈玉祥等: "基于SPARDL的模型和程序一致性测试", 《计算机应用研究》, vol. 30, no. 3, 31 March 2013 (2013-03-31), pages 787 - 791 *
黄波: "1553B总线控制系统时间同步设计", 《航天控制》, vol. 26, no. 6, 31 December 2008 (2008-12-31), pages 70 - 73 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106411675A (en) * 2016-09-19 2017-02-15 北京控制工程研究所 Centralized bus timing control method based on time slice planning
CN106411675B (en) * 2016-09-19 2019-04-09 北京控制工程研究所 A kind of centralized bus timing control method based on timeslice planning
CN111541595A (en) * 2020-04-16 2020-08-14 上海航天计算机技术研究所 1553B bus data communication method and system

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