CN106411675A - Centralized bus timing control method based on time slice planning - Google Patents
Centralized bus timing control method based on time slice planning Download PDFInfo
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- CN106411675A CN106411675A CN201610833842.4A CN201610833842A CN106411675A CN 106411675 A CN106411675 A CN 106411675A CN 201610833842 A CN201610833842 A CN 201610833842A CN 106411675 A CN106411675 A CN 106411675A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
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Abstract
The invention discloses a centralized bus timing control method based on time slice planning. The method comprises the following steps: a step of sending a fast frame message to an ADU on a comprehensive satellite electronic system; a step of reading closed loop feedback data sent back by the ADU from a BC message stack after delaying for 1.6ms; a step of sending message frames of a type A and or message frames a type B according to 64ms cycle count CNT1 and 448ms cycle count CNT2; a step of reading telemeasuring data sent back a RT from a BC message stack within a next control period; and a step of performing bus fault judgment by using CMU software within each control period, judging a bus communication state of BC and RT according to a RT message state character, and switching from a bus A to a bus B. According to the centralized bus timing control method disclosed by the invention, the bus operation is strictly controlled within one control period, thereby avoiding temporary message frame reception and transmission caused by emergency, improving the communication instantaneity of the system, reducing the bus load and ensuring the predictability of the operation state of the system.
Description
Technical field
The present invention relates to a kind of centralized bus timing control method based on timeslice planning, belong to embedded software neck
Domain is it is adaptable to the communication construction of the spaceborne application software of Integrated Electronic System designs.
Background technology
In spacecraft (satellite or airship) 1553B bus network, center-controlling computer is as bus control unit (BC)
Initiate data communication, other units instruct and response as remote terminal (RT) response data.Traditional spacecraft bus communication
In design, the main bus message frame sending method adopting based on event, this method has two kinds of limitation：1) real-time is not
By force.BC initiates message frame for triggering to RT with event, and the establishment of data, transmitting-receiving have obvious aperiodicity, for length not
One message, because the difference that the delivery time brings can lead to system real time to decline.2) system action is unpredictable.Center controls
Calculate and read input, output control instruction is all realized by 1553B bus message, if message communicating is not in accordance with fixation
The mode of time point creates, receive and dispatch, and may result in program operation process and does not know from the execution moment being input to output, is
System running status also can become unpredictable because of " chain reaction ".
Content of the invention
Present invention solves the technical problem that being：Overcome prior art not enough, propose a kind of concentration based on timeslice planning
Formula bus timing method for designing, achieves the real-time Communication for Power of BC and RT in Integrated Electronic System in bus management task, is based on
The unified timing Design strategy of timeslice planning is achieved bus data transmission and is processed with reception and bus failure, and bus timing sets
Meter is rationally efficient, and system action is measurable, avoid the situation initiating to communicate that happens suddenly, it can in addition contain reduce bus load, it is to avoid
Bus data frame collides.
The technology of the present invention solution is：A kind of centralized bus timing control method based on timeslice planning, step
As follows：
1) send fast frame message to the ADU on satellite Integrated Electronic System, including control instruction message and closed loop feedback number
According to message；Described satellite Integrated Electronic System includes central manage-ment unit CMU, platform service unit PFISU, load business unit
PLISU and actuator driver element ADU, each unit passes through 1553B bus communication；Wherein CMU is the core of Integrated Electronic System
The heart, initiates data communication as bus control unit BC, and other units instruct and response as remote terminal RT response data；
2) the closed loop feedback data of ADU loopback after time delay 1.6ms, is read from BC message stack；
3) it is handled as follows according to 64ms cycle count CNT1 value：
As CNT1=0, create and initiate the A class message frame of BC and ADU；
As CNT1=1, create and initiate the A class message frame of BC and PFISU；
As CNT1=2, create and initiate the A class message frame of BC and PLISU；
As CNT1=3, it is left intact；
As CNT1=4, counting CNT2 is rotated according to the 448ms cycle and is handled as follows：
As CNT2=0, CMU completes a significant data packing and processes；
As CNT2=1, create and initiate the B class message frame of BC and ADU；
As CNT2=2, create and initiate the B class message frame of BC and PFISU；
As CNT2=3, create and initiate the B class message frame of BC and PLISU；
When CNT2=4～141, it is left intact；
When CNT1=5,6, it is left intact；
CNT2 is incremented by 1；
The described 64ms cycle rotates counter cnt 1, initially sets to 0, and every controlling cycle is incremented by 1, and in 0～6 rotation, the cycle counts
When 7 × 64ms=448ms；
The described 448ms cycle rotates counting CNT2 device, initially sets to 0, and every 448ms is incremented by 1, and in 0～141 rotation, the cycle counts
When 142 × 448ms=63.616s；
Described A class message frame includes telecommand message, telemetry message and remote measurement duties instruction message；
Described B class message frame includes significant data message and significant data duties instruction message；
4), after next controlling cycle enters subtask 4 1553B bus management task, CMU reads RT from BC message stack
The telemetry of loopback；
As CNT1=0, fetch the telemetry of ADU；
As CNT1=1, fetch the telemetry of PFISU；
As CNT1=2, fetch the telemetry of PLISU；
CNT1 is incremented by 1；
5) every controlling cycle CMU carries out bus failure judgement, judges the bus communication of BC and RT according to RT message status word
State, if sentence bus communication mistake, the bus run of BC and RT is switched to B bus by A bus.
The present invention compared with prior art has the advantage that：
1) real-time is higher, bus operation is strict controlled in a controlling cycle, it is to avoid what accident led to faces
When property message frame is received and dispatched；
2) system action is measurable, and the establishment of bus communication data, transmission and reception are all in the triggering of set time point, from
The running state of programs inputting, processing output all can be predicted.
3) the above advantage of the present invention can improve system real-time communication, reduce bus load, meet satellite data very well
The mission requirements that interactive quantity is big, real-time is high, bus management becomes increasingly complex.
Brief description
Fig. 1 is eastern three B platform Integrated Electronic System 1553B bus topolopies；
Fig. 2 is the distribution of controlling cycle subtask time；
Fig. 3 is 1553B bus management task communication sequential；
Fig. 4 is to count, according to controlling cycle, data is activation and the reception that rotation realizes BC and RT；
Fig. 5 is significant data packing and significant data transmission processe strategy.
Specific embodiment
Certain satellite Integrated Electronic System is by central manage-ment unit CMU, platform service unit (PFISU), load business unit
(PLISU) form with actuator driver element (ADU), each unit passes through 1553B bus communication, and wherein CMU is integrated electronicses
The core of system, initiates data communication as bus control unit (BC), and other units refer to as remote terminal (RT) response data
Order response.The spaceborne application software of Integrated Electronic System realizes bus control unit function, periodically communicates with each RT end, thus completing
The data management of Integrated Electronic System, network topology structure is as shown in figure 1, real needs are as follows：
1st, CMU application software controlling cycle is 64ms, and that is, every 64ms carries out a data management, and communication cycle must be to control
Cycle processed is divided for timeslice.One controlling cycle comprises 4 subtasks, and the son that all bus operations are limited in 12ms is appointed
It is engaged in completing, as shown in Figure 2 in 4 1553B bus management tasks.
2nd, the present invention is mainly using following 3 kinds of 1553B message formats：
1)BC-RT：BC sends a reception command word to RT, is followed by the data word of length-specific.RT is receiving
After command word data word, send a status word after carrying out message legitimate verification to BC；
2)RT-BC：BC sends a transmission command word to RT first, and RT is receiving command word and carrying out legitimate verification
Send a status word afterwards to BC end, be followed by the data word of length-specific；
3) the BC-RT mode order with one data word：BC sends a reception command word to RT, after carry one
The data word of 16；
3rd, the every controlling cycle of CMU application software and ADU carry out fast frame traffic, including control instruction message and closed loop feedback number
According to collection message, message format is respectively single message of BC-RT and single message of RT-BC；
4th, every 7 controlling cycles of CMU application software, i.e. 448ms, complete slow frame traffic with ADU, PFISU, PLISU respectively,
Including control instruction message, Telemetry Data Acquisition message and the duties instruction message for data syn-chronization, message format is respectively
Single message of BC-RT, single message of RT-BC and the BC-RT mode order with one data word.
5th, CMU application software preserves significant data with fixed time period to RT end, and this time cycle is less than 64S, number
According to scale for 2K byte it is desirable to the data sending is identical, it is sent to ADU, PFISU, PLISU in triplicate respectively.Message lattice
Formula is the cyclic buffer message of BC-RT and the BC-RT mode command messages with one data word.
6th, each controlling cycle of CMU application software all enters row bus abnormality processing, switches to B bus from A bus.
According to the communication requirement of Integrated Electronic System, the present invention is using the centralized bus timing control based on timeslice planning
Method processed, design principle is as follows：
1) real-time demand according to BC and RT, using periodic timing design, reduces bus load.
2) Frame is created for target with RT, avoid comprising in a frame to be sent to the message of multiple RT as far as possible, so process just
Process in bus failure, when finding, in a frame, error message occurs, whole frame can be abandoned, do not affect the logical of BC and other RT
Letter；
3) BC does not retry strategy using chip-scale message, transfers to application layer process completely, it is to avoid beat after occurring retrying for 1,2 times
Disorderly former sequential；
4) BC does not adopt frame abort sending strategy, according to message status word comprehensive descision after unconditional transmission message frame
Bus failure；
5) BC completes data transmit-receive using inquiry mode, thus avoid the sequential interrupting bringing conflicting with data access.
Further illustrate below in conjunction with the accompanying drawings：
According to the bus communication demand above describing, complete all bus data transmitting-receivings in a controlling cycle domestic demand, no
Only include the fast frame traffic of the BC with 64ms as cycle and ADU, also include with 448ms for cycle BC and ADU, PFISU, PLISU
Slow frame traffic, additionally include with less than 64S fixed time period significant data preserve task.The present invention devises base
In the bus timing control method of timeslice, initiate two message frames in a 64ms controlling cycle：One frame is according to 64ms
Cycle rotation counts the BC initiating and communicate with ADU fast frame, and another frame is rotate under the BC and certain of counting initiation according to the 448ms cycle
The slow frame of communication of position machine or significant data preserve frame.All bus operations all concentrate in the bus management task of 12ms, sequential
Design is as shown in Figure 3.
Wherein, it is related to enumerator to be defined as follows：
● the 64ms cycle rotates counter cnt 1, initially sets to 0, and every controlling cycle is incremented by 1, in 0～6 rotation, cycle timing
For 7 × 64ms=448ms.
● the 448ms cycle rotates counter cnt 2, initially sets to 0, and every 448ms is incremented by 1, in 0～141 rotation, cycle timing
For 142 × 448ms=63.616s.
It is related to message frame to be defined as：
● A class message frame is made up of telecommand message, telemetry message and remote measurement duties instruction message；
● B class message frame is made up of significant data message and significant data duties instruction message.
Fig. 3 is flow chart of the present invention, and step is described as follows：
1. step sends fast frame message to ADU, including control instruction message and closed loop feedback data-message；
Step, 2. after time delay 1.6ms, reads the closed loop feedback data of ADU loopback from BC message stack；
3. step is handled as follows according to 64ms cycle count CNT1 value, and flow process is as shown in Figure 4：
As CNT1=0, create and initiate the A class message frame of BC and ADU；
As CNT1=1, create and initiate the A class message frame of BC and PFISU；
As CNT1=2, create and initiate the A class message frame of BC and PLISU；
As CNT1=3, it is left intact；
As CNT1=4, counting CNT2 value is rotated according to the 448ms cycle and is handled as follows, flow process is as shown in Figure 5：
As CNT2=0, CMU software completes a significant data packing；
As CNT2=1, create and initiate the B class message frame of BC and ADU；
As CNT2=2, create and initiate the B class message frame of BC and PFISU；
As CNT2=3, create and initiate the B class message frame of BC and PLISU；
CNT2 is incremented by 1；Note：During CNT1=4, CNT2 increases 1 certainly from increasing 1, i.e. every 448ms every time
When CNT2=4～141, it is left intact.
When CNT1=5,6, it is left intact.
, 4. after the 1553B bus management task of next controlling cycle entrance subtask 4, CMU software is from BC message for step
Stack reads the telemetry of RT loopback；
As CNT1=0, fetch the telemetry of ADU loopback；
As CNT1=1, fetch the telemetry of PFISU loopback；
As CNT1=2, fetch the telemetry of PLISU loopback.
CNT1 is from increasing 1；Note：Change controlling cycle to count, prepare to communicate with next RT
5. every controlling cycle carries out bus failure judgement to step, judges the bus communication of BC and RT according to RT message status word
State, if sentence bus failure, the bus run of BC and RT is switched to B bus by A bus.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (1)
1. a kind of centralized bus timing control method based on timeslice planning is it is characterised in that step is as follows：
1) send fast frame message to the ADU on satellite Integrated Electronic System, disappear including control instruction message and closed loop feedback data
Breath；Described satellite Integrated Electronic System includes central manage-ment unit CMU, platform service unit PFISU, load business unit
PLISU and actuator driver element ADU, each unit passes through 1553B bus communication；Wherein CMU is the core of Integrated Electronic System
The heart, initiates data communication as bus control unit BC, and other units instruct and response as remote terminal RT response data；
2) the closed loop feedback data of ADU loopback after time delay 1.6ms, is read from BC message stack；
3) it is handled as follows according to 64ms cycle count CNT1 value：
As CNT1=0, create and initiate the A class message frame of BC and ADU；
As CNT1=1, create and initiate the A class message frame of BC and PFISU；
As CNT1=2, create and initiate the A class message frame of BC and PLISU；
As CNT1=3, it is left intact；
As CNT1=4, counting CNT2 is rotated according to the 448ms cycle and is handled as follows：
As CNT2=0, CMU completes a significant data packing and processes；
As CNT2=1, create and initiate the B class message frame of BC and ADU；
As CNT2=2, create and initiate the B class message frame of BC and PFISU；
As CNT2=3, create and initiate the B class message frame of BC and PLISU；
When CNT2=4～141, it is left intact；
When CNT1=5,6, it is left intact；
CNT2 is incremented by 1；
The described 64ms cycle rotates counter cnt 1, initially sets to 0, and every controlling cycle is incremented by 1, in 0～6 rotation, cycle timing 7 ×
64ms=448ms；
The described 448ms cycle rotates counting CNT2 device, initially sets to 0, and every 448ms is incremented by 1, in 0～141 rotation, cycle timing 142
× 448ms=63.616s；
Described A class message frame includes telecommand message, telemetry message and remote measurement duties instruction message；
Described B class message frame includes significant data message and significant data duties instruction message；
4), after next controlling cycle enters subtask 4 1553B bus management task, CMU reads RT loopback from BC message stack
Telemetry；
As CNT1=0, fetch the telemetry of ADU；
As CNT1=1, fetch the telemetry of PFISU；
As CNT1=2, fetch the telemetry of PLISU；
CNT1 is incremented by 1；
5) every controlling cycle CMU carries out bus failure judgement, judges the bus communication state of BC and RT according to RT message status word,
If sentence bus communication mistake, the bus run of BC and RT is switched to B bus by A bus.
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| CN112415885A (en) * | 2020-11-30 | 2021-02-26 | 北京控制工程研究所 | Universal bus management method suitable for multi-machine multi-bus redundancy fault-tolerant system |
| CN116074156A (en) * | 2022-12-29 | 2023-05-05 | 北京机电工程研究所 | 1553B protocol design method for avoiding data conflict through time sequence design |
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