CN103731103A - Fully-differential microwave millimeter wave frequency multiplier - Google Patents

Fully-differential microwave millimeter wave frequency multiplier Download PDF

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CN103731103A
CN103731103A CN201410023534.6A CN201410023534A CN103731103A CN 103731103 A CN103731103 A CN 103731103A CN 201410023534 A CN201410023534 A CN 201410023534A CN 103731103 A CN103731103 A CN 103731103A
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frequency
transmission line
unit
frequency multiplication
connects
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CN103731103B (en
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李智群
刘扬
李芹
王志功
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Shenzhen Times Suxin Technology Co Ltd
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Southeast University
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Abstract

A fully-differential frequency multiplier with high conversion gain is provided with a frequency multiplication unit, two same transmission line units and a negative resistance strengthening unit. The frequency multiplication unit adopts a complementary pushing-pushing structure, the transmission line units adopt coplanar waveguide structures, the negative resistance strengthening unit adopts a complementary intersected coupling structure, the frequency multiplication unit achieves frequency multiplication of input signals and adopts one PMOS pushing-pushing frequency multiplier and one NMOS pipe pushing-pushing frequency multiplier which are connected in parallel, direct-current power supply and output alternating-current signal blocking are achieved by utilizing the transmission line units, the negative resistance strengthening unit strengthens output alternating-current signals, and finally a circuit outputs differential voltage signals subjected to the frequency multiplication through a capacitor.

Description

A kind of fully differential microwave and millimeter wave frequency multiplier
Technical field
The present invention relates to the frequency multiplier in microwave and millimetre-wave circuit, especially a kind of fully differential microwave and millimeter wave frequency multiplier, adopt CMOS technique, in microwave and millimetre-wave circuit, there is greater advantage, project organization is simple, when fully differential output signal is provided, conversion gain can be increased substantially.
Background technology
Frequency multiplier is the conventional device in microwave and millimetre-wave circuit, and its effect is that the frequency of input signal is improved, and according to the multiple improving, can be divided into varactor doubler, frequency tripler etc.The generation of frequency multiplier is because when frequency applications, and because the Q value of the passive devices such as inductance, electric capacity is lower, oscillator need to consume larger electric current ability starting of oscillation, and therefore the phase noise of oscillator also can worsen.So need to first generate an intermediate frequency, and then utilize frequency multiplier to obtain the frequency of target.The frequency multiplier circuit I P core that designs a low-power consumption, high-conversion-gain has application prospect and using value comparatively widely.
Microwave and millimeter wave refers generally to the frequency range of 30GHz to 300GHz.The wavelength of this frequency range, in 1cm, designs for integrated circuit and PCB, and the length of holding wire is close with wavelength or exceed wavelength, need to consider transmission line effect.
Push-push configuration frequency multiplier is widely used in the design of frequency multiplier, and main cause is that it has simple circuit structure, and traditional pushes away-push away frequency multiplier circuit as shown in Figure 1, and its operation principle as shown in Figure 2.Two metal-oxide-semiconductor bias voltages are all arranged on cut-in voltage place, suppose to have differential signal Vin that one group of cycle is T to send into the input of frequency multiplier, as shown in Figure 2 (a) shows, MN1 conducting in the positive half cycle (0～T/2) of signal, MN2 turn-offs; MN2 conducting in the negative half period (T/2～T) of signal, MN1 turn-offs.Therefore can form waveform as shown in Figure 2 (b) at M point place, pass through again the filtering of inductance, electric capacity and parasitic capacitance, high fdrequency component is by filtering, DC component is isolated, finally form as 2(c) as shown in signal output waveform, now the cycle of output signal becomes T/2, and circuit has been realized double frequency function.
Traditional push-push configuration frequency multiplier has following shortcoming: the firstth, and conversion gain is low.Tradition push-push configuration frequency multiplier conversion gain generally-below 10dB.This is because the structure of circuit determines.Because the biasing of metal-oxide-semiconductor is placed in the position of cut-in voltage, therefore limited the amplification of metal-oxide-semiconductor, cause amplitude output signal limited, even and if increase circuit power consumption and also do not have remarkable income.
The secondth, input signal is difference, and output signal is single-ended, and the port number of input/output signal does not mate.As shown in Figure 1, traditional push-push configuration frequency multiplier is connected the drain electrode of two metal-oxide-semiconductors, and draws output signal, therefore only has Single-end output signal.
Summary of the invention
The object of the invention is the deficiency for overcoming traditional push-push configuration frequency multiplier, propose a kind of fully differential microwave and millimeter wave frequency multiplier, can guarantee on the basis of fully differential input and output, increase substantially circuit conversion gain.
The technical scheme that the present invention takes is as follows: a kind of fully differential microwave and millimeter wave frequency multiplier, is characterized in that: be provided with frequency multiplication unit, transmission line unit that negative resistance enhancement unit is identical with two, difference radio-frequency input signals V in+, V in-connect respectively positive input terminal 1-In+ and the negative input end 1-In of frequency multiplication unit -, the output 1-Out of frequency multiplication unit +and 1-Out -connect respectively positive input terminal 3-In+ and the negative input end 3-In of negative resistance enhancement unit -, meanwhile, the output 1-Out of frequency multiplication unit +and 1-Out -a transmission line unit of each connection, the other end of two transmission line unit connects respectively VDD-to-VSS line, the positive output end 3-Out+ of negative resistance enhancement unit and negative output terminal 3-Out -output difference radio-frequency signal Vout; Wherein:
Frequency multiplication unit is provided with a pair of differential input end mouth 1-In +and 1-In -, a pair of bias input end mouth V bias_Pand V bias_N, a pair of difference output port 1-Out +and 1-Out -, comprising PMOS pipe MP1, MP2, NMOS manages MN1, MN2, capacitance CP1, CP2, CN1, CN2, biasing resistor RP1, RP2, RN1, RN2, Input matching inductance L 1 and L2, differential input end mouth 1-In+ connects difference radio-frequency input signals V in+one end with inductance L 1, the other end of inductance L 1 connects one end of capacitance CP1 and CN1, the other end of capacitance CP1 connects the PMOS pipe grid of MP1 and one end of biasing resistor RP1, and the other end of capacitance CN1 connects the PMOS pipe grid of MN1 and one end of biasing resistor RN1; Correspondingly, differential input end mouth 1-In-connects difference radio-frequency input signals V in-one end with inductance L 2, the other end of inductance L 2 connects one end of capacitance CP2 and CN2, the other end of capacitance CP2 connects the PMOS pipe grid of MP2 and one end of biasing resistor RP2, and the other end of capacitance CN2 connects the PMOS pipe grid of MN2 and one end of biasing resistor RN2; The other end of biasing resistor RP1 and RP2 is connected bias input end mouth V jointly bias_P, the other end of biasing resistor RN1 and RN2 is connected bias input end mouth V jointly bias_N, the PMOS pipe source electrode of MP1 and the source electrode of MP2, the NMOS pipe drain electrode of MN1 and the drain electrode of MN2 link together, as the difference output port 1-Out of frequency multiplication unit +, the PMOS pipe drain electrode of MP1 and the drain electrode of MP2, the NMOS pipe source electrode of MN1 and the source electrode of MN2 link together, as the difference output port 1-Out of frequency multiplication unit -;
Negative resistance enhancement unit is provided with a pair of differential input end mouth 3-In +and 3-In -, a pair of difference output port 3-Out +and 3-Out -, comprising PMOS pipe MP3, MP4, NMOS manages MN3, MN4, inductance L 3, capacitor C 3, C4, C5, C6; The source electrode of PMOS pipe MP3 and MP4 interconnects and is connected power vd D, source electrode interconnection the ground connection of NMOS pipe MN3 and MN4, the grid of one end, one end of inductance L 3 and the drain electrode of NMOS pipe MN3 and the NMOS pipe MN4 of the grid of the drain electrode of PMOS pipe MP3 and PMOS pipe MP4, capacitor C 3, C5 links together, the difference output port 1-Out of the other end connection frequency multiplication unit of capacitor C 3 +, the other end of capacitor C 5 is the output difference radio-frequency signal Vout of negative resistance enhancement unit +, the drain electrode of one end, the other end of inductance L 3 and the grid of NMOS pipe MN3 and the NMOS pipe MN4 of the drain electrode of the grid of PMOS pipe MP3 and PMOS pipe MP4, capacitor C 4, C6 links together, the difference output port 1-Out of the other end connection frequency multiplication unit of capacitor C 4 -, the other end of capacitor C 6 is the output difference radio-frequency signal Vout of negative resistance enhancement unit -;
Two transmission line unit are equipped with a transmission lines, and its length is output frequency 1/4th, and one end of the transmission line of one of them transmission line unit connects power vd D, and the other end connects the difference output port 1-Out of frequency multiplication unit +, one end ground connection of the transmission line of another transmission line unit, the other end connects the difference output port 1-Out of frequency multiplication unit -.
Transmission line in said transmission line unit comprises coplanar waveguide transmission line, microstrip transmission line or other transmission line for microwave and millimeter wave.
NMOS pipe in frequency multiplication unit and negative resistance enhancement unit can be replaced to NPN type triode, PMOS pipe replaces to positive-negative-positive triode.
Advantage of the present invention and remarkable result (following simulation result all carries out under the frequency range of 25GHz input, 50GHz output, and by adjusting component parameters, structure of the present invention can be applied to other each frequency ranges):
(1) fully differential output.As shown in Figure 1, traditional pushes away-pushes away frequency multiplier because reasons in structure can only generate Single-end output signal in the drain electrode of metal-oxide-semiconductor, under the occasion of some use differential signals, needs to add in addition Ba Lun (Balun) to obtain differential signal.And Ba Lun can make the amplitude of output signal reduce.The present invention adopts complementary push-push configuration, can obtain the differential output signal that amplitude is comparatively balanced.
(2) high-conversion-gain.In tradition push-push configuration frequency multiplier, because the biasing of metal-oxide-semiconductor is placed in the position of cut-in voltage, therefore limit the amplification of metal-oxide-semiconductor, caused amplitude output signal lower.The present invention adopts negative resistance enhancing technology, can increase substantially the power of output signal.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of traditional push-push configuration frequency multiplier;
Fig. 2 is the fundamental diagram of traditional push-push configuration frequency multiplier;
Fig. 3 is the circuit block diagram of frequency multiplier of the present invention;
Fig. 4 is the circuit theory diagrams of frequency multiplier of the present invention;
Fig. 5 is the equivalent fundamental diagram of frequency multiplication unit in frequency multiplier of the present invention;
Fig. 6 is the equivalent fundamental diagram of negative resistance enhancement unit in frequency multiplier of the present invention;
Fig. 7 is the circuit theory diagrams that adopt the frequency multiplier of the present invention of bipolar device.
Embodiment
Referring to Fig. 3, the present invention is provided with frequency multiplication unit 1, two identical transmission line unit 2 and negative resistance enhancement unit 3.Difference radio-frequency input signals V in+, V in-connect respectively positive input terminal 1-In+ and the negative input end 1-In of frequency multiplication unit 1 -, the output 1-Out of frequency multiplication unit 1 +and 1-Out -connect respectively positive input terminal 3-In+ and the negative input end 3-In of negative resistance enhancement unit 3 -, meanwhile, the output 1-Out of frequency multiplication unit 1 +and 1-Out -an each transmission line unit 2, the positive output end 3-Out+ of negative resistance enhancement unit 3 and negative output terminal 3-Out of connecting -output difference radio-frequency signal Vout.One end of two transmission line unit 2 connects respectively VDD-to-VSS line, and the other end connects respectively the output 1-Out of frequency multiplication unit 1 +and 1-Out -.
Referring to Fig. 4, frequency multiplication unit 1 comprises PMOS pipe MP1, MP2, and NMOS manages MN1, MN2, capacitance CP1, CP2, CN1, CN2, biasing resistor RP1, RP2, RN1, RN2, Input matching inductance L 1 and L2.Transmission line unit 2 comprises transmission line TL.The PMOS that comprises of negative resistance enhancement unit 3 manages MP3, MP4, and NMOS manages MN3, MN4, inductance L 3, capacitor C 3, C4, C5, C6.The annexation of circuit is as follows:
The difference output end of frequency multiplication unit 1 connects respectively two identical transmission line unit 2, accesses the difference input of negative resistance enhancement unit 3 simultaneously.The other end of two transmission line unit 2 connects respectively VDD-to-VSS line.Transmission line unit 2 is comprised of a coplanar waveguide transmission line, the quarter-wave that length of transmission line is output frequency.
Frequency multiplication unit 1 has adopted the modified model push-push configuration of PMOS and NMOS complementation, and its operation principle as shown in Figure 5.Together with the source electrode of PMOS pipe MP1 and MP2 is connected to drain electrode, form a push-push configuration frequency multiplier, two tie points are exported as difference, as shown in Fig. 5 (a).But because the amplifying power of metal-oxide-semiconductor source electrode and drain electrode is different, there is larger deviation in the amplitude of this differential output signal.NMOS pipe MN1, MN2 build another push-push configuration frequency multiplier, as shown in Fig. 5 (b).Make two frequency multipliers and connect, as shown in Fig. 5 (c), and the bias voltage by adjusting PMOS and NMOS is to obtain the comparatively differential signal of balance.In actual use, need to realize input impedance coupling by inductance L 1, L2, by resistance R P1, RP2, RN1, RN2, respectively the grid of MP1, MP2, MN1, MN2 is added to bias voltage, and carry out isolated DC level by capacitor C P1, CP2, CN1, CN2.
Transmission line unit 2 consists of a transmission lines, and its length is output frequency 1/4th.According to the impedance transformation principle of transmission line, when this section of transmission line one termination DC power supply or ground connection, another port is high resistant for output frequency, can effectively intercept AC signal, and signal is transmitted to negative resistance enhancement unit 3.Transmission line can be realized with the microwave of arbitrary structures and millimeter wave transmission line, as co-planar waveguide, microstrip line etc., only needs to guarantee that its length is output wavelength 1/4th.
The circuit theory of negative resistance enhancement unit 3 as shown in Figure 6 (a), is used complementary chiasma coupled structure to build negative resistance, and the inductance in figure plays the effect of the operating frequency of tuning negative resistance.As shown in Figure 6 (b), node 1 and 2 is a pair of differential signal output point to the operation principle of negative resistance enhancing technology, R l1and R l2for the load resistance of difference output, v 1and v 2for corresponding differential output voltage, i 1and i 2for corresponding difference output current.A negative resistance-R of access in the middle of differential output signal, as output voltage v 1>v 2time, negative resistance flows to 1 current i by producing one from 2 neg, this electric current can strengthen output current, and the electric current in final load can become i l1=i 1+ i negand i l2=i 2-i neg.
The present invention improves on the basis of traditional push-push configuration frequency multiplier, has realized fully differential input and output, and utilizes negative resistance enhancing technology to improve conversion gain.Frequency multiplication unit 1 adopts complementary push-push configuration, transmission line unit 2 adopts coplanar waveguide structure, negative resistance enhancement unit 3 adopts complementary chiasma coupled structure, the frequency multiplication of input signal is realized in frequency multiplication unit 1, adopt a PMOS to push away-push away frequency multiplier and a NMOS pipe pushes away-push away frequency multiplier parallel connection, utilize transmission line unit 2 realize direct current supply and intercept output AC signal, by negative resistance enhancement unit 3, alternating current output signal is strengthened, final circuit is exported the differential voltage signal after frequency multiplication by electric capacity.
Although what provide in the present invention is the simulation result of 25GHz input band, by adjusting component parameters of the present invention, the present invention is equally applicable to other frequency ranges.For example, regulate the inductance value of L1, L2, make Input matching in incoming frequency; Regulate the length of transmission line in transmission line unit 2, make it equal the quarter-wave of output frequency; The inductance value that regulates L3, makes negative resistance enhancement unit 3 on output frequency, be negative resistance.
Structure of the present invention, except realizing by field effect transistor, also can realize with bipolar transistor.While realizing with bipolar transistor, only NMOS pipe need to be replaced to NPN type triode, PMOS pipe replaces to positive-negative-positive triode.Specific embodiments as shown in Figure 7.

Claims (3)

1. a fully differential microwave and millimeter wave frequency multiplier, is characterized in that: be provided with frequency multiplication unit, transmission line unit that negative resistance enhancement unit is identical with two, difference radio-frequency input signals V in+, V in-connect respectively positive input terminal 1-In+ and the negative input end 1-In of frequency multiplication unit -, the output 1-Out of frequency multiplication unit +and 1-Out -connect respectively positive input terminal 3-In+ and the negative input end 3-In of negative resistance enhancement unit -, meanwhile, the output 1-Out of frequency multiplication unit +and 1-Out -a transmission line unit of each connection, the other end of two transmission line unit connects respectively VDD-to-VSS line, the positive output end 3-Out+ of negative resistance enhancement unit and negative output terminal 3-Out -output difference radio-frequency signal Vout; Wherein:
Frequency multiplication unit is provided with a pair of differential input end mouth 1-In +and 1-In -, a pair of bias input end mouth V bias_Pand V bias_N, a pair of difference output port 1-Out +and 1-Out -, comprising PMOS pipe MP1, MP2, NMOS manages MN1, MN2, capacitance CP1, CP2, CN1, CN2, biasing resistor RP1, RP2, RN1, RN2, Input matching inductance L 1 and L2, differential input end mouth 1-In+ connects difference radio-frequency input signals V in+one end with inductance L 1, the other end of inductance L 1 connects one end of capacitance CP1 and CN1, the other end of capacitance CP1 connects the PMOS pipe grid of MP1 and one end of biasing resistor RP1, and the other end of capacitance CN1 connects the PMOS pipe grid of MN1 and one end of biasing resistor RN1; Correspondingly, differential input end mouth 1-In-connects difference radio-frequency input signals V in-one end with inductance L 2, the other end of inductance L 2 connects one end of capacitance CP2 and CN2, the other end of capacitance CP2 connects the PMOS pipe grid of MP2 and one end of biasing resistor RP2, and the other end of capacitance CN2 connects the PMOS pipe grid of MN2 and one end of biasing resistor RN2; The other end of biasing resistor RP1 and RP2 is connected bias input end mouth V jointly bias_P, the other end of biasing resistor RN1 and RN2 is connected bias input end mouth V jointly bias_N, the PMOS pipe source electrode of MP1 and the source electrode of MP2, the NMOS pipe drain electrode of MN1 and the drain electrode of MN2 link together, as the difference output port 1-Out of frequency multiplication unit +, the PMOS pipe drain electrode of MP1 and the drain electrode of MP2, the NMOS pipe source electrode of MN1 and the source electrode of MN2 link together, as the difference output port 1-Out of frequency multiplication unit -;
Negative resistance enhancement unit is provided with a pair of differential input end mouth 3-In +and 3-In -, a pair of difference output port 3-Out +and 3-Out -, comprising PMOS pipe MP3, MP4, NMOS manages MN3, MN4, inductance L 3, capacitor C 3, C4, C5, C6; The source electrode of PMOS pipe MP3 and MP4 interconnects and is connected power vd D, source electrode interconnection the ground connection of NMOS pipe MN3 and MN4, the grid of one end, one end of inductance L 3 and the drain electrode of NMOS pipe MN3 and the NMOS pipe MN4 of the grid of the drain electrode of PMOS pipe MP3 and PMOS pipe MP4, capacitor C 3, C5 links together, the difference output port 1-Out of the other end connection frequency multiplication unit of capacitor C 3 +, the other end of capacitor C 5 is the output difference radio-frequency signal Vout of negative resistance enhancement unit +, the drain electrode of one end, the other end of inductance L 3 and the grid of NMOS pipe MN3 and the NMOS pipe MN4 of the drain electrode of the grid of PMOS pipe MP3 and PMOS pipe MP4, capacitor C 4, C6 links together, the difference output port 1-Out of the other end connection frequency multiplication unit of capacitor C 4 -, the other end of capacitor C 6 is the output difference radio-frequency signal Vout of negative resistance enhancement unit -;
Two transmission line unit are equipped with a transmission lines, and its length is output frequency 1/4th, and one end of the transmission line of one of them transmission line unit connects power vd D, and the other end connects the difference output port 1-Out of frequency multiplication unit +, one end ground connection of the transmission line of another transmission line unit, the other end connects the difference output port 1-Out of frequency multiplication unit -.
2. fully differential microwave and millimeter wave frequency multiplier according to claim 1, is characterized in that: the transmission line in said transmission line unit comprises coplanar waveguide transmission line, microstrip transmission line.
3. fully differential microwave and millimeter wave frequency multiplier according to claim 1, is characterized in that: the NMOS pipe in frequency multiplication unit and negative resistance enhancement unit is replaced to NPN type triode, and PMOS pipe replaces to positive-negative-positive triode.
CN201410023534.6A 2014-01-17 2014-01-17 A kind of Fully-differential microwave millimeter wave frequency multiplier Active CN103731103B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107508556A (en) * 2017-08-28 2017-12-22 河海大学 A kind of DE classes frequency multiplier and design method
CN112542994A (en) * 2019-09-20 2021-03-23 意法半导体股份有限公司 Electronic circuit for tripling frequency
CN112671346A (en) * 2020-12-18 2021-04-16 电子科技大学 Broadband frequency multiplier with transconductance enhancement technology and double LC matching networks
US11632090B1 (en) 2021-12-20 2023-04-18 The Chinese University Of Hong Kong, Shenzhen Push-push frequency doubling scheme and circuit based on complementary transistors
CN112542994B (en) * 2019-09-20 2024-06-25 意法半导体股份有限公司 Electronic circuit for frequency tripling

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107508556A (en) * 2017-08-28 2017-12-22 河海大学 A kind of DE classes frequency multiplier and design method
CN112542994A (en) * 2019-09-20 2021-03-23 意法半导体股份有限公司 Electronic circuit for tripling frequency
CN112542994B (en) * 2019-09-20 2024-06-25 意法半导体股份有限公司 Electronic circuit for frequency tripling
CN112671346A (en) * 2020-12-18 2021-04-16 电子科技大学 Broadband frequency multiplier with transconductance enhancement technology and double LC matching networks
US11632090B1 (en) 2021-12-20 2023-04-18 The Chinese University Of Hong Kong, Shenzhen Push-push frequency doubling scheme and circuit based on complementary transistors
WO2023115270A1 (en) * 2021-12-20 2023-06-29 香港中文大学（深圳） Push-push frequency doubler based on complementary transistors

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