CN107508556A - A kind of DE classes frequency multiplier and design method - Google Patents

A kind of DE classes frequency multiplier and design method Download PDF

Info

Publication number
CN107508556A
CN107508556A CN201710748598.6A CN201710748598A CN107508556A CN 107508556 A CN107508556 A CN 107508556A CN 201710748598 A CN201710748598 A CN 201710748598A CN 107508556 A CN107508556 A CN 107508556A
Authority
CN
China
Prior art keywords
inductance
fet
frequency
load resistance
msub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710748598.6A
Other languages
Chinese (zh)
Other versions
CN107508556B (en
Inventor
花再军
陈钊
李建霓
黄凤辰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hohai University HHU
Original Assignee
Hohai University HHU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hohai University HHU filed Critical Hohai University HHU
Priority to CN201710748598.6A priority Critical patent/CN107508556B/en
Publication of CN107508556A publication Critical patent/CN107508556A/en
Application granted granted Critical
Publication of CN107508556B publication Critical patent/CN107508556B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device

Landscapes

  • Amplifiers (AREA)

Abstract

The invention discloses a kind of DE classes frequency multiplier and design method, including direct voltage source, first FET, second FET, first inductance, second inductance, capacitance, Shunt compensation capacitor, LC parallel-tuned circuits and load resistance, capacitance one terminates one end of the first inductance and the second inductance, the other end connects LC parallel-tuned circuits respectively, one end of Shunt compensation capacitor and load resistance, the other end of first inductance concatenates the drain electrode of the first FET, the other end of second inductance concatenates the drain electrode of the second FET, LC parallel-tuned circuits, another termination power of Shunt compensation capacitor and load resistance, first FET S1With connecing power supply, grid meets the first driving voltage, the second FET S to source electrode2Source electrode connects direct voltage source, and grid connects the second driving voltage.The component value that the present invention only adjusts passive device in the case where not changing former DE class A amplifier As structure and drive signal waveform can obtain frequency-doubled signal.

Description

A kind of DE classes frequency multiplier and design method
Technical field
The present invention relates to a kind of DE classes frequency multiplier and design method, belong to frequency multiplier technical field.
Background technology
Frequency multiplier is the important devices in communication, and the source signal frequency of several times can be obtained by frequency multiplier.Transistor times For frequency device except that can realize frequency multiplication, its output signal generally also has power gain.Transistor frequency multiplier amplifies with switching regulator Device is similar, there is D classes, E classes, DE classes etc., generally all has higher efficiency.
The content of the invention
The technical problems to be solved by the invention are the defects of overcoming prior art, there is provided a kind of DE classes frequency multiplier and design Method, the component value of passive device is only adjusted in the case where not changing former DE class A amplifier As structure and drive signal waveform to be obtained Frequency-doubled signal.
In order to solve the above technical problems, the present invention provides a kind of DE classes frequency multiplier, including direct voltage source Vdd, first effect Should pipe S1, the second FET S2, the first inductance L1, the second inductance L2, capacitance CDC, Shunt compensation capacitor C, LC and joint debugging Humorous circuit and load resistance RL；
The capacitance CDCOne the first inductance L of termination1With the second inductance L2One end, capacitance CDCThe other end point LC parallel-tuned circuits, Shunt compensation capacitor C and load resistance R are not metLOne end；The first inductance L1The other end concatenation First FET S1Drain electrode；The second inductance L2The other end concatenate the second FET S2Drain electrode；The LC is in parallel Tuning circuit, Shunt compensation capacitor C and load resistance RLAnother termination power；
The first FET S1With connecing power supply, grid connects the first driving voltage to source electrode；
The second FET S2Source electrode meets direct voltage source Vdd, grid connects the second driving voltage.
Foregoing LC parallel-tuned circuits include tuning capacitance CpWith tuning coil Lp, wherein, tuning capacitance CpBoth ends connect Tuning coil LpBoth ends, resonance is in frequency multiplication target frequency.
The design method of DE class frequency multipliers, comprises the following steps：
1) the drive signal dutycycle of DE classes frequency multiplier is 25%, as the first fet switch S1During disconnection, the first electricity Feel L1In electric current drop to 0, and electric current changes with time rate as 0 so that the first inductance L1Power attenuation be 0；When first Fet switch S2During disconnection, the second inductance L2In electric current drop to 0, and electric current changes with time rate as 0 so that the Two inductance L2Power attenuation be 0；According to this inductance zero-current switching and zero current derivative switch condition, obtain in N frequency multipliers Parameters relationship：
Wherein,
It is multiple of the output voltage amplitude relative to direct current power source voltage,
It is the phase of output voltage,
For load resistance RLInverse,
B=N ω C are Shunt compensation capacitor C susceptance,
X=ω L1=ω L2It is series inductance L1And L2Induction reactance,
The π f of ω=2；
2) design parameter of DE class frequency multipliers, including direct voltage source V are givendd, power output Po, loaded quality factor QLC, driving signal frequency f and frequency multiple N；
3) parameters relationship of step 1), the expression formula of load resistance and the design parameter of DE class frequency multipliers are combined, obtains N times The component parameters of frequency device：Load resistance RL, the first inductance L1, the second inductance L2, Shunt compensation capacitor C, parallel resonant electric capacity CpWith Parallel resonant inductance Lp；
4) the result of calculation design DE class frequency multipliers of step 3) are utilized.
N in foregoing N frequency multipliers is odd number.
Foregoing load resistance RLMeet：
Foregoing parallel resonant electric capacity CpWith parallel resonant inductance LpCalculation formula it is as follows：
What the present invention was reached has the beneficial effect that：In the case where not changing former DE class A amplifier As structure and drive signal waveform only The component value of adjustment passive device can obtain frequency-doubled signal, and keep very high efficiency.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram of DE classes frequency multiplier；
Fig. 2 is a kind of equivalent circuit of DE classes frequency multiplier；
Fig. 3 is drive signal dutycycle when being 25%, N=3, each current-voltage waveform figure of the frequency multiplier of DE classes 3；Fig. 3 (a) is The driving voltage waveform v of first FETDr1(θ)；Fig. 3 (b) is the driving voltage waveform v of the second FETDr2(θ)；Fig. 3 (c) it is to flow through the first FET S1Electric current is1The oscillogram of (θ)；Fig. 3 (d) is to flow through the second FET S2Electric current is2 The oscillogram of (θ)；Fig. 3 (e) is the voltage waveform v of the first FET drainD1(θ)；Fig. 3 (f) is the second FET drain Voltage waveform vD2(θ)；Fig. 3 (g) is output voltage waveforms vo(θ)。
Embodiment
The invention will be further described below.Following examples are only used for the technical side for clearly illustrating the present invention Case, and can not be limited the scope of the invention with this.
As shown in figure 1, the DE classes frequency multiplier of the present invention includes direct voltage source Vdd, the first FET S1, second effect Should pipe S2, the first inductance L1, the second inductance L2, capacitance CDC, Shunt compensation capacitor C, LC parallel-tuned circuit and load resistance RL.In Fig. 1, vDr1(θ) and vDr2(θ) is first and second FET driving voltage, vs2(θ), is2(θ) is the leakage of the second FET Source voltage and the electric current for flowing through it, i1(θ) is the alternating current for flowing through capacitance, vm(θ) is the first inductance L1With the second electricity Feel L2The voltage of tie point, vs1(θ) and is1(θ) is the first FET drain-source voltage and flows through its electric current, ix(θ) is simultaneously Join the electric current in compensating electric capacity C, io(θ) is load resistance RLIn electric current, vo(θ) is the voltage on load resistance, when θ is angle Between, θ=ω t.
Capacitance CDCOne the first inductance L of termination1With the second inductance L2One end, the other end connect respectively LC parallel resonants electricity Road, Shunt compensation capacitor C and load resistance RLOne end.
LC parallel-tuned circuits, Shunt compensation capacitor C and load resistance RLAnother termination power.
First FET S1With connecing power supply, grid connects the first driving voltage to source electrode, and drain series meet the first inductance L1It is another One end.
Second FET S2Source electrode meets direct voltage source Vdd, grid connects the second driving voltage, and drain series connect the second electricity Feel L2The other end.
LC parallel-tuned circuits include tuning capacitance CpWith tuning coil Lp, wherein, tuning capacitance CpBoth ends connection tuning electricity Feel LpBoth ends, resonance is in frequency multiplication target frequency.
Fig. 2 is the equivalent circuit of DE class frequency multipliers.By the first FET S1, the second FET S2It is equivalent to two electricity Press controlling switch.
The drive signal dutycycle of DE class frequency multipliers is 25%.As the first fet switch S1During disconnection, the first inductance L1 In electric current drop to 0, and electric current changes with time rate (i.e. the slope of electric current) as 0 so that the first inductance L1Power damage Consume for 0.As the first fet switch S2During disconnection, the second inductance L2In electric current drop to 0, and electric current changes with time Rate (i.e. the slope of electric current) is 0 so that the second inductance L2Power attenuation be 0.
With above inductance zero-current switching and zero current derivative switch condition, the ginseng in N frequency multipliers (N is odd number) is obtained Number relation：
Wherein：
It is multiple of the output voltage amplitude relative to direct current power source voltage,
It is the phase of output voltage,
For load resistance RLInverse,
B=N ω C are Shunt compensation capacitor C susceptance,
X=ω L1=ω L2It is series inductance L1And L2Induction reactance.
The π f of ω=2.
In order to facilitate the design of N frequency multipliers, design parameter corresponding to odd number N=3,5,7 is listed in table 1：
The parameters relationship of table 1N frequency multipliers
N B/G GX
3 3.562 0.0474
5 10.94 0.0091
7 9.445 0.0076
When Fig. 3 is drive signal dutycycle D=25%, the course of work of the frequency multiplier example of DE classes 3 within a 2 π cycles For：
(1) in the π of 0 ＜ θ≤0.5, as Fig. 3 (a) drive signals make the first FET S1Closure；Such as Fig. 3 (b) drive signals Make the second FET S2Disconnect；As Fig. 3 (c) flows through the first FET S1Electric current iS1(and flow through the first inductance L1Electricity Stream) there is the process of a rising, rise to after peak value and the process of a decline occur, finally to 0, electric current i when reaching 0S1At any time Between derivative also be 0；Such as Fig. 3 (e), the first FET drain voltage is 0, i.e. the first FET S1Both end voltage vS1For 0； Such as Fig. 3 (d), the second FET S is flowed through2Electric current iS2(and flow through the second inductance L2Electric current) be 0；Such as Fig. 3 (f), Two FET S2Disconnect, the second FET drain voltage vD2Change with output voltage.
(2) the first FET S is made in 0.5 π ＜ θ≤π, such as Fig. 3 (a) drive signals1Disconnect；Such as Fig. 3 (b) drive signals Make the second FET S2Disconnect.Fig. 3 (c) flows through the first FET electric current iS1(and flow through the first inductance L1Electric current) be 0；Such as Fig. 3 (e), the first FET S1Disconnect, the first FET drain voltage vD1Change with output voltage；Fig. 3 (d) flows through Second FET electric current iS2(and flow through the second inductance L2Electric current) be 0；Such as Fig. 3 (f), the second FET S2Disconnect, Second FET drain voltage vD2Change with output voltage.
(3) in the π of π ＜ θ≤1.5, as Fig. 3 (a) drive signals make the first FET S1Disconnect；Such as Fig. 3 (b) drive signals Make the second FET S2Closure；Fig. 3 (c) flows through the first FET electric current iS1(and flow through the first inductance L1Electric current) be 0；Such as Fig. 3 (e), the first FET S1Disconnect, the first FET drain voltage vD1Change with output voltage；Fig. 3 (d), stream Cross the second FET S2Electric current iS2(and flow through the second inductance L2Electric current) have one rising process, rise to peak value Occur the process of a decline afterwards, finally to 0, electric current i when reaching 0S2Derivative with the time is also 0；Fig. 3 (f), the second field-effect Pipe drain voltage is equal to direct current power source voltage, i.e. the second FET S2Both end voltage vS2For 0.
(4) in the π of 1.5 π ＜ θ≤2, this operated within range process is the same as (2).As Fig. 3 (a) drive signals make the first FET S1Disconnect；As Fig. 3 (b) drive signals make the second FET S2Disconnect.Fig. 3 (c) flows through the first FET electric current iS1(and Flow through the first inductance L1Electric current) be 0；Such as Fig. 3 (e), the first FET S1Disconnect, the first FET drain voltage vD1With Output voltage changes；Fig. 3 (d) flows through the second FET electric current iS2(and flow through the second inductance L2Electric current) be 0；Such as Fig. 3 (f), the second FET S2Disconnect, the second FET drain voltage vD2Change with output voltage.
Fig. 3 (g) is output voltage waveforms, and output electrical signal voltage is direct voltage source Vdd2.9 times, frequency be driving letter Number 3 times, realize 3 frequencys multiplication.
The design parameter of given DE class frequency multipliers, including direct voltage source Vdd, power output Po, loaded quality factor QLC, The expression formula of driving signal frequency f and frequency multiple N, incorporating parametric relation and load resistance, obtain DE class frequency multiplier elements Each parameter：
Wherein, load resistance meets：
LC parallel-tuned circuits are used to extract required frequency, and the component parameters of LC parallel-tuned circuits are：
The π f of ω=2
Output voltage is：
When drive signal dutycycle is 25%, as N=3, i.e. DE-1The frequency multiplier of class 3, output signal voltage are direct currents Source voltage Vdd2.9 times, frequency is 3 times of drive signal, realizes 3 frequencys multiplication.Its load resistance RL, the first inductance L1, second Inductance L2, Shunt compensation capacitor C, parallel resonant electric capacity CpWith parallel resonant inductance LpCalculation formula (capacitance CDCOnly need foot It is enough big, it is not necessary to especially to calculate)；
Quality factor are QLCLC parallel resonant component parameters：
Wherein, the π f of ω=2.
Finally, DE class frequency multipliers are designed using result of calculation.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these are improved and deformation Also it should be regarded as protection scope of the present invention.

Claims (6)

1. a kind of DE classes frequency multiplier, it is characterised in that including direct voltage source Vdd, the first FET S1, the second FET S2, the first inductance L1, the second inductance L2, capacitance CDC, Shunt compensation capacitor C, LC parallel-tuned circuit and load resistance RL；
The capacitance CDCOne the first inductance L of termination1With the second inductance L2One end, capacitance CDCThe other end connect respectively LC parallel-tuned circuits, Shunt compensation capacitor C and load resistance RLOne end；The first inductance L1The other end concatenation first FET S1Drain electrode；The second inductance L2The other end concatenate the second FET S2Drain electrode；The LC parallel resonants Circuit, Shunt compensation capacitor C and load resistance RLAnother termination power；
The first FET S1With connecing power supply, grid connects the first driving voltage to source electrode；
The second FET S2Source electrode meets direct voltage source Vdd, grid connects the second driving voltage.
2. a kind of DE classes frequency multiplier according to claim 1, it is characterised in that the LC parallel-tuned circuits include tuning Electric capacity CpWith tuning coil Lp, wherein, tuning capacitance CpBoth ends connection tuning coil LpBoth ends, resonance is in frequency multiplication target frequency.
3. the design method of the DE class frequency multipliers described in claim 1 or 2, it is characterised in that comprise the following steps：
1) the drive signal dutycycle of DE classes frequency multiplier is 25%, as the first fet switch S1During disconnection, the first inductance L1In Electric current drop to 0, and electric current changes with time rate as 0 so that the first inductance L1Power attenuation be 0；When first effect Should pipe switch S2During disconnection, the second inductance L2In electric current drop to 0, and electric current changes with time rate as 0 so that the second electricity Feel L2Power attenuation be 0；According to this inductance zero-current switching and zero current derivative switch condition, the ginseng in N frequency multipliers is obtained Number relation：
Wherein,
It is multiple of the output voltage amplitude relative to direct current power source voltage,
It is the phase of output voltage,
For load resistance RLInverse,
B=N ω C are Shunt compensation capacitor C susceptance,
X=ω L1=ω L2It is series inductance L1And L2Induction reactance,
The π f of ω=2；
2) design parameter of DE class frequency multipliers, including direct voltage source V are givendd, power output Po, loaded quality factor QLC, drive Dynamic signal frequency f and frequency multiple N,
3) parameters relationship of step 1), the expression formula of load resistance and the design parameter of DE class frequency multipliers are combined, obtains N frequency multipliers Component parameters：Load resistance RL, the first inductance L1, the second inductance L2, Shunt compensation capacitor C, parallel resonant electric capacity CpAnd parallel connection Tuning coil Lp；
4) the result of calculation design DE class frequency multipliers of step 3) are utilized.
4. design method according to claim 3, it is characterised in that the N in the N frequency multipliers is odd number.
5. design method according to claim 3, it is characterised in that the load resistance RLMeet：
6. design method according to claim 3, it is characterised in that the parallel resonant electric capacity CpWith parallel resonant inductance LpCalculation formula it is as follows：
<mrow> <msub> <mi>C</mi> <mi>p</mi> </msub> <mo>=</mo> <mfrac> <msub> <mi>Q</mi> <mrow> <mi>L</mi> <mi>C</mi> </mrow> </msub> <mrow> <msub> <mi>N&amp;omega;R</mi> <mi>L</mi> </msub> </mrow> </mfrac> </mrow>
<mrow> <msub> <mi>L</mi> <mi>p</mi> </msub> <mo>=</mo> <mfrac> <mn>1</mn> <mrow> <msup> <mi>N</mi> <mn>2</mn> </msup> <msup> <mi>&amp;omega;</mi> <mn>2</mn> </msup> <msub> <mi>C</mi> <mi>p</mi> </msub> </mrow> </mfrac> <mo>.</mo> </mrow>
CN201710748598.6A 2017-08-28 2017-08-28 Design method of DE frequency multiplier Active CN107508556B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710748598.6A CN107508556B (en) 2017-08-28 2017-08-28 Design method of DE frequency multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710748598.6A CN107508556B (en) 2017-08-28 2017-08-28 Design method of DE frequency multiplier

Publications (2)

Publication Number Publication Date
CN107508556A true CN107508556A (en) 2017-12-22
CN107508556B CN107508556B (en) 2020-11-10

Family

ID=60693847

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710748598.6A Active CN107508556B (en) 2017-08-28 2017-08-28 Design method of DE frequency multiplier

Country Status (1)

Country Link
CN (1) CN107508556B (en)

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248945A (en) * 1990-08-28 1993-09-28 Simon Atkinson Power amplifiers
CN1087764A (en) * 1992-12-03 1994-06-08 艾利森电话股份有限公司 Radio-frequency generator and the oscillator formed by differential amplifier
CN1886888A (en) * 2003-12-19 2006-12-27 艾利森电话股份有限公司 Frequency multiplying arrangements and a method for frequency multiplication
CN101299593A (en) * 2008-06-24 2008-11-05 上海杰盛无线通讯设备有限公司 Three frequency multiplier based on BJT tube
CN102104362A (en) * 2011-03-01 2011-06-22 北京大学 Millimeter-wave frequency multiplier and cascaded frequency multipliers
CN202153722U (en) * 2011-08-16 2012-02-29 武汉凡谷电子技术股份有限公司 Frequency multiplication circuit
CN103312279A (en) * 2013-05-21 2013-09-18 河海大学 DE type power amplifier and design method thereof
CN203377843U (en) * 2013-07-31 2014-01-01 珠海市光辰科技有限公司 Higher frequency multiplier
CN203377864U (en) * 2013-07-24 2014-01-01 珠海市光辰科技有限公司 Direct digital frequency synthesizer
CN103731103A (en) * 2014-01-17 2014-04-16 东南大学 Fully-differential microwave millimeter wave frequency multiplier
CN104113307A (en) * 2014-07-07 2014-10-22 北京交通大学 All-optical clock frequency multiplication device and frequency multiplication method based on device
US8917805B2 (en) * 2012-11-20 2014-12-23 International Business Machines Corporation Bipolar transistor frequency doublers at millimeter-wave frequencies
CN104579316A (en) * 2015-01-30 2015-04-29 灿芯半导体(上海)有限公司 Programmable frequency divider with fifty-percent duty cycles
CN105322890A (en) * 2014-07-23 2016-02-10 精工爱普生株式会社 Frequency multiplication circuit, electronic device and moving object
US20170141763A1 (en) * 2015-11-18 2017-05-18 Electronics And Telecommunications Research Institute Frequency doubler having optimized harmonic suppression characteristics

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248945A (en) * 1990-08-28 1993-09-28 Simon Atkinson Power amplifiers
CN1087764A (en) * 1992-12-03 1994-06-08 艾利森电话股份有限公司 Radio-frequency generator and the oscillator formed by differential amplifier
CN1886888A (en) * 2003-12-19 2006-12-27 艾利森电话股份有限公司 Frequency multiplying arrangements and a method for frequency multiplication
CN101299593A (en) * 2008-06-24 2008-11-05 上海杰盛无线通讯设备有限公司 Three frequency multiplier based on BJT tube
CN102104362A (en) * 2011-03-01 2011-06-22 北京大学 Millimeter-wave frequency multiplier and cascaded frequency multipliers
CN202153722U (en) * 2011-08-16 2012-02-29 武汉凡谷电子技术股份有限公司 Frequency multiplication circuit
US8917805B2 (en) * 2012-11-20 2014-12-23 International Business Machines Corporation Bipolar transistor frequency doublers at millimeter-wave frequencies
CN103312279A (en) * 2013-05-21 2013-09-18 河海大学 DE type power amplifier and design method thereof
CN203377864U (en) * 2013-07-24 2014-01-01 珠海市光辰科技有限公司 Direct digital frequency synthesizer
CN203377843U (en) * 2013-07-31 2014-01-01 珠海市光辰科技有限公司 Higher frequency multiplier
CN103731103A (en) * 2014-01-17 2014-04-16 东南大学 Fully-differential microwave millimeter wave frequency multiplier
CN104113307A (en) * 2014-07-07 2014-10-22 北京交通大学 All-optical clock frequency multiplication device and frequency multiplication method based on device
CN105322890A (en) * 2014-07-23 2016-02-10 精工爱普生株式会社 Frequency multiplication circuit, electronic device and moving object
CN104579316A (en) * 2015-01-30 2015-04-29 灿芯半导体(上海)有限公司 Programmable frequency divider with fifty-percent duty cycles
US20170141763A1 (en) * 2015-11-18 2017-05-18 Electronics And Telecommunications Research Institute Frequency doubler having optimized harmonic suppression characteristics

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
刘平 等: "DE类高频调谐功率放大器", 《微计算机信息》 *
郑狄 等: "基于布里渊载波相移的宽带可调谐二倍频微波信号生成", 《物理学报》 *
陈钊 等: "北斗卫星通信在远程自动气象站中的应用", 《工业控制计算机》 *

Also Published As

Publication number Publication date
CN107508556B (en) 2020-11-10

Similar Documents

Publication Publication Date Title
DE10262286B4 (en) A power supply device for generating high frequency power for a plasma generating device
WO2006119362A2 (en) Methods and apparatus for resistance compression networks
US8744378B2 (en) LINC transmitter with improved efficiency
CN105932859A (en) Radio-frequency power supply for mass spectrometer
CN101350554A (en) Multipath insulation output power supply
CN105162319B (en) ZVT quasi-resonance high-gain DC booster converter
CN105071651A (en) Loop compensation method and circuit
CN103337964A (en) Ultrahigh frequency isolation push-pull resonant power converter
Jamal et al. A study on performances of different compensation topologies for loosely coupled inductive power transfer system
DE102019101566A1 (en) Device for controlling a DC-AC converter
CN103548258B (en) On-off circuit
Pakasiri et al. Modified class-F power amplifier design with fundamental frequency output impedance load
CN104467714B (en) A kind of operation amplifier circuit, operational amplifier and envelope following power supply
CN107508556A (en) A kind of DE classes frequency multiplier and design method
CN105871341B (en) The high linearity Doherty power amplifier realized using double negative ferroelectric materials
CN104518745B9 (en) Amplifier with a high-frequency amplifier
CN106655742A (en) Ultralow ripple wave circuit control method and device
CN103312279B (en) A kind of DE power-like amplifier and method for designing thereof
CN204706890U (en) Secondary ripple wave cancellation element in a kind of easy pfc circuit
CN102447410A (en) AC-DC (Alternating Current-Direct Current) power converter and loop compensating circuit thereof
CN101404478B (en) Method and apparatus for improving efficiency of class E power amplifier
DE102011012622A1 (en) Hochfrequenzleistungsvervielfacherlösung
CN102609028B (en) Phase compensation controller
CN206180830U (en) Pulse frequency regulation control circuit based on current mirror modulation
CN205319759U (en) Battery charging converter circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant