CN103730371B - Method for manufacturing super junction high-voltage device - Google Patents
Method for manufacturing super junction high-voltage device Download PDFInfo
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- CN103730371B CN103730371B CN201310734730.XA CN201310734730A CN103730371B CN 103730371 B CN103730371 B CN 103730371B CN 201310734730 A CN201310734730 A CN 201310734730A CN 103730371 B CN103730371 B CN 103730371B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 239000012535 impurity Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000011049 filling Methods 0.000 claims abstract description 16
- 239000002131 composite material Substances 0.000 claims abstract description 7
- 230000003139 buffering effect Effects 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 17
- 238000000407 epitaxy Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 description 21
- 230000001413 cellular effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 238000000518 rheometry Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The invention relates to a method for manufacturing a super junction high-voltage device. An existing device is weak in electrorheological capacity. The method for manufacturing the super junction high-voltage device includes the steps of preparing a silicon wafer with an N+ doped substrate; forming a first groove through an etching process; filling the first groove through a P-type epitaxial layer, and removing the P-type epitaxial layer outside the filled first groove to form P posts and N posts which are distributed at intervals; forming a second groove through the etching process; filling the second groove through a growth N-type epitaxial layer with impurity concentration; removing the redundant N-type epitaxial layer on the surface of the silicon wafer on a composite buffering layer to form new P posts and N posts which are distributed at intervals; manufacturing a feature layer of the device on the surface of a silicon wafer of a new composite buffering layer. According to the method, voltage resistance performance of the device and current capacity of the device can be improved, and reliability of the device can be improved.
Description
Technical field
The invention belongs to technical field of semiconductors, is related to a kind of manufacture method of super junction high-voltage device.
Background technology
At present the manufacture method of superjunction is roughly divided into two kinds:Epitaxy and ditch channel process（Ma Wanli, Zhao Shengzhe. hyperconjugation VDMOS
Several processing technology [J] of drift region. semiconductor technology, 2014 (9):689-693）.
Epitaxy：If Figure 10 and Figure 11 is the flow chart that existing epitaxy manufactures super junction, its concrete grammar is：
First in heavily doped N+ (P+) Grown ground floor N (P) type extension, inject in the precalculated position of the epitaxial layer
P (N) the type impurity of predetermined close so that the amount of N (P) the type impurity in the epitaxial layer is flux matched with P (N) type impurity, due to
The method in this layer of outer Yanzhong injection is needed to form P (N) post, so the thickness of every layer of extension can not be too thick, for one
The transistor of 600v, substantially needs which floor N (P) type extension as shown in Figure 10, and P (N) type is made after each extension
Ion implanting；As shown in figure 11, the shape up and down that P (N) type ion implanted layer is defined shown in figure after diffusion is more consistent
Air bubble-shaped is connected and concentration spreads uniform P (N) post；Thus, spaced P posts and N posts are defined, this is spaced
P posts are referred to as compound buffer layer with N posts.P (N) post in the superjunction of epitaxy manufacture is through repeatedly extension, oxidation, photoetching repeatedly
Formed with canopy ion implanting;In technical process, the canopy ion of previous injection can with rear extension Diffusion drift, need
Calibrate through many experiments.So this process needs precise control canopy ion implantation dosage, window and propulsion time to be formed
Up and down the more consistent air bubble-shaped of shape is connected and concentration spreads uniform column knot, to realize the charge compensation of super junction.And it is many
Secondary epitaxial growth, ion implanting and diffusion can produce substantial amounts of lattice defect, can also affect the reliability of device.
Ditch channel process is one of main flow manufacture method of current super-junction structure, and such as Figure 12 to Figure 13 is prior art groove legal system
Make the flow chart of super junction;Its concrete manufacturing process is：
As shown in figure 12, first in heavily doped N+（P+）One layer of N of Grown（P）Type extension, this sentences 650v crystal
40um is taken around as a example by pipe, in the presumptive area digging groove of the epitaxial layer of N (P) the type doping type, the depth of groove is about
For 40um;
Form the epitaxial layer with P (N) type doping type, this P (N) type extension respectively as shown in figure 13 and then in the trench
In the content of P (N) type impurity be set in advance according to charge balance requirements, the amount and P of N (P) the type impurity in epitaxial layer
(N) amount of type impurity is equal.
Thus, spaced P posts and N posts are defined, this spaced P post and N posts is referred to as into compound buffer layer.
Raising the pressure of device is wanted in the case of not changing outer layer doping concentration and is accomplished by deeper gash depth, it is thicker to be formed
Compound buffer layer, have thicker Withstand voltage layer, the pressure of device also can improve.Want to obtain deeper in traditional handicraft
Gash depth must just increase the width of groove, the i.e. width of P posts can broaden.The width of P posts is wider, the size meeting of single cellular
It is bigger, and the current capacity of single cellular can not be improved.If the area of superjunction devices chip is certain, the width of P posts broadens, and makes
The cellular number for obtaining device tails off, so that the electric rheology of device dies down.
There is a NPN triode for parasitism in a mosfet, as shown in figure 1, base stage is with the equivalent resistance of transmitting interpolar
Rbb, when power MOSFET is in inductive load loop, when MOSFET is turned off by opening to moment, the electricity that inductance will be stored
Amount is released to MOSFET, and base has electric current to flow through, the PN junction pressure drop Vbi=I*Rbb of base stage and transmitting interpolar.Work as Vbi>During 0.7v,
Parasitic triode will be turned on, and device can fail.Prevent one of method of such failure from being to reduce base resistance Rbb.Reduce Rbb
Can be realized by increasing the concentration of base n-type impurity, but this would generally be impacted to the electric property of device, can be caused
The cut-in voltage of device and conducting resistance increase, and solution is to increase one layer of p+ mask plate to carry out p+ injections, is reduced with this
Base resistance Rbb and other characteristics of device are not affected.For super node MOSFET, as shown in Fig. 2 the concentration of P posts is lower,
Parasitic triode in super node MOSFET is more easy to turn on, and principle is as follows：If the concentration of P posts is low, when power MOSFET is in perception
In load circuit, when MOSFET is turned off by opening to moment, the electricity of storage is released to MOSFET by inductance, and there is electricity base
Stream flows through, because the concentration of P posts is low, it is meant that the resistance of P posts is larger, so the electric current passed through from P posts is just few, from p+
The electric current for passing through just is increased, i.e. I in Vbi=I*Rbb becomes big, so Vbi can become big, works as Vbi>During 0.7v, parasitic three pole
Pipe will be turned on, and device can fail.
The content of the invention
It is an object of the invention to provide a kind of pressure and device current capacity that can improve device and device can be improved
Reliability super junction high-voltage device manufacture method.
To solve above-mentioned technical problem, the technical scheme is that：A kind of manufacture method of super junction high-voltage device, it is special
Part is not：Comprise the following steps：
Step one：Prepare the silicon chip with N+ doped substrates, the N extensions with n-type doping on the substrate；
Step 2：The region of first groove is defined by photoetching in the silicon chip surface of n-type doping substrate, and by etching
Technique forms first groove；The first groove width is X2, and depth is Y2, and meets 2X1>X2>X1,2Y1>Y2>Y1, its
In, X1 is the groove width that conventional groove manufacturing process is formed, and Y1 is its depth；
Step 3：On the surface of the silicon chip of n-type doping substrate, with the p-type epitaxial layer of p type impurity concentration first is filled
Groove, the impurity concentration that first groove is filled herein is p2, and is met：p2>P1, wherein p1 are that the impurity of tradition filling groove is dense
Degree；
Step 4：The p-type epitaxial layer filled on the surface of the silicon chip of n-type doping substrate outside first groove is got rid of,
Spaced P posts and N posts is formed, that is, forms compound buffer layer；
Step 5：The region of second groove is defined by photoetching in composite buffering layer surface, and by etching technics shape
Into second groove, herein the width of second groove is X3, and depth is Y2, meets relational expression：X2>X3>X1,2Y1>Y2>Y1, quilt
The part for etching away includes the N posts of the P posts of a part and a part, herein remaining P posts width, that is, the P post width not etched away
Spend for X4, meet relational expression X4<X1；
Step 6：The epitaxial layer of N-type impurity concentration is grown on the silicon chip surface with compound buffer layer filling second
Groove；The N-type extension impurity concentration filled herein is identical with the N-type epitaxy layer impurity concentration of the silicon chip of N+ doped substrates；
Step 7：N-type epitaxy layer unnecessary on the silicon chip surface of compound buffer layer is got rid of, forms new spaced
P posts and N posts, that is, form new compound buffer layer；
Step 8：The characteristic layer of device is manufactured in the silicon chip surface of new compound buffer layer.
Compared with prior art, the invention has the advantages that：
Because the width X4 of the P posts in the present invention is less than the width X1 of tradition P posts, so doping content p2 of P posts is more than
Doping content p1 of traditional P posts, so that in inductive load loop, the parasitism of device when being turned off by opening to moment
The more difficult conducting of audion, thus improves the reliability of device；
Due to the P posts in the present invention width X4 less than tradition P posts width X1, so in the present invention single cellular chi
Very little meeting is less than the size of traditional single cellular, and the current capacity of single cellular can't reduce, so in superjunction devices chip
The cellular number of device can become many in the present invention in the case that area is certain, so that the current capacity of device becomes strong；
The present invention can realize depth Y2 of groove more than tradition in the case where the doping content of N-type epitaxy layer is not changed
Depth Y1 of groove, i.e., P posts depth of the present invention is more than tradition P post depth, such that it is able to improve the breakdown voltage of device.
Description of the drawings
Fig. 1 is traditional MOSFET parasitic triode diagram explanations；
Fig. 2 is super node MOSFET parasitic triode diagram explanation；
Fig. 3 is the schematic diagram of the step one of the present invention；
Fig. 4 is the schematic diagram of the step two of the present invention；
Fig. 5 is the schematic diagram of the step three of the present invention；
Fig. 6 is the schematic diagram of the step four of the present invention；
Fig. 7 is the schematic diagram of the step five of the present invention；
Fig. 8 is the schematic diagram of the step six of the present invention；
Fig. 9 is the schematic diagram of the step eight of the present invention；
Figure 10-Figure 11 is the schematic diagram that conventional epitaxial legal system makes super-junction structure；
Figure 12-Figure 13 is the schematic diagram that conventional groove legal system makes super-junction structure.
Wherein：1.N extensions；2.N substrates；3. first surface；4. first groove；5. second groove；6.P type epitaxial layers, 7.P
Post, 8.N posts, 9. grid polycrystalline silicon；10. grid oxic horizon；11. metal levels.
Specific embodiment
With reference to specific embodiment, the present invention will be described in detail.
A kind of manufacture method of super junction high-voltage device, comprises the following steps：
Step one：Prepare the silicon chip with N+ doped substrates, the N extensions 1 with n-type doping on the substrate, such as Fig. 3 institutes
Show；
Step 2：The region of first groove 4 is defined by photoetching in the silicon chip surface of n-type doping substrate, and by carving
Etching technique forms first groove 4；The width of first groove 4 is X2, and depth is Y2, and meets 2X1>X2>X1,2Y1>Y2>Y1, its
In, X1 is the groove width that conventional groove manufacturing process is formed, and Y1 is its depth, because technological level is limited, it is desirable to obtain more
Deep gash depth must just increase the width of groove, so wanting to realize deeper gash depth i.e. Y2 in the present invention>Y1,
The width that groove must just be caused deepens i.e. X2>X1, as shown in Figure 4；
Step 3：On the surface of the silicon chip of n-type doping substrate, the epitaxial layer with p type impurity concentration is p-type epitaxial layer 6
To fill first groove 4, the impurity concentration that first groove 4 is filled herein is p2, and is met：p2>P1, wherein p1 are tradition filling
The impurity concentration of groove, as shown in Figure 5；
Step 4：The p-type epitaxial layer 6 filled on the surface of the silicon chip of n-type doping substrate outside first groove 4 is removed
Fall, form spaced P posts and N posts, that is, form compound buffer layer, as shown in Figure 6；
Step 5：The region of second groove 5 is defined by photoetching in composite buffering layer surface, and by etching technics point
Other etch away sections P posts and part N posts form second groove 5, and herein the width of second groove 5 is X3, and depth is Y2, meets and closes
It is formula：X2>X3>X1,2Y1>Y2>Y1, remaining P posts width herein, that is, the P posts width not being etched away is X4, meets relation
Formula X 4<X1, i.e., herein the width of P posts is less than the width of tradition P posts, as shown in Figure 7；
Step 6：Grow the epitaxial layer of predetermined N-type impurity concentration on the silicon chip surface with compound buffer layer to fill
Second groove 5；The N-type extension impurity concentration filled herein as the N-type extension impurity concentration of the silicon chip of N+ doped substrates, such as
Shown in Fig. 8；
Step 7：N-type epitaxy layer unnecessary on the silicon chip surface of compound buffer layer is got rid of, forms new spaced
P posts and N posts, that is, form new compound buffer layer；
Step 8：The characteristic layer of device is manufactured in the silicon chip surface of new compound buffer layer, as shown in Figure 9.
Below the present invention is specifically described by taking mosfet as an example.
The characteristic layer of Mosfet includes：Gate oxide（gate oxide）10th, gate electrode（poly）, drain electrode（drain）、
Bpsg layers, source electrode（source）, comprise the following steps that：
Step one：Prepare the silicon chip with N+ doped substrates, the extension with n-type doping on the substrate, such as Fig. 3 institutes
Show；
Step 2：The region of first groove 4 is defined by photoetching in the silicon chip surface of n-type doping substrate, and by carving
Etching technique forms first groove 4；The width of the first groove 4 is X2, and depth is Y2, and meets 2X1>X2>X1,2Y1>Y2>Y1,
Wherein, X1 is the groove width that conventional groove manufacturing process is formed, and Y1 is its depth, because the restriction of technological level is wanted to dig
Deeper groove increases just must the width of groove, so working as X2>Y2 can just be accomplished during X1>Y1, as shown in Figure 4；
Step 3：On the surface of the silicon chip of n-type doping substrate, the epitaxial layer with p type impurity concentration is p-type epitaxial layer 6
To fill first groove 4, the impurity concentration that first groove is filled herein is p2, and is met：p2>P1, wherein p1 are tradition filling
The impurity concentration of groove, as shown in Figure 5；
Step 4：The p-type extension filled on the surface of the silicon chip of n-type doping substrate outside first groove 4 is got rid of, shape
Into spaced P posts and N posts, that is, compound buffer layer is formed, as shown in Figure 6；
Step 5：The region of second groove 5 is defined by photoetching in the first composite buffering layer surface, and by etching work
Respectively etch away sections fall P posts to skill and part N posts form second groove 5, and herein the width of second groove 5 is X3, and depth is Y2,
Meet relational expression：X2>X3>X1,2Y1>Y2>Y1, remaining P posts width herein, that is, the P posts width not being etched away is X4, full
Sufficient relational expression X4<X1, as shown in Figure 7；
Step 6：Grow the epitaxial layer of predetermined N-type impurity concentration on the silicon chip surface with compound buffer layer to fill
Second groove 5；The N-type extension impurity concentration filled herein as the N-type extension impurity concentration of the silicon chip of N+ doped substrates, such as
Shown in Fig. 8；
Step 7：N-type extension unnecessary on the silicon chip surface of compound buffer layer is got rid of, forms new spaced
P posts and N posts, that is, form new compound buffer layer；
Step 8：As shown in figure 9, the characteristic layer of the silicon chip surface manufacture device in new compound buffer layer, specifically includes：
1) in the autochthonal long oxide layer of semi-conductor silicon chip;
2) by photoetching, boundary walks out active area, and field oxide is performed etching;
3) gate oxide is grown, in gate oxide surface deposition conductive grid polysilicon 9;
4) by photoetching, boundary walks out the region of grid polycrystalline silicon 9, carries out grid polycrystalline silicon 9 and etches；
5) p type impurity ion implanting is carried out with whole semi-conductor silicon chip surface, field oxide and grid that previous process is formed
The region of pole polysilicon 9 can define the region of the p-well to be formed, and high temperature returns the p-well that fire forms array;
6) source region, N-type impurity ion implanting are walked out by photoetching circle, and carries out pushing away trap formation N+ type source regions;
7) with whole semi-conductor silicon chip surface deposition dielectric layer;
8) by photoetching, boundary walks out contact bore region, and carries out oxide layer etching;
9) deposited metal, by photoetching, defines etch areas, carries out metal etch.
The device manufactured by above-mentioned steps is contained：The substrate layer of one the first conductivity type material, it can be N-type half
Conductor can also be P-type semiconductor, but is illustrated with N-type semiconductor in the present invention, and we are called N+ substrates.
In the epitaxial layer of the conductivity type material of N+ Growns first, it can also be p-type half that it can be N-type semiconductor
Conductor, but be illustrated with N-type semiconductor in the present invention, we are called N epitaxial layers.
There are many cellulars on N epitaxial layers, each cellular has a device feature layer containing device feature region,
Device feature layer plays second conductivity type material, and it can play N-type semiconductor, it is also possible to plays p-type and partly leads
The effect of body, but be illustrated with P-type semiconductor in the present invention, we are referred to as p-well.
There are a compound buffer layer (Composite Buffer Layer), abbreviation CB between p-well and N epitaxial layers
Layer.
The first semiconductor region constituted containing the first conductivity type material in CB layers, the material of this first conduction type
It can also be P-type semiconductor that material can be N-type semiconductor, but be illustrated with N-type conductive material in the present invention.
Also containing the second semiconductor region of second conductivity type material composition in CB layers, this second conduction type
It can also be N-type semiconductor that material can be P-type semiconductor, but be illustrated with P-type conduction material in the present invention.
The first semiconductor region and second semiconductor region in CB layers is alternately arranged, and in the present invention we will
The first semiconductor region in CB layers is referred to as N posts, and second semiconductor region in CB layers is become P posts by us.If with MOSFET
As a example by, as shown in Figure 10, in addition to comprising P posts, N posts and p traps, also need to be formed on the surface of active area silicon chip：Source region n+, grid
Pole oxide layer（gate oxide）, gate electrode（poly）, drain electrode（drain）, bpsg layers, source electrode（source）.
Traditional trench region（P post region domain）Photoetching, etching and filling be by a photoetching, etching and filling complete
, above-mentioned trench region（P post region domain）Photoetching, etching and fill by Twi-lithography, etching and filling complete.
Complete above by Twi-lithography, etching and filling, trench region（P post region domain）Than the ditch of traditional method manufacture
Groove depth depth, it is assumed that the gash depth of conventional groove manufacture is Y1, the gash depth that this is formed is Y2, then Y2>Y1,
Complete above by Twi-lithography, etching and filling, trench region（P post region domain）Than filling out for traditional method manufacture
The impurity concentration for filling groove is high, it is assumed that the impurity concentration of tradition filling groove is p1, and the impurity concentration that groove is filled herein is p2,
Then meet：p2>p1.
The depth that the groove of said method formation is total is more than the gash depth that traditional method is formed.So not changing N-type
Deep trench high withstand voltage can be realized in the case of the doping content of epitaxial layer.
The doping content in the P post region domain that said method is formed can make power more than the doping content in traditional P post region domain
MOSFET in inductive load loop, the parasitic triode of device more difficult conducting when being turned off by opening to moment, by
This improves the reliability of device.
Said method formed P posts width X4 less than tradition P posts width X1, so in the present invention single cellular chi
Very little meeting is less than the size of traditional single cellular, and the current capacity of single cellular can't reduce, so in superjunction devices chip
The cellular number of device can become many in the present invention in the case that area is certain, so that the current capacity of device becomes strong.
Claims (1)
1. a kind of manufacture method of super junction high-voltage device, it is characterised in that：Comprise the following steps：
Step one：Prepare the silicon chip with N+ doped substrates, the N extensions with n-type doping on the substrate（1）；
Step 2：First groove is defined by photoetching in the silicon chip surface of n-type doping substrate（4）Region, and by etching
Technique forms first groove（4）；The first groove（4）Width is X2, and depth is Y2, and meets 2X1>X2>X1,2Y1>Y2>
Y1, wherein, X1 is the groove width that conventional groove manufacturing process is formed, and Y1 is its depth；
Step 3：On the surface of the silicon chip of n-type doping substrate, with the p-type epitaxial layer of p type impurity concentration（6）To fill first
Groove（4）, first groove is filled herein（4）Impurity concentration be p2, and meet：p2>P1, wherein p1 are tradition filling groove
Impurity concentration；
Step 4：First groove will be filled on the surface of the silicon chip of n-type doping substrate（4）Outside p-type epitaxial layer（6）Remove
Fall, form spaced P posts and N posts, that is, form compound buffer layer；
Step 5：Second groove is defined by photoetching in composite buffering layer surface（5）Region, and formed by etching technics
Second groove（5）, second groove herein（5）Width be X3, depth is Y2, meets relational expression：X2>X3>X1,2Y1>Y2>Y1,
The part being etched away includes a part of P posts and a part of N posts, and remaining P posts width is X4, and depth is Y2, meets relational expression：
X4<X1；
Step 6：The epitaxial layer of N-type impurity concentration is grown on the silicon chip surface with compound buffer layer filling second groove
（5）；The N-type extension impurity concentration filled herein is identical with the N-type epitaxy layer impurity concentration of the silicon chip of N+ doped substrates；
Step 7：N-type epitaxy layer unnecessary on the silicon chip surface of compound buffer layer is got rid of, spaced P posts and N is formed
Post, that is, form new compound buffer layer；
Step 8：The characteristic layer of device is manufactured in the silicon chip surface of new compound buffer layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310734730.XA CN103730371B (en) | 2013-12-27 | 2013-12-27 | Method for manufacturing super junction high-voltage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310734730.XA CN103730371B (en) | 2013-12-27 | 2013-12-27 | Method for manufacturing super junction high-voltage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103730371A CN103730371A (en) | 2014-04-16 |
| CN103730371B true CN103730371B (en) | 2017-04-19 |
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