CN103714027A - Data transmission method and device for direct memory access controller - Google Patents
Data transmission method and device for direct memory access controller Download PDFInfo
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- CN103714027A CN103714027A CN201410012698.9A CN201410012698A CN103714027A CN 103714027 A CN103714027 A CN 103714027A CN 201410012698 A CN201410012698 A CN 201410012698A CN 103714027 A CN103714027 A CN 103714027A
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Abstract
Provided is a data transmission method and device for a direct memory access controller. When multiple system-to-equipment DMA engines send reading request commands to a system through an arbitration mechanism, the system sends first messages or reading operation commands to be sent to equipment to a receiving massage distribution module, and the receiving massage distribution module analyzes the request identifiers of the first messages or the request identifiers of the reading operation commands, and sends the first messages or the reading operation commands to the corresponding system-to-equipment DMA engines according to the request identifiers; multiple equipment-to-system DMA engines send writing request commands to the system through the arbitration mechanism, the system sends writing operation commands to the receiving massage distribution module, and then transmits the writing operation commands to the equipment-to-system DMA engines, and then the equipment-to-system DMA engines send second messages to the system through the arbitration mechanism. Multiple sets of parallel DMA engines are adopted to work simultaneously, the efficiency of DMA equipment for receiving and sending data can be improved remarkably, and system performance can be improved.
Description
Technical field
The present invention relates to Computer System Design field and integrated circuit (IC) design field, be specifically related to a kind of data transmission method and device of direct memory access controller.
Background technology
Along with the develop rapidly of computer technology and integrated circuit technique, high performance computer system more and more becomes the needs of socio-economic development.The data transfer bandwidth of computer system reaches tens of GB/s, and data processing and the analysis ability of simultaneous computer system attachment equipment are also more and more higher, and this just brings challenges for the transmittability of data.On the one hand need to raising system to the transmitted data amount of equipment, improve as much as possible the utilization factor of system data transmission bandwidth, need on the other hand to avoid data transmission as much as possible and the CPU computational resource that consumes.This just need to adopt advanced DMA(Direct Memory Access, direct memory access (DMA)) transmission technology, DMA(Direct Memory Access, direct memory access (DMA)) refer to a kind of data transfer operation of high speed, allow externally direct read/write data between equipment and storer.
DMA transmission technology both can effectively improve data transmission efficiency, can avoid the consumption to CPU computational resource again.
But single DMA engine transfer efficiency is low, and the transmission bandwidth utilization factor of data handling system is not high, has affected system performance.
Summary of the invention
The technical problem to be solved in the present invention is to overcome the low deficiency of single DMA engine transfer efficiency, adopts multi-set parallel DMA engine to work simultaneously, can significantly improve the efficiency that dma device received and sent data, elevator system performance.
A data transmission method for direct memory access dma controller, is applied to the dma controller that comprises a plurality of DMA engines, and described DMA engine comprises that system arrives equipment DMA engine and equipment to system DMA engine, and described method comprises:
When a plurality of described systems send request read command by arbitration mechanism to system to equipment DMA engine, system sends to reception message distribution module to the first message of equipment or read operation order by be sent, described reception message distribution module is resolved the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order is distributed to corresponding system to equipment DMA engine; Described system is transmitted to relevant device after equipment DMA engine obtains described the first message;
When a plurality of described equipment is worked to system DMA engine simultaneously, equipment sends to each equipment to system DMA engine by the second message of system of giving to be sent, a plurality of equipment sends request write order by arbitration mechanism to system to system DMA engine, system is received after described request write order, write operation order is sent to and receives message distribution module, described reception message distribution module is resolved the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine; Equipment is received after described write operation order to system DMA engine, by arbitration mechanism, sends described the second message to system.
Alternatively, describedly by arbitration mechanism, send the second message and comprise to the step of system:
The second message that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described the second message through arbitration is carried out again to prioritization arbitration;
The described step that sends request write order to system by arbitration mechanism comprises:
The request write order that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described request write order through arbitration is carried out again to prioritization arbitration;
The described step that sends request read command by arbitration mechanism comprises:
Prioritization arbitration is carried out in the request read command that system described in each is sent to equipment DMA engine, to carry out again prioritization arbitration through the described order of arbitration.
Alternatively, also comprise: according to internal interrupt and/or external interrupt, generate interrupt request, interrupt request is carried out to priority arbitration, after arbitration, generate and interrupt message, send to arbitration mechanism again to carry out prioritization arbitration together with described the second message described interruption message, after arbitration, described interruption message is sent to system.
Alternatively, obtain the step of described the first message to equipment DMA engine in described system before, also comprise: described system is initiated descriptor information to equipment DMA engine, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system is obtained the step of described the first message described in carrying out from system according to described descriptor information to equipment DMA engine.
Alternatively, before sending the step of described the second message to system, also comprise: described equipment is initiated descriptor information to system DMA engine, described descriptor information is write to the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, described equipment sends described the second message data message to the step of system to system DMA according to described descriptor information.
A data transmission device for direct memory access controller, comprising: receive message distribution module, arbitration modules, a plurality of DMA engine modules;
Described a plurality of DMA engine modules comprises that a plurality of systems are to equipment DMA engine modules, a plurality of equipment to system DMA engine modules;
Described system is used for to system, sending request read command by arbitration modules to equipment DMA engine modules; The first message or read operation order that receiving system sends over by receiving message distribution module; When the system of obtaining the first message to equipment to be sent, be transmitted to relevant device;
Described reception message distribution module is for receiving the first message or the read operation order to equipment to be sent from system, resolve the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order are distributed to corresponding system to equipment DMA engine modules;
Described reception message distribution module also sends to equipment to the write operation order of system DMA engine modules for receiving system, resolve the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine modules;
Described equipment is used for to system, sending request write order by arbitration modules to system DMA engine modules; Described equipment also for receiving after described write operation order, sends described second message to system by arbitration modules to system DMA engine modules.
Described arbitration modules is carried out priority arbitration for the request read command that system is sent to system to equipment DMA engine modules; Described arbitration modules is also carried out priority arbitration for request write order or the second message that equipment is sent to system to system DMA engine modules.
Alternatively, described arbitration modules comprises one instance arbitration module, secondary arbitration modules;
Described one instance arbitration module is carried out prioritization arbitration for the second message or the request write order that equipment described in each is sent to system DMA engine modules;
Described secondary arbitration modules is carried out again prioritization arbitration for described the second message to through one instance arbitration or described request write order;
Described one instance arbitration module is carried out prioritization arbitration for the request read command that system described in each is sent to equipment DMA engine modules,
Described secondary arbitration modules is for carrying out again prioritization arbitration to sending request read command described in process one instance arbitration;
Described secondary arbitration modules is also for carrying out again prioritization arbitration to described interruption message.
Alternatively, also comprise interrupt arbitrage module, interrupt generation module; Described interruption generation module generates interrupt request according to internal interrupt and/or external interrupt, and the interrupt request that described interrupt arbitrage module generates described interruption generation module is carried out prioritization arbitration, and after prioritization arbitration, generate and interrupt message,
Described interrupt arbitrage module is sent to secondary arbitration modules by described interruption message and participates in prioritization arbitration together with described the second message, and described interruption message is sent to system after the arbitration of secondary arbitration modules prioritization.
Alternatively, also comprise the first descriptor register, system to equipment DMA engine modules also for before obtaining the step of described the first message, described system is initiated descriptor information to equipment DMA engine modules, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system to equipment DMA engine modules according to described descriptor information from the first message described in system acquisition.
Alternatively, also comprise the second descriptor register, described equipment to system DMA engine modules also for by arbitration modules, send described the second message to system before, initiate descriptor information, described descriptor information is write to described the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, carry out the described operation that described the second message is sent to system.
The present invention, at the many groups of chip internal dma module design DMA engine, makes its concurrent working.While receiving the first message from system, by receiving message distribution module, be responsible for resolving the request identifier ID that receives message, and complete to the distribution of each DMA engine, while sending the second message to system, by the one instance arbitration of each DMA engine internal, control inner transmission message collisions, by secondary arbitration modules, control the conflict that a plurality of DMA engines send message.Same, interrupt request is produced by each DMA engine internal, and then arbitrates control by interrupt arbitrage module, and generates interruption message, sends to arbitration modules to arbitrate control.The multistage arbitration control of transmission message and the interrupt arbitrage of many group DMA engines are controlled the collision problem of effectively having avoided magnanimity message transmissions, therefore in high bandwidth transfer systems, or in large data handling system, there is vast potential for future development, there is very high technological value.
Accompanying drawing explanation
Fig. 1 is the operational flowchart of system while receiving data manipulation to equipment DMA engine modules;
Fig. 2 is the operational flowchart of equipment while sending data manipulation to system DMA engine modules;
Fig. 3 is the installation drawing that a plurality of parallel DMA engine modules are worked simultaneously.
Embodiment
Below in conjunction with drawings and Examples, technical scheme of the present invention is described in detail.
It should be noted that, if do not conflicted, each feature in the embodiment of the present invention and embodiment can mutually combine, all within protection scope of the present invention.In addition, although there is shown logical order in flow process, in some cases, can carry out shown or described step with the order being different from herein.
Before setting forth embodiment, first set forth several implications.
The first message refers to the message that sends to device orientation from system;
The second message refers to the message that sends to system orientation from equipment.
DMA engine modules comprises that system arrives equipment DMA engine modules and equipment to system DMA engine modules, and DMA engine modules receives data and refers to and from system to device orientation, transmits data, and DMA engine modules sends data and refers to and from equipment to system orientation, transmits data.
Embodiment mono-
Operating process while receiving data manipulation in conjunction with Fig. 1 and Fig. 3 elaboration system to equipment DMA engine modules.
A data transmission method for direct memory access dma controller, is applied to the dma controller that comprises a plurality of DMA engines, and described DMA engine comprises that system arrives equipment DMA engine and equipment to system DMA engine, and described method comprises:
When a plurality of described systems send request read command by arbitration mechanism to system to equipment DMA engine, system sends to reception message distribution module to the first message of equipment or read operation order by be sent, described reception message distribution module is resolved the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order is distributed to corresponding system to equipment DMA engine; Described system is transmitted to relevant device after equipment DMA engine obtains described the first message;
The described step that sends request read command by arbitration mechanism comprises:
Prioritization arbitration is carried out in the request read command that system described in each is sent to equipment DMA engine, to carry out again prioritization arbitration through the described order of arbitration.
As can be seen from Figure 3 a plurality of systems are worked to equipment DMA engine simultaneously.
First by system, to equipment DMA engine, initiate request read command, for fear of same system to equipment, send a plurality of request read commands conflict of competing simultaneously, and set up arbitration mechanism, after one instance arbitration, the request read command that priority is high can preferentially be passed through, the request read command that priority the is low transmission that can lag behind.
Secondary arbitration is carried out in the request read command that priority is high after one instance arbitration again, after secondary arbitration, enters into system.Setting up of secondary arbitration is mainly that the request read command of sending to system to equipment DMA engine for fear of different systems still has and sends simultaneously and compete conflict after one instance arbitration.
Obtain the step of described the first message to equipment DMA engine in described system before, also comprise: described system is initiated descriptor information to equipment DMA engine, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system is obtained the step of described the first message described in carrying out from system according to described descriptor information to equipment DMA engine.
System receives after request read command, and system sends the first message and with the read operation response command of data, with the read operation order of descriptor information.First read operation order and the first message with descriptor information arrive message distribution module, read operation order or the first message and system have relation one to one to equipment DMA engine modules, by request identifier, ID distinguishes, described reception message distribution module is resolved the request identifier ID of described read operation order or the first message, read operation order with descriptor information and the first message are distributed to receiving end, receiving end is connected to equipment DMA engine modules with system
In system, to equipment DMA engine modules inside, also has descriptor register, the first message or the register interface by receiving end enters into system to the descriptor register of equipment DMA engine modules inside with the read operation order of descriptor information, system is initiated descriptor information to equipment DMA engine modules, described descriptor information is write to the first descriptor register, when described the first descriptor register is received the read operation order with descriptor information that system returns, the first descriptor register sends to system to equipment DMA engine modules by transmission the first message.
The first descriptor register also can arrive in system the outside of equipment DMA engine modules.
The first message is sent to system after equipment DMA engine modules, by system, to equipment DMA, is transmitted to equipment.
Owing to having had arbitration mechanism and message distribution mechanism, a plurality of systems can be initiated read operation request to equipment DMA engine simultaneously, therefore can greatly improve the efficiency of system data transmission.
Embodiment bis-
Operating process while sending data manipulation in conjunction with Fig. 2 and Fig. 3 illustrated devices to system DMA engine modules.
A data transmission method for direct memory access dma controller, is applied to the dma controller that comprises a plurality of DMA engines, and described DMA engine comprises that system arrives equipment DMA engine and equipment to system DMA engine, and described method comprises:
When a plurality of described equipment is worked to system DMA engine simultaneously, equipment sends to each equipment to system DMA engine by the second message of system of giving to be sent, a plurality of equipment sends request write order by arbitration mechanism to system to system DMA engine, system is received after described request write order, write operation order is sent to and receives message distribution module, described reception message distribution module is resolved the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine; Equipment is received after described write operation order to system DMA engine, by arbitration mechanism, sends described the second message to system.
Alternatively, describedly by arbitration mechanism, send the second message and comprise to the step of system:
The second message that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described the second message through arbitration is carried out again to prioritization arbitration;
The described step that sends request write order to system by arbitration mechanism comprises:
The request write order that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described request write order through arbitration is carried out again to prioritization arbitration.
First, when equipment carries out sending data manipulation to system orientation to system DMA engine, first by equipment, to system DMA, initiate write operation requests, equipment sends request write order to system DMA to one instance arbitration module.
One instance arbitration is carried out priority arbitration to request write order, and what priority was high can preferentially send, and the hysteresis that priority is low sends.
The request write order that priority is high carries out secondary arbitration after one instance arbitration again, carries out priority arbitration again, after secondary arbitration, enters into system.
Setting up of secondary arbitration is mainly that the request write order that sends to system to system DMA for fear of different equipment still has and sends simultaneously and compete conflict after one instance arbitration.
Alternatively, also comprise: according to internal interrupt and/or external interrupt, generate interrupt request, interrupt request is carried out to priority arbitration, after arbitration, generate and interrupt message, send to arbitration mechanism again to carry out prioritization arbitration together with described the second message described interruption message, after arbitration, described interruption message is sent to system.
Internal interrupt refers to the interruption that system produces to system DMA engine, one instance arbitration mechanism, system to equipment DMA engine, equipment, when having produced a plurality of interrupt request, a plurality of interrupt request have just produced competition and have sent conflict, now just need to carry out priority arbitration to interrupt request, what priority was high can preferentially be sent to system, the transmission that can lag behind that priority is low.
By interrupt priority level, arbitrate the arbitration that can realize interrupt priority level, also can and generate and interrupt message, the interrupt request that priority is high generates interrupts message, described interruption message sends to that secondary arbitration mechanism and equipment are to be sent participates in priority arbitration together with the second message of system, after secondary arbitration, sends to system.
Alternatively, before sending the step of described the second message to system, also comprise: described equipment is initiated descriptor information to system DMA engine, described descriptor information is write to the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, described equipment sends described the second message data message to the step of system to system DMA according to described descriptor information.
System receives that after request write order, system sends the write operation response command with data, with the write operation order of descriptor information.First write operation order with descriptor information arrives message distribution module, write operation order and equipment have relation one to one to system DMA engine modules, by request identifier, ID distinguishes, described reception message distribution module is resolved the request identifier ID of described read operation order, described write operation order is distributed to receiving end, receiving end is connected to system DMA engine modules with equipment
The second descriptor register can arrive system DMA engine outside at equipment in system DMA engine or at equipment;
Register interface with the write operation order of descriptor information by receiving end enters into equipment to the second descriptor register of system DMA engine modules inside, equipment is initiated descriptor information to system DMA engine modules, described descriptor information is write to descriptor register, and equipment is sent to system according to descriptor information by the second message to system DMA engine.
The second descriptor register also can be outside to system DMA engine modules at equipment.
Owing to having had arbitration mechanism and message distribution mechanism, a plurality of equipment can be initiated write operation requests to system DMA engine simultaneously, therefore can greatly improve the efficiency of system data transmission.
When only having a DMA engine job, the priority of its internal interrupt and external interrupt is controlled at interruption generation module and completes.
In conjunction with Fig. 3, set forth the embodiment of device claim.
A data transmission device for direct memory access controller, comprising: receive message distribution module, arbitration modules, a plurality of DMA engine modules;
Described a plurality of DMA engine modules comprises that a plurality of systems are to equipment DMA engine modules, a plurality of equipment to system DMA engine modules;
Described system is used for to system, sending request read command by arbitration modules to equipment DMA engine modules; The first message or read operation order that receiving system sends over by receiving message distribution module; When the system of obtaining the first message to equipment to be sent, be transmitted to relevant device;
Described reception message distribution module is for receiving the first message or the read operation order to equipment to be sent from system, resolve the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order are distributed to corresponding system to equipment DMA engine modules;
Described reception message distribution module also sends to equipment to the write operation order of system DMA engine modules for receiving system, resolve the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine modules;
Described equipment is used for to system, sending request write order by arbitration modules to system DMA engine modules; Described equipment also for receiving after described write operation order, sends described second message to system by arbitration modules to system DMA engine modules.
Described arbitration modules is carried out priority arbitration for the request read command that system is sent to system to equipment DMA engine modules; Described arbitration modules is also carried out priority arbitration for request write order or the second message that equipment is sent to system to system DMA engine modules.
Alternatively, described arbitration modules comprises one instance arbitration module, secondary arbitration modules;
Described one instance arbitration module is carried out prioritization arbitration for the second message or the request write order that equipment described in each is sent to system DMA engine modules;
Described secondary arbitration modules is carried out again prioritization arbitration for described the second message to through one instance arbitration or described request write order;
For example, an equipment receives to system DMA engine modules the second message A and the second message B that equipment is sent simultaneously, both messages have generated competition conflict, one instance arbitration module is carried out priority arbitration to described the second message A and B, if the priority of A is higher than the priority of B, the message A that priority is high preferentially sends to secondary arbitration modules.When having received message A, secondary arbitration modules received again the message C that another equipment is sent to system DMA engine modules, now need message A and C to carry out prioritization arbitration, if the priority of A is higher than the priority of C, message A is preferentially sent in system by the second arbitration modules.
Described one instance arbitration module is carried out prioritization arbitration for the request read command that system described in each is sent to equipment DMA engine modules,
Described secondary arbitration modules is for carrying out again prioritization arbitration to sending request read command described in process one instance arbitration;
Described secondary arbitration modules is also for carrying out again prioritization arbitration to described interruption message;
Alternatively, also comprise interrupt arbitrage module, interrupt generation module; Described interruption generation module generates interrupt request according to internal interrupt and/or external interrupt, the interrupt request that described interrupt arbitrage module generates described interruption generation module is carried out prioritization arbitration, after prioritization arbitration, generate and interrupt message, described interrupt arbitrage module is sent to secondary arbitration modules by described interruption message and participates in prioritization arbitration together with described the second message, and described interruption message is sent to system after the arbitration of secondary arbitration modules prioritization.
System, to equipment DMA engine modules, equipment to system engine modules, one instance arbitration module, system, can occur to interrupt or interrupt request.
The interrupt request of system is by receiving message distribution module, receiving end, being transferred to interrupt register, and interrupt register sends to interruption generation module by the interrupt request of system.
Interrupt generation module and also can receive outside interrupt request and production interrupt request message.
When producing a plurality of interrupt request message simultaneously, just need to carry out prioritization arbitration to interrupt request message, interrupt arbitrage module is carried out prioritization arbitration to interrupt request, and the interrupt request that priority is high has been generated interruption message,
For example, external interrupt request A, system has an interrupt request B to equipment dma module, external interrupt request A and system have been generated to the interrupt request B of equipment DMA engine modules interrupting generation module simultaneously, because A and B occur simultaneously, need interrupt arbitrage module to carry out prioritization, if A is preferential, interrupt arbitrage module first generates the interrupt request message of A, interrupt request message A is sent to the second arbitration modules, the second message that sends to system orientation with equipment carries out prioritization arbitration, if the priority of interrupt request message A is greater than the priority of the second message C, interrupt request message A preferentially sends in system and goes.
Alternatively, also comprise the first descriptor register, system to equipment DMA engine modules also for before obtaining the step of described the first message, described system is initiated descriptor information to equipment DMA engine modules, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system to equipment DMA engine modules according to described descriptor information from the first message described in system acquisition.
The first descriptor register can be in system to also can be in system outside equipment DMA engine modules in equipment DMA engine modules.
Alternatively, also comprise the second descriptor register, described equipment to system DMA engine modules also for by arbitration modules, send described the second message to system before, initiate descriptor information, described descriptor information is write to described the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, carry out the described operation that described the second message is sent to system.
The second descriptor register can be at equipment to also can be at equipment outside system DMA engine modules in system DMA engine modules.
The present invention takes into full account the feature of computer system data transmission bandwidth and accessory device Data Management Analysis ability, adopt the DMA engine technique of multi-set parallel, coordinate corresponding multistage arbitration control technology, system is realized respectively to multi-set parallel work to equipment and equipment to the DMA engine of system both direction, with this, improve the transmission bandwidth utilization factor of data handling system, thereby reach the object of elevator system performance.
One of ordinary skill in the art will appreciate that all or part of step in said method can come instruction related hardware to complete by program, described program can be stored in computer-readable recording medium, as ROM (read-only memory), disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuit.Correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (10)
1. a data transmission method for direct memory access dma controller, is characterized in that, is applied to the dma controller that comprises a plurality of DMA engines, and described DMA engine comprises that system arrives equipment DMA engine and equipment to system DMA engine, and described method comprises:
When a plurality of described systems send request read command by arbitration mechanism to system to equipment DMA engine, system sends to reception message distribution module to the first message of equipment or read operation order by be sent, described reception message distribution module is resolved the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order is distributed to corresponding system to equipment DMA engine; Described system is transmitted to relevant device after equipment DMA engine obtains described the first message;
When a plurality of described equipment is worked to system DMA engine simultaneously, equipment sends to each equipment to system DMA engine by the second message of system of giving to be sent, a plurality of equipment sends request write order by arbitration mechanism to system to system DMA engine, system is received after described request write order, write operation order is sent to and receives message distribution module, described reception message distribution module is resolved the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine; Equipment is received after described write operation order to system DMA engine, by arbitration mechanism, sends described the second message to system.
2. method according to claim 1, is characterized in that, describedly by arbitration mechanism, sends the second message and comprises to the step of system:
The second message that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described the second message through arbitration is carried out again to prioritization arbitration;
The described step that sends request write order to system by arbitration mechanism comprises:
The request write order that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described request write order through arbitration is carried out again to prioritization arbitration;
The described step that sends request read command by arbitration mechanism comprises:
Prioritization arbitration is carried out in the request read command that system described in each is sent to equipment DMA engine, to carry out again prioritization arbitration through the described order of arbitration.
3. method according to claim 2, it is characterized in that: also comprise: according to internal interrupt and/or external interrupt, generate interrupt request, interrupt request is carried out to priority arbitration, after arbitration, generate and interrupt message, send to arbitration mechanism again to carry out prioritization arbitration together with described the second message described interruption message, after arbitration, described interruption message is sent to system.
4. method according to claim 1, it is characterized in that, obtain the step of described the first message to equipment DMA engine in described system before, also comprise: described system is initiated descriptor information to equipment DMA engine, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system is obtained the step of described the first message described in carrying out from system according to described descriptor information to equipment DMA engine.
5. method according to claim 1, it is characterized in that, before sending the step of described the second message to system, also comprise: described equipment is initiated descriptor information to system DMA engine, described descriptor information is write to the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, described equipment sends described the second message data message to the step of system to system DMA according to described descriptor information.
6. a data transmission device for direct memory access controller, is characterized in that, comprising: receive message distribution module, arbitration modules, a plurality of DMA engine modules;
Described a plurality of DMA engine modules comprises that a plurality of systems are to equipment DMA engine modules, a plurality of equipment to system DMA engine modules;
Described system is used for to system, sending request read command by arbitration modules to equipment DMA engine modules; The first message or read operation order that receiving system sends over by receiving message distribution module; When the system of obtaining the first message to equipment to be sent, be transmitted to relevant device;
Described reception message distribution module is for receiving the first message or the read operation order to equipment to be sent from system, resolve the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order are distributed to corresponding system to equipment DMA engine modules;
Described reception message distribution module also sends to equipment to the write operation order of system DMA engine modules for receiving system, resolve the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine modules;
Described equipment is used for to system, sending request write order by arbitration modules to system DMA engine modules; Described equipment also for receiving after described write operation order, sends described second message to system by arbitration modules to system DMA engine modules;
Described arbitration modules is carried out priority arbitration for the request read command that system is sent to system to equipment DMA engine modules; Described arbitration modules is also carried out priority arbitration for request write order or the second message that equipment is sent to system to system DMA engine modules.
7. device according to claim 6, is characterized in that, described arbitration modules comprises one instance arbitration module, secondary arbitration modules;
Described one instance arbitration module is carried out prioritization arbitration for the second message or the request write order that equipment described in each is sent to system DMA engine modules;
Described secondary arbitration modules is carried out again prioritization arbitration for described the second message to through one instance arbitration or described request write order;
Described one instance arbitration module is carried out prioritization arbitration for the request read command that system described in each is sent to equipment DMA engine modules,
Described secondary arbitration modules is for carrying out again prioritization arbitration to sending request read command described in process one instance arbitration;
Described secondary arbitration modules is also for carrying out again prioritization arbitration to described interruption message.
8. device according to claim 7, is characterized in that, also comprises interrupt arbitrage module, interrupts generation module; Described interruption generation module generates interrupt request according to internal interrupt and/or external interrupt, and the interrupt request that described interrupt arbitrage module generates described interruption generation module is carried out prioritization second month in a season
Cut out, after prioritization arbitration, generate and interrupt message, described interrupt arbitrage module is sent to secondary arbitration modules by described interruption message and participates in prioritization arbitration together with described the second message, and described interruption message is sent to system after the arbitration of secondary arbitration modules prioritization.
9. device according to claim 6, it is characterized in that, also comprise the first descriptor register, system to equipment DMA engine modules also for before obtaining the step of described the first message, described system is initiated descriptor information to equipment DMA engine modules, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system to equipment DMA engine modules according to described descriptor information from the first message described in system acquisition.
10. device according to claim 6, it is characterized in that, also comprise the second descriptor register, described equipment to system DMA engine modules also for by arbitration modules, send described the second message to system before, initiate descriptor information, described descriptor information is write to described the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, carry out the described operation that described the second message is sent to system.
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| CN201410012698.9A CN103714027B (en) | 2014-01-10 | 2014-01-10 | A kind of data transmission method of direct memory access controller and device |
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| CN201410012698.9A CN103714027B (en) | 2014-01-10 | 2014-01-10 | A kind of data transmission method of direct memory access controller and device |
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| CN103714027B CN103714027B (en) | 2016-04-20 |
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| CN201410012698.9A Active CN103714027B (en) | 2014-01-10 | 2014-01-10 | A kind of data transmission method of direct memory access controller and device |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104298628A (en) * | 2014-09-30 | 2015-01-21 | 中国电子科技集团公司第三十八研究所 | Data storage device arbitration circuit and method for concurrent access |
| CN105573933A (en) * | 2014-10-17 | 2016-05-11 | 瑞昱半导体股份有限公司 | Processor and method for accessing to memory |
| WO2016138817A1 (en) * | 2015-03-03 | 2016-09-09 | 中兴通讯股份有限公司 | Message moving method and apparatus |
| CN109359069A (en) * | 2018-09-25 | 2019-02-19 | 济南浪潮高新科技投资发展有限公司 | A kind of data transmission method and device |
| CN111401541A (en) * | 2020-03-10 | 2020-07-10 | 湖南国科微电子股份有限公司 | Data transmission control method and device |
| CN112199309A (en) * | 2020-10-10 | 2021-01-08 | 北京泽石科技有限公司 | Data reading method and device based on DMA engine and data transmission system |
| CN112447227A (en) * | 2019-08-28 | 2021-03-05 | 美光科技公司 | Command tracking |
| CN112749112A (en) * | 2020-12-31 | 2021-05-04 | 无锡众星微系统技术有限公司 | Hardware flow structure |
| CN113742267A (en) * | 2021-09-07 | 2021-12-03 | 中国科学院计算技术研究所 | DMA communication system and method for RDMA communication equipment |
| CN113900977A (en) * | 2021-09-16 | 2022-01-07 | 深圳致星科技有限公司 | DMA data transmission optimization method in federal learning |
| CN114443529A (en) * | 2022-04-02 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Direct memory access architecture, system, method, electronic device and medium |
| CN115658571A (en) * | 2022-11-16 | 2023-01-31 | 浪潮电子信息产业股份有限公司 | Data transmission method, device, electronic equipment and medium |
| CN117749718A (en) * | 2023-12-07 | 2024-03-22 | 无锡众星微系统技术有限公司 | DMA transmission order-preserving processing method and device based on ACK and NOP mechanisms |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6651119B2 (en) * | 1998-11-16 | 2003-11-18 | Lsi Logic Corporation | Method for allocating priorities to plurality of DMA engines for processing data packets based on bus phase and transactions status |
| CN1996272A (en) * | 2006-02-24 | 2007-07-11 | 威盛电子股份有限公司 | Method for dynamically using direct memory access channel and arbitration circuit therefor |
| US7324438B1 (en) * | 2003-02-13 | 2008-01-29 | Cisco Technology, Inc. | Technique for nondisruptively recovering from a processor failure in a multi-processor flow device |
| US8214553B2 (en) * | 2010-02-01 | 2012-07-03 | Oracle America, Inc. | Virtualization of an input/output device for supporting multiple hosts and functions |
-
2014
- 2014-01-10 CN CN201410012698.9A patent/CN103714027B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6651119B2 (en) * | 1998-11-16 | 2003-11-18 | Lsi Logic Corporation | Method for allocating priorities to plurality of DMA engines for processing data packets based on bus phase and transactions status |
| US7324438B1 (en) * | 2003-02-13 | 2008-01-29 | Cisco Technology, Inc. | Technique for nondisruptively recovering from a processor failure in a multi-processor flow device |
| CN1996272A (en) * | 2006-02-24 | 2007-07-11 | 威盛电子股份有限公司 | Method for dynamically using direct memory access channel and arbitration circuit therefor |
| US8214553B2 (en) * | 2010-02-01 | 2012-07-03 | Oracle America, Inc. | Virtualization of an input/output device for supporting multiple hosts and functions |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104298628B (en) * | 2014-09-30 | 2017-12-29 | 中国电子科技集团公司第三十八研究所 | A kind of data storage arbitration circuit and referee method for concurrently accessing |
| CN104298628A (en) * | 2014-09-30 | 2015-01-21 | 中国电子科技集团公司第三十八研究所 | Data storage device arbitration circuit and method for concurrent access |
| CN105573933A (en) * | 2014-10-17 | 2016-05-11 | 瑞昱半导体股份有限公司 | Processor and method for accessing to memory |
| CN105573933B (en) * | 2014-10-17 | 2018-10-09 | 瑞昱半导体股份有限公司 | Processor and the method for accessing memory |
| WO2016138817A1 (en) * | 2015-03-03 | 2016-09-09 | 中兴通讯股份有限公司 | Message moving method and apparatus |
| CN109359069A (en) * | 2018-09-25 | 2019-02-19 | 济南浪潮高新科技投资发展有限公司 | A kind of data transmission method and device |
| CN112447227A (en) * | 2019-08-28 | 2021-03-05 | 美光科技公司 | Command tracking |
| CN111401541A (en) * | 2020-03-10 | 2020-07-10 | 湖南国科微电子股份有限公司 | Data transmission control method and device |
| CN112199309B (en) * | 2020-10-10 | 2022-03-15 | 北京泽石科技有限公司 | Data reading method and device based on DMA engine and data transmission system |
| CN112199309A (en) * | 2020-10-10 | 2021-01-08 | 北京泽石科技有限公司 | Data reading method and device based on DMA engine and data transmission system |
| CN112749112A (en) * | 2020-12-31 | 2021-05-04 | 无锡众星微系统技术有限公司 | Hardware flow structure |
| CN112749112B (en) * | 2020-12-31 | 2021-12-24 | 无锡众星微系统技术有限公司 | Hardware flow structure |
| CN113742267A (en) * | 2021-09-07 | 2021-12-03 | 中国科学院计算技术研究所 | DMA communication system and method for RDMA communication equipment |
| CN113742267B (en) * | 2021-09-07 | 2023-10-27 | 中国科学院计算技术研究所 | DMA communication system and method for RDMA communication equipment |
| CN113900977A (en) * | 2021-09-16 | 2022-01-07 | 深圳致星科技有限公司 | DMA data transmission optimization method in federal learning |
| CN114443529A (en) * | 2022-04-02 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Direct memory access architecture, system, method, electronic device and medium |
| CN115658571A (en) * | 2022-11-16 | 2023-01-31 | 浪潮电子信息产业股份有限公司 | Data transmission method, device, electronic equipment and medium |
| CN115658571B (en) * | 2022-11-16 | 2023-02-28 | 浪潮电子信息产业股份有限公司 | Data transmission method, device, electronic equipment and medium |
| CN117749718A (en) * | 2023-12-07 | 2024-03-22 | 无锡众星微系统技术有限公司 | DMA transmission order-preserving processing method and device based on ACK and NOP mechanisms |
| CN117749718B (en) * | 2023-12-07 | 2024-07-16 | 无锡众星微系统技术有限公司 | DMA transmission order-preserving processing method and device based on ACK and NOP mechanisms |
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