CN103714027A - Data transmission method and device for direct memory access controller - Google Patents

Abstract

A data transmission method and device for a direct memory access DMA controller. When multiple system-to-device DMA engines send request read commands to the system through an arbitration mechanism, the system sends the first message or read command to be sent to the device. The operation command is sent to the receiving message distribution module, and the receiving message distribution module parses the request identifier of the first message or the read operation command, and distributes the first message or the read operation command according to the request identifier The corresponding system-to-device DMA engine; multiple device-to-system DMA engines send request write commands to the system through the arbitration mechanism, and the system sends the write operation command to the receiving message distribution module, and then transmits it to the device-to-system DMA engine, and then the device to the system The system DMA engine sends the second message to the system through an arbitration mechanism. Using multiple sets of parallel DMA engines to work at the same time can significantly improve the efficiency of DMA devices receiving and sending data and improve system performance.

Description

A data transmission method and device for a direct memory access controller

technical field

The invention relates to the field of computer system design and integrated circuit design, and in particular to a data transmission method and device of a direct memory access controller.

Background technique

With the rapid development of computer technology and integrated circuit technology, high-performance computer systems have increasingly become the needs of economic and social development. The data transmission bandwidth of the computer system reaches tens of GB/s, and at the same time, the data processing and analysis capabilities of the computer system accessories are getting higher and higher, which brings challenges to the data transmission capability. On the one hand, it is necessary to increase the amount of data transmitted from the system to the device, that is, to increase the utilization rate of the system data transmission bandwidth as much as possible; on the other hand, it is necessary to avoid CPU computing resources consumed by data transmission as much as possible. This requires the use of advanced DMA (Direct Memory Access, memory direct access) transmission technology, DMA (Direct Memory Access, memory direct access) refers to a high-speed data transmission operation that allows direct reading and writing between external devices and memory data.

The DMA transfer technology can not only effectively improve data transfer efficiency, but also avoid consumption of CPU computing resources.

However, the transmission efficiency of a single DMA engine is low, and the transmission bandwidth utilization rate of the data processing system is not high, which affects the system performance.

Contents of the invention

The technical problem to be solved by the present invention is to overcome the problem of low transmission efficiency of a single DMA engine, and adopt multiple groups of parallel DMA engines to work at the same time, which can significantly improve the efficiency of receiving and sending data by DMA devices and improve system performance.

A data transmission method of a direct memory access DMA controller, applied to a DMA controller comprising a plurality of DMA engines, the DMA engines comprising a system-to-device DMA engine and a device-to-system DMA engine, the method comprising:

When multiple system-to-device DMA engines send request read commands to the system through the arbitration mechanism, the system sends the first message or read operation command to be sent to the device to the receiving message distribution module, and the receiving message distribution module The module parses the request identifier of the first message or the read operation command, and distributes the first message or the read operation command to the corresponding system-to-device DMA engine according to the request identifier; the system-to-device DMA engine acquires The first message is then forwarded to the corresponding device;

When multiple described device-to-system DMA engines work at the same time, the device sends the second message to be sent to the system to each device-to-system DMA engine, and multiple device-to-system DMA engines send requests to the system through an arbitration mechanism. command, after the system receives the request write command, it sends the write operation command to the receiving message distribution module, and the receiving message distribution module analyzes the request identifier of the write operation command, and sends the write operation command according to the identifier The write operation command is distributed to the corresponding device-to-system DMA engine; after receiving the write operation command, the device-to-system DMA engine sends the second message to the system through an arbitration mechanism.

Optionally, the step of sending the second message to the system through the arbitration mechanism includes:

performing priority sorting arbitration on each of the second messages sent by the device-to-system DMA engine; performing priority sorting arbitration again on the arbitrated second messages;

The step of sending a request write command to the system through an arbitration mechanism includes:

Perform priority order arbitration on the request write commands sent from each of the devices to the system DMA engine; perform priority order arbitration again on the arbitrated request write commands;

The step of sending a request read command through an arbitration mechanism includes:

Perform priority sorting arbitration on the request read commands sent by each system-to-device DMA engine, and perform priority sorting arbitration again on the commands that have been arbitrated.

Optionally, it also includes: generating an interrupt request according to an internal interrupt and/or an external interrupt, performing priority arbitration on the interrupt request, generating an interrupt message after the arbitration, and sending the interrupt message to the arbitration mechanism and the second report After the arbitration, the interrupt message is sent to the system.

Optionally, before the step of obtaining the first message by the system-to-device DMA engine, the method further includes: the system-to-device DMA engine initiates descriptor information, and writes the descriptor information into the first descriptor register , when receiving the read operation command with descriptor information returned by the system, the system-to-device DMA engine performs the step of obtaining the first message from the system according to the descriptor information.

Optionally, before the step of sending the second message to the system, it also includes: the device-to-system DMA engine initiates descriptor information, writes the descriptor information into the second descriptor register, and when receiving the system When the write operation command with descriptor information is returned, the device-to-system DMA performs the step of sending the second message data message to the system according to the descriptor information.

A data transmission device of a direct memory access controller, comprising: a receiving message distribution module, an arbitration module, and multiple DMA engine modules;

The multiple DMA engine modules include multiple system-to-equipment DMA engine modules, and multiple equipment-to-system DMA engine modules;

The system-to-device DMA engine module is used to send a request read command to the system through the arbitration module; the receiving system receives the first message or read operation command sent by the message distribution module; When the message is forwarded to the corresponding device;

The receiving message distribution module is used to receive the first message or read operation command to be sent to the device from the system, analyze the request identifier of the first message or read operation command, and allocate the first message or read operation command according to the request identifier. A message or read operation command is distributed to the corresponding system-to-device DMA engine module;

The receiving message distribution module is also used for receiving the write operation command sent by the system to the device to the system DMA engine module, parsing the request identifier of the write operation command, and distributing the write operation command to the corresponding The device-to-system DMA engine module;

The device-to-system DMA engine module is used to send a request write command to the system through the arbitration module; the device-to-system DMA engine module is also used to send the second message through the arbitration module after receiving the write operation command to the system.

The arbitration module is used to perform priority arbitration on the request read command sent to the system by the system-to-device DMA engine module; files for priority arbitration.

Optionally, the arbitration module includes a primary arbitration module and a secondary arbitration module;

The first-level arbitration module is configured to perform priority order arbitration on the second messages or request write commands sent by each of the device-to-system DMA engine modules;

The second-level arbitration module is configured to perform another priority-sorting arbitration on the second message or the request write command that has undergone the first-level arbitration;

The first-level arbitration module is configured to perform priority order arbitration on the request read commands sent by each of the system-to-device DMA engine modules,

The second-level arbitration module is used to perform another priority order arbitration on the send request read command that has undergone the first-level arbitration;

The second-level arbitration module is also used for re-arbitrating the interrupt packets with priority ordering.

Optionally, an interrupt arbitration module and an interrupt generation module are also included; the interrupt generation module generates interrupt requests according to internal interrupts and/or external interrupts, and the interrupt arbitration module prioritizes the interrupt requests generated by the interrupt generation module Arbitration, priority sorting arbitration to generate an interrupt message,

The interrupt arbitration module sends the interrupt message to the secondary arbitration module to participate in priority sorting arbitration together with the second message, and the interrupt message is sent to the system after being prioritized and arbitrated by the secondary arbitration module.

Optionally, it also includes a first descriptor register, and the system-to-device DMA engine module is also used to initiate descriptor information from the system-to-device DMA engine module before the step of obtaining the first message, and transfer the description The descriptor information is written into the first descriptor register, and when receiving a read operation command with descriptor information returned by the system, the system-to-device DMA engine module obtains the first message from the system according to the descriptor information.

Optionally, it also includes a second descriptor register, and the device-to-system DMA engine module is also used to initiate descriptor information and write the descriptor information before sending the second message to the system through the arbitration module When receiving the write operation command with descriptor information returned by the system, perform the operation of sending the second message to the system.

The invention designs multiple sets of DMA engines in the DMA module inside the chip to make them work in parallel. When receiving the first message from the system, the receiving message distribution module is responsible for parsing the request identifier ID of the received message, and completes the distribution to each DMA engine, and when sending the second message to the system, the internal DMA engine The first-level arbitration controls the conflict of sending messages inside, and the second-level arbitration module controls the conflict of sending messages of multiple DMA engines. Similarly, interrupt requests are generated internally by each DMA engine, and then the interrupt arbitration module performs arbitration control, generates an interrupt message, and sends it to the arbitration module for arbitration control. The multi-level arbitration control and interrupt arbitration control of multiple groups of DMA engines can effectively avoid the collision problem of massive message transmission, so it has broad development prospects in high-bandwidth transmission systems or large data processing systems, and has a high potential technical value.

Description of drawings

Fig. 1 is the operation flowchart when the system receives data from the device DMA engine module;

Fig. 2 is the operation flowchart when the device sends data to the system DMA engine module;

Fig. 3 is a device diagram of multiple parallel DMA engine modules working simultaneously.

Detailed ways

The technical solution of the present invention will be described in more detail below with reference to the drawings and embodiments.

It should be noted that, if there is no conflict, the embodiments of the present invention and various features in the embodiments can be combined with each other, and all are within the protection scope of the present invention. In addition, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

Before explaining the implementation manner, several meanings are firstly explained.

The first message refers to a message sent from the system to the device;

The second message refers to a message sent from the device to the system.

The DMA engine module includes a system-to-device DMA engine module and a device-to-system DMA engine module. The DMA engine module receives data from the system to the device, and the DMA engine module sends data from the device to the system.

Embodiment one

The operation flow when the system-to-device DMA engine module receives data is described in conjunction with FIG. 1 and FIG. 3 .

A data transmission method of a direct memory access DMA controller, applied to a DMA controller comprising a plurality of DMA engines, the DMA engines comprising a system-to-device DMA engine and a device-to-system DMA engine, the method comprising:

When multiple system-to-device DMA engines send request read commands to the system through the arbitration mechanism, the system sends the first message or read operation command to be sent to the device to the receiving message distribution module, and the receiving message distribution module The module parses the request identifier of the first message or the read operation command, and distributes the first message or the read operation command to the corresponding system-to-device DMA engine according to the request identifier; the system-to-device DMA engine acquires The first message is then forwarded to the corresponding device;

The step of sending a request read command through an arbitration mechanism includes:

Perform priority sorting arbitration on the request read commands sent by each system-to-device DMA engine, and perform priority sorting arbitration again on the commands that have been arbitrated.

It can be seen from Figure 3 that multiple system-to-device DMA engines work simultaneously.

Firstly, the system-to-device DMA engine initiates the request read command. In order to avoid competition conflicts caused by sending multiple request read commands from the same system to the device at the same time, an arbitration mechanism is established. After the first-level arbitration, the request read command with high priority can take priority By this, low-priority request read commands can be sent with a delay.

The request read command with high priority goes through the first-level arbitration and then the second-level arbitration, and then enters the system after the second-level arbitration. The establishment of the second-level arbitration is mainly to avoid contention conflicts caused by simultaneous transmission of read commands sent by different system-to-device DMA engines to the system after the first-level arbitration.

Before the step of obtaining the first message by the system-to-device DMA engine, it also includes: the system-to-device DMA engine initiates descriptor information, writes the descriptor information into the first descriptor register, and when received When the system returns a read operation command with descriptor information, the system-to-device DMA engine performs the step of acquiring the first message from the system according to the descriptor information.

After the system receives the request read command, the system sends the first message and a read operation response command with data, that is, a read operation command with descriptor information. The read operation command with descriptor information and the first message arrive at the message distribution module first, and the read operation command or the first message has a one-to-one correspondence with the system-to-device DMA engine module, which is distinguished by the request identifier ID. The receiving message distribution module parses the read operation command or the request identifier ID of the first message, and distributes the read operation command with descriptor information and the first message to the receiving end, and the receiving end and the system to the device DMA The engine module is connected,

There is also a descriptor register inside the system-to-device DMA engine module. The first message or a read operation command with descriptor information enters the descriptor register inside the system-to-device DMA engine module through the register interface of the receiving end. The system-to-device DMA The engine module initiates descriptor information, writes the descriptor information into the first descriptor register, and when the first descriptor register receives a read operation command with descriptor information returned by the system, the first descriptor register will Send the first packet to the system-to-device DMA engine module.

The first descriptor register can also be external to the system-to-device DMA engine module.

After the first message is sent to the system-to-device DMA engine module, it is forwarded to the device by the system-to-device DMA.

Due to the arbitration mechanism and message distribution mechanism, multiple system-to-device DMA engines can initiate read operation requests at the same time, so the efficiency of system data transmission can be greatly improved.

Embodiment two

The operation flow when the device-to-system DMA engine module transmits data is described with reference to FIG. 2 and FIG. 3 .

A data transmission method of a direct memory access DMA controller, applied to a DMA controller comprising a plurality of DMA engines, the DMA engines comprising a system-to-device DMA engine and a device-to-system DMA engine, the method comprising:

When multiple described device-to-system DMA engines work at the same time, the device sends the second message to be sent to the system to each device-to-system DMA engine, and multiple device-to-system DMA engines send requests to the system through an arbitration mechanism. command, after the system receives the request write command, it sends the write operation command to the receiving message distribution module, and the receiving message distribution module analyzes the request identifier of the write operation command, and sends the write operation command according to the identifier The write operation command is distributed to the corresponding device-to-system DMA engine; after receiving the write operation command, the device-to-system DMA engine sends the second message to the system through an arbitration mechanism.

Optionally, the step of sending the second message to the system through the arbitration mechanism includes:

performing priority sorting arbitration on each of the second messages sent by the device-to-system DMA engine; performing priority sorting arbitration again on the arbitrated second messages;

The step of sending a request write command to the system through an arbitration mechanism includes:

performing priority order arbitration on the request write commands sent by each device-to-system DMA engine; and performing priority order arbitration again on the arbitrated request write commands.

First, when the device-to-system DMA engine is sending data to the system, the device-to-system DMA first initiates a write operation request, and the device-to-system DMA sends a request write command to the first-level arbitration module.

The first-level arbitration performs priority arbitration on request write commands. Those with high priority can be sent first, and those with low priority can be sent later.

Request write commands with high priority go through the first-level arbitration and then go through the second-level arbitration, and then go through the priority arbitration again, and then enter the system after the second-level arbitration.

The establishment of the second-level arbitration is mainly to avoid competition conflicts due to the simultaneous transmission of the write commands sent by different device-to-system DMAs to the system after the first-level arbitration.

Optionally, it also includes: generating an interrupt request according to an internal interrupt and/or an external interrupt, performing priority arbitration on the interrupt request, generating an interrupt message after the arbitration, and sending the interrupt message to the arbitration mechanism and the second report After the arbitration, the interrupt message is sent to the system.

Internal interrupts refer to system-to-device DMA engines, device-to-system DMA engines, first-level arbitration mechanisms, and system-generated interrupts. When multiple interrupt requests are generated, multiple interrupt requests will cause contention and send conflicts. At this time, Priority arbitration is required for interrupt requests, those with high priority can be sent to the system first, and those with low priority can be sent later.

The arbitration of the interrupt priority can be realized through the interrupt priority arbitration, and the interrupt message can also be generated. The interrupt request with high priority generates an interrupt message, and the interrupt message is sent to the secondary arbitration mechanism and the device to be sent to the system. The second message participates in priority arbitration together, and is sent to the system after secondary arbitration.

Optionally, before the step of sending the second message to the system, it also includes: the device-to-system DMA engine initiates descriptor information, writes the descriptor information into the second descriptor register, and when receiving the system When the write operation command with descriptor information is returned, the device-to-system DMA performs the step of sending the second message data message to the system according to the descriptor information.

After the system receives the request write command, the system sends a write operation response command with data, that is, a write operation command with descriptor information. The write operation command with descriptor information first arrives at the message distribution module, and the write operation command has a one-to-one correspondence with the device to the system DMA engine module, which is distinguished by the request identifier ID, and the receiving message distribution module parses the The request identifier ID of the read operation command, the write operation command is distributed to the receiving end, and the receiving end is connected with the device to the system DMA engine module,

The second descriptor register may be within the device-to-system DMA engine or external to the device-to-system DMA engine;

The write operation command with descriptor information enters the second descriptor register inside the device-to-system DMA engine module through the register interface of the receiving end, and the device-to-system DMA engine module initiates the descriptor information and writes the descriptor information into the descriptor The register, the device-to-system DMA engine sends the second message to the system according to the descriptor information.

The second descriptor register can also be external to the device-to-system DMA engine module.

Due to the arbitration mechanism and message distribution mechanism, multiple devices can initiate write operation requests to the system DMA engine at the same time, so the efficiency of system data transmission can be greatly improved.

When only one DMA engine is working, the priority control of its internal interrupt and external interrupt is completed in the interrupt generation module.

Embodiments of device claims are explained in conjunction with FIG. 3 .

A data transmission device of a direct memory access controller, comprising: a receiving message distribution module, an arbitration module, and multiple DMA engine modules;

The multiple DMA engine modules include multiple system-to-equipment DMA engine modules, and multiple equipment-to-system DMA engine modules;

The system-to-device DMA engine module is used to send a request read command to the system through the arbitration module; the receiving system receives the first message or read operation command sent by the message distribution module; When the message is forwarded to the corresponding device;

The receiving message distribution module is used to receive the first message or read operation command to be sent to the device from the system, analyze the request identifier of the first message or read operation command, and allocate the first message or read operation command according to the request identifier. A message or read operation command is distributed to the corresponding system-to-device DMA engine module;

The receiving message distribution module is also used for receiving the write operation command sent by the system to the device to the system DMA engine module, parsing the request identifier of the write operation command, and distributing the write operation command to the corresponding The device-to-system DMA engine module;

The device-to-system DMA engine module is used to send a request write command to the system through the arbitration module; the device-to-system DMA engine module is also used to send the second message through the arbitration module after receiving the write operation command to the system.

The arbitration module is used to perform priority arbitration on the request read command sent to the system by the system-to-device DMA engine module; files for priority arbitration.

Optionally, the arbitration module includes a primary arbitration module and a secondary arbitration module;

The first-level arbitration module is configured to perform priority order arbitration on the second messages or request write commands sent by each of the device-to-system DMA engine modules;

The second-level arbitration module is configured to perform another priority-sorting arbitration on the second message or the request write command that has undergone the first-level arbitration;

For example, a device-to-system DMA engine module receives the second message A and the second message B sent by the device at the same time, and the two messages generate a contention conflict, and the first-level arbitration module compares the second message A and the second message B B performs priority arbitration. If the priority of A is higher than that of B, the message A with higher priority is sent to the secondary arbitration module first. The second-level arbitration module receives message A and at the same time receives message C from another device-to-system DMA engine module. At this time, it needs to perform priority order arbitration on messages A and C. If the priority of A is If the priority is higher than C, message A is sent to the system by the second arbitration module first.

The first-level arbitration module is configured to perform priority order arbitration on the request read commands sent by each of the system-to-device DMA engine modules,

The second-level arbitration module is used to perform another priority order arbitration on the send request read command that has undergone the first-level arbitration;

The secondary arbitration module is also used to perform priority ordering arbitration on the interrupt message again;

Optionally, an interrupt arbitration module and an interrupt generation module are also included; the interrupt generation module generates interrupt requests according to internal interrupts and/or external interrupts, and the interrupt arbitration module prioritizes the interrupt requests generated by the interrupt generation module Arbitration, after the priority sorting arbitration, an interrupt message is generated, and the interrupt arbitration module sends the interrupt message to the secondary arbitration module to participate in the priority sorting arbitration together with the second message, and the interrupt message passes through two Arbitration module prioritizes and sends to the system after arbitration.

The system-to-device DMA engine module, the device-to-system engine module, the first-level arbitration module, and the system can all generate interrupts or interrupt requests.

The interrupt request of the system is transmitted to the interrupt register through the receiving message distribution module and the receiving end, and the interrupt register sends the interrupt request of the system to the interrupt generating module.

The interrupt generating module can also receive an external interrupt request and generate an interrupt request message.

When multiple interrupt request messages are generated at the same time, it is necessary to perform priority order arbitration on the interrupt request messages. The interrupt arbitration module performs priority order arbitration on the interrupt requests. The interrupt request with high priority is generated as an interrupt message.

For example, the external interrupt request A, the system-to-device DMA module has an interrupt request B, and the interrupt generation module simultaneously generates the external interrupt request A and the system-to-device DMA engine module interrupt request B, because A and B occur at the same time, an interrupt is required The arbitration module performs priority sorting. If A is prioritized, the interrupt arbitration module first generates an interrupt request message for A, sends the interrupt request message A to the second arbitration module, and prioritizes the second message sent by the device to the system. Level sorting arbitration, if the priority of the interrupt request message A is greater than the priority of the second message C, then the interrupt request message A is sent to the system first.

Optionally, it also includes a first descriptor register, and the system-to-device DMA engine module is also used to initiate descriptor information from the system-to-device DMA engine module before the step of obtaining the first message, and transfer the description The descriptor information is written into the first descriptor register, and when receiving a read operation command with descriptor information returned by the system, the system-to-device DMA engine module obtains the first message from the system according to the descriptor information.

The first descriptor register can be inside the system-to-device DMA engine module or outside the system-to-device DMA engine module.

Optionally, it also includes a second descriptor register, and the device-to-system DMA engine module is also used to initiate descriptor information and write the descriptor information before sending the second message to the system through the arbitration module When receiving the write operation command with descriptor information returned by the system, perform the operation of sending the second message to the system.

The second descriptor register can be inside the device-to-system DMA engine module or outside the device-to-system DMA engine module.

The present invention fully considers the characteristics of the data transmission bandwidth of the computer system and the data processing and analysis ability of the accessory equipment, adopts multiple sets of parallel DMA engine technology, cooperates with the corresponding multi-level arbitration control technology, and performs DMA in two directions from the system to the device and from the device to the system. The engines respectively implement multiple groups of parallel work, so as to improve the transmission bandwidth utilization rate of the data processing system, thereby achieving the purpose of improving system performance.

Those skilled in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk, and the like. Optionally, all or part of the steps in the foregoing embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the foregoing embodiments may be implemented in the form of hardware, or may be implemented in the form of software function modules. The present invention is not limited to any specific combination of hardware and software.

Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention, but these corresponding Changes and deformations should all belong to the protection scope of the claims of the present invention.

Claims (10)

1. a data transmission method for direct memory access dma controller, is characterized in that, is applied to the dma controller that comprises a plurality of DMA engines, and described DMA engine comprises that system arrives equipment DMA engine and equipment to system DMA engine, and described method comprises:

When a plurality of described systems send request read command by arbitration mechanism to system to equipment DMA engine, system sends to reception message distribution module to the first message of equipment or read operation order by be sent, described reception message distribution module is resolved the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order is distributed to corresponding system to equipment DMA engine; Described system is transmitted to relevant device after equipment DMA engine obtains described the first message;

When a plurality of described equipment is worked to system DMA engine simultaneously, equipment sends to each equipment to system DMA engine by the second message of system of giving to be sent, a plurality of equipment sends request write order by arbitration mechanism to system to system DMA engine, system is received after described request write order, write operation order is sent to and receives message distribution module, described reception message distribution module is resolved the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine; Equipment is received after described write operation order to system DMA engine, by arbitration mechanism, sends described the second message to system.

2. method according to claim 1, is characterized in that, describedly by arbitration mechanism, sends the second message and comprises to the step of system:

The second message that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described the second message through arbitration is carried out again to prioritization arbitration;

The described step that sends request write order to system by arbitration mechanism comprises:

The request write order that equipment described in each is sent to system DMA engine carries out prioritization arbitration; Described request write order through arbitration is carried out again to prioritization arbitration;

The described step that sends request read command by arbitration mechanism comprises:

Prioritization arbitration is carried out in the request read command that system described in each is sent to equipment DMA engine, to carry out again prioritization arbitration through the described order of arbitration.

3. method according to claim 2, it is characterized in that: also comprise: according to internal interrupt and/or external interrupt, generate interrupt request, interrupt request is carried out to priority arbitration, after arbitration, generate and interrupt message, send to arbitration mechanism again to carry out prioritization arbitration together with described the second message described interruption message, after arbitration, described interruption message is sent to system.

4. method according to claim 1, it is characterized in that, obtain the step of described the first message to equipment DMA engine in described system before, also comprise: described system is initiated descriptor information to equipment DMA engine, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system is obtained the step of described the first message described in carrying out from system according to described descriptor information to equipment DMA engine.

5. method according to claim 1, it is characterized in that, before sending the step of described the second message to system, also comprise: described equipment is initiated descriptor information to system DMA engine, described descriptor information is write to the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, described equipment sends described the second message data message to the step of system to system DMA according to described descriptor information.

6. a data transmission device for direct memory access controller, is characterized in that, comprising: receive message distribution module, arbitration modules, a plurality of DMA engine modules;

Described a plurality of DMA engine modules comprises that a plurality of systems are to equipment DMA engine modules, a plurality of equipment to system DMA engine modules;

Described system is used for to system, sending request read command by arbitration modules to equipment DMA engine modules; The first message or read operation order that receiving system sends over by receiving message distribution module; When the system of obtaining the first message to equipment to be sent, be transmitted to relevant device;

Described reception message distribution module is for receiving the first message or the read operation order to equipment to be sent from system, resolve the request identifier of described the first message or read operation order, according to this request mark, described the first message or read operation order are distributed to corresponding system to equipment DMA engine modules;

Described reception message distribution module also sends to equipment to the write operation order of system DMA engine modules for receiving system, resolve the request identifier of described write operation order, according to described identifier, described write operation order is distributed to corresponding equipment to system DMA engine modules;

Described equipment is used for to system, sending request write order by arbitration modules to system DMA engine modules; Described equipment also for receiving after described write operation order, sends described second message to system by arbitration modules to system DMA engine modules;

Described arbitration modules is carried out priority arbitration for the request read command that system is sent to system to equipment DMA engine modules; Described arbitration modules is also carried out priority arbitration for request write order or the second message that equipment is sent to system to system DMA engine modules.

7. device according to claim 6, is characterized in that, described arbitration modules comprises one instance arbitration module, secondary arbitration modules;

Described one instance arbitration module is carried out prioritization arbitration for the second message or the request write order that equipment described in each is sent to system DMA engine modules;

Described secondary arbitration modules is carried out again prioritization arbitration for described the second message to through one instance arbitration or described request write order;

Described one instance arbitration module is carried out prioritization arbitration for the request read command that system described in each is sent to equipment DMA engine modules,

Described secondary arbitration modules is for carrying out again prioritization arbitration to sending request read command described in process one instance arbitration;

Described secondary arbitration modules is also for carrying out again prioritization arbitration to described interruption message.

8. device according to claim 7, is characterized in that, also comprises interrupt arbitrage module, interrupts generation module; Described interruption generation module generates interrupt request according to internal interrupt and/or external interrupt, and the interrupt request that described interrupt arbitrage module generates described interruption generation module is carried out prioritization second month in a season

Cut out, after prioritization arbitration, generate and interrupt message, described interrupt arbitrage module is sent to secondary arbitration modules by described interruption message and participates in prioritization arbitration together with described the second message, and described interruption message is sent to system after the arbitration of secondary arbitration modules prioritization.

9. device according to claim 6, it is characterized in that, also comprise the first descriptor register, system to equipment DMA engine modules also for before obtaining the step of described the first message, described system is initiated descriptor information to equipment DMA engine modules, described descriptor information is write to the first descriptor register, when the read operation order with descriptor information that the system of receiving is returned, described system to equipment DMA engine modules according to described descriptor information from the first message described in system acquisition.

10. device according to claim 6, it is characterized in that, also comprise the second descriptor register, described equipment to system DMA engine modules also for by arbitration modules, send described the second message to system before, initiate descriptor information, described descriptor information is write to described the second descriptor register, when the write operation order with descriptor information that the system of receiving is returned, carry out the described operation that described the second message is sent to system.

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