CN104298628B - A kind of data storage arbitration circuit and referee method for concurrently accessing - Google Patents
A kind of data storage arbitration circuit and referee method for concurrently accessing Download PDFInfo
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- CN104298628B CN104298628B CN201410519692.0A CN201410519692A CN104298628B CN 104298628 B CN104298628 B CN 104298628B CN 201410519692 A CN201410519692 A CN 201410519692A CN 104298628 B CN104298628 B CN 104298628B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
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Abstract
A kind of data storage arbitration circuit for concurrently accessing, including：- be used to connect the peripheral hardware DMA channel one instance arbitration module of peripheral channel request interface, the passage that will ask same memory BLOCK with fixed priority resolving strategy is arranged as from high priority to low priority；- be used to connect the Memory access channel one instance arbitration module of local Memory access channel and internuclear Memory access channel；- be used to connect the peripheral hardware DMA channel of peripheral hardware DMA channel one instance arbitration module and Memory access channel one instance arbitration module and the two level arbitration modules of Memory access channel；- atomic operation instructs protection module, and atomic operation protection flag is set for each memory BLOCK.Child of the present invention provides a kind of for the referee method of the data storage concurrently accessed.The advantage of the invention is that：Effective resolving strategy is provided for multichannel peripheral hardware DMA channel and multichannel Memory access channel concurrent request Multi-ported Data memory, supports the request of Memory access channel atomic type, high-priority channel request can be timely responded to.
Description
Technical field
The present invention relates to a kind of memory arbitration circuit applied to digital signal processor, belongs to digital signal processor skill
Art field.
Background technology
With the horizontal development of microelectronic technique, digital signal processor performance increasingly improves, and processor is from monokaryon to more
Core develops, and integrated external components are also more and more, corresponding, peripheral channel, instruction Memory access channel, internuclear Memory access channel
New demand is proposed to the bandwidth match of data storage.Under this background, the different passage of multichannel priority is visited simultaneously
When asking memory, arbitration and the competitive relation of complexity will occur, instruct the atomic operation in Memory access channel in arbitrated procedure
It it is also required to provide special relay protective scheme.
The content of the invention
The technical problem to be solved of the present invention is that providing one kind can solve the problem that multichannel peripheral hardware DMA (Direct
Memory Access, direct memory access) passage, multichannel Memory access channel be applied to the priority arbitration of data storage
The data storage arbitration circuit of digital signal processor.
The present invention solves above-mentioned technical problem using following technical scheme：A kind of data storage for concurrently accessing
Arbitration circuit, including：
- peripheral hardware DMA channel one instance arbitration module, for connecting peripheral channel request interface, plan is arbitrated with fixed priority
Slightly the passage for asking same memory BLOCK is arranged as from high priority to low priority, it is equal for each memory BLOCK
Similar logic be present, peripheral hardware DMA channel one instance arbitration module tentative prediction goes out the arbitration result of each DMA channel and each
Memory BLOCK seizure condition；
- Memory access channel one instance arbitration module, for connecting local Memory access channel and internuclear Memory access channel, Memory access channel one
External memory request can ask multiple memory BLOCK, to ensure to perform the uniformity of row operation, it is desirable in once asking
Multiple memory BLOCK obtain arbitration power simultaneously, and two groups of Memory access channels are pressed multi-core operation system requirements, arbitrated with fixed priority
Strategy carries out arbitral award；
The two level arbitration modules of-peripheral hardware DMA channel and Memory access channel, for connecting peripheral hardware DMA channel one instance arbitration module
With Memory access channel one instance arbitration module, mould is protected into the arbitration result combination atomic operation instruction of two one instance arbitration module outputs
The protection bit flag joint of block output judges, is more than peripheral hardware DMA channel as resolving strategy using memory access priority, judges peripheral hardware again
The arbitration result and memory BLOCK seizure conditions of DMA channel, generate pause and the handshake of multiplexer channel；
- atomic operation instructs protection module, sets atomic operation protection flag for each memory BLOCK, works as memory access
When channel request is that atomic operation instructs, respective memory BLOCK protection flags are effective, now, if peripheral hardware DMA channel has
Identical BLOCK requests, then judge its two level arbitration result for failure.
Memory arbitration circuit in digital signal processor is present between data storage and request channel, be according to
Prior claims carries out the circuit module of logical process, and its effect essentially consists in：
1st, balanced memory readwrite bandwidth and multiplexer channel bandwidth on demand, it can meet that multi input request channel to multi output rings
Answer the selection of passage.
2nd, by channel priorities requirement, memory data read-write operation is responded, ensures that the request of high priority preferentially obtains
Response, the request of low priority are responded in high priority transfer gap.
3rd, corresponding protection mechanism is provided for atomic operation, ensures the uniformity of atom read-write.
Atomic operation is indivisible, will not be by any other task or event interrupt before being finished.In numeral
In signal processor, it is as follows to define atomic operation instruction：In atomic operation instruction, read request and write request must be held same
Match and use in every trade, meanwhile, do not allow common access instruction occur in remaining instruction slots.I.e. atomic operation is same instruction
One on row reads to write with one.
Present invention also offers a kind of for the referee method of the data storage arbitration concurrently accessed, specifically include following
Step：
Step 1：Judge that peripheral hardware DMA channel M whether there is the read-write requests to memory BLOCK N, and passage M is
It is no to be in limit priority in all peripheral hardware DMA channels, if it is, two are gone to step, if it is not, then going to step three；
Step 2：Judge that Memory access channel whether there is the read-write requests to memory BLOCK N, if it is, going to step
Three, if it is not, then going to step four；
Step 3：Peripheral hardware DMA channel M there is no corresponding arbitration power, if passage M has effective memory read/write
The value of operation, then a following clock cycle front end input register needs holding upper cycle；If there is respective stored in Memory access channel
Device read-write requests read and write arbitration power corresponding to then obtaining；
Step 4：Memory BLOCK P atomic operation instruction protective emblem is detected, if it is valid, going to step three, such as
Fruit is invalid, then goes to step five；
Step 5：Peripheral hardware DMA channel M obtains memory BLOCK P access arbitration power, and its read-write can be chosen to
Corresponding memory input mouth, for read operation, it is also necessary to arbitration result is updated to rear two-stage with streamline, read with generating
Go out data effective marker.
The advantage of the invention is that：Deposited for multichannel peripheral hardware DMA channel and multichannel Memory access channel concurrent request Multi-ported Data
Reservoir provides effective resolving strategy, supports the request of Memory access channel atomic type, can timely respond to high-priority channel
Request, simultaneously as using pure combinational logic circuit, renewable arbitration result of each clock cycle, low-priority channel can
To be able to access memory using high-priority channel transmission gap, the real-time and memory band of multiplexer channel request have been taken into account
The characteristics of width makes full use of.
Brief description of the drawings
Fig. 1 present invention is applied to the structured flowchart of the data storage arbitration circuit of digital signal processor；
Fig. 2 is data storage schematic diagram；
Fig. 3 is that multipath concurrence accesses data storage time diagram.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing.
As shown in figure 1, data storage arbitration circuit is made up of pure combinatorial logic unit, it is inputted asks for multiple access
Passage deposits the reading-writing port of output after parallel-serial conversion, is exported after one instance arbitration, two level arbitration totally three arbitration modules
To corresponding memory input mouth.
Arbitration is in units of memory BLOCK, and Fig. 1 show the arbitration selection for memory BLOCK0, if memory
It is made up of N number of (N is more than 1) BLOCK, then each BLOCK has the data storage for being applied to digital signal processor accordingly
Device arbitration circuit.Atomic operation instructs protective emblem to influence each channel priorities selection and arbitration result in two level arbitration modules.
Identical with arbitration result each cycle regeneration behavior, the atomic operation instruction same each cycle of protection flag updates with access instruction.
As shown in Fig. 2 the data storage that arbitration circuit is supported is made up of multiple BLOCK, each memory BLOCK by
Multiple memory BANK are formed, and the memory BANK depth illustrated in Fig. 2 is 8KB, data bit width 32bit.
As shown in figure 3, T1 moment peripheral hardwares DMA channel 0 initiates the read-write requests to memory BLOCK0, while peripheral hardware DMA
Passage 1 initiates the request to memory BLOCK1, and Memory access channel initiates the request to memory BLOCK2, due to not occurring
BLOCK conflicts, and 3 road access paths obtain arbitration power.
T2 moment peripheral hardwares DMA channel 0 initiates the request to memory BLOCK1, while peripheral hardware DMA channel 1 is also initiated to depositing
Reservoir BLOCK1 request, and do not conflict with Memory access channel request, now Memory access channel is arbitrated with peripheral hardware DMA channel 1
Power, peripheral hardware DMA channel 0 lose arbitration power.
The T3 moment, Memory access channel obtained arbitration power because peripheral hardware DMA channel mutually conflicts with Memory access channel, and peripheral hardware DMA leads to
Road loses arbitration power.
T4 moment Memory access channel initiates atomic operation request, and atomic operation is directed to memory BLOCK2, at the same time,
Peripheral hardware DMA does not occur BLOCK with Memory access channel and conflicted, thus can obtain arbitration power.
Influenceed by atomic operation instruction protective emblem in the T5 periods, any peripheral hardware DMA channel initiate to memory
BLOCK2 request is blocked, and the request for memory BLOCK3 that peripheral hardware DMA channel 0 is initiated can then be chosen to take
Business.
Data storage arbitration circuit specific works mode is as described below：
Step 1：Judge that peripheral hardware DMA channel M whether there is the read-write requests to memory BLOCK N, and passage M is
It is no to be in limit priority in all peripheral hardware DMA channels, if it is, two are gone to step, if it is not, then going to step three；
Step 2：Judge that Memory access channel whether there is the read-write requests to memory BLOCK N, if it is, going to step
Three, if it is not, then going to step four；
Step 3：Peripheral hardware DMA channel M there is no corresponding arbitration power, if passage M has effective memory read/write
The value of operation, then a following clock cycle front end input register needs holding upper cycle；If there is respective stored in Memory access channel
Device read-write requests read and write arbitration power corresponding to then obtaining；
Step 4：Memory BLOCK P atomic operation instruction protective emblem is detected, if it is valid, going to step three, such as
Fruit is invalid, then goes to step five；
Step 5：Peripheral hardware DMA channel M obtains memory BLOCK P access arbitration power, and its read-write can be chosen to
Corresponding memory input mouth, for read operation, it is also necessary to arbitration result is updated to rear two-stage with streamline, read with generating
Go out data effective marker.
Above-mentioned M and P are 1 to any numeral between N.
The preferred embodiment of the invention is the foregoing is only, is not intended to limit the invention creation, it is all at this
All any modification, equivalent and improvement made within the spirit and principle of innovation and creation etc., should be included in the invention
Protection domain within.
Claims (3)
- A kind of 1. data storage arbitration circuit for concurrently accessing, it is characterised in that：Including：- peripheral hardware DMA channel one instance arbitration module, will with fixed priority resolving strategy for connecting peripheral channel request interface Ask same memory BLOCK passage to be arranged by from high priority to low priority, exist for each memory BLOCK Similar logic, peripheral hardware DMA channel one instance arbitration module tentative prediction go out the arbitration result of each DMA channel and each storage Device BLOCK seizure condition；- Memory access channel one instance arbitration module, for connecting local Memory access channel and internuclear Memory access channel, Memory access channel is once deposited Reservoir request can ask multiple memory BLOCK, to ensure to perform the uniformity of row operation, it is desirable to multiple in once asking Memory BLOCK obtains arbitration power simultaneously, and two groups of Memory access channels press multi-core operation system requirements, with fixed priority resolving strategy Carry out arbitral award；The two level arbitration modules of-peripheral hardware DMA channel and Memory access channel, for connecting peripheral hardware DMA channel one instance arbitration module and visit Passage one instance arbitration module is deposited, instructs protection module defeated the arbitration result combination atomic operation of two one instance arbitration module outputs The protection bit flag joint gone out judges, is more than peripheral hardware DMA channel as resolving strategy using memory access priority, judges peripheral hardware DMA again The arbitration result and memory BLOCK seizure conditions of passage, generate pause and the handshake of multiplexer channel；- atomic operation instructs protection module, sets atomic operation protection flag for each memory BLOCK, works as Memory access channel When asking to instruct for atomic operation, respective memory BLOCK protection flags are effective, now, if peripheral hardware DMA channel have it is identical BLOCK is asked, then judges its two level arbitration result for failure.
- A kind of 2. data storage arbitration circuit for concurrently accessing as claimed in claim 1, it is characterised in that：Above-mentioned use It is as described below in the referee method of the data storage arbitration circuit concurrently accessed：Step 1：Judge that peripheral hardware DMA channel M whether there is the read-write requests to memory BLOCK N, and whether passage M locates The limit priority in all peripheral hardware DMA channels, if it is, two are gone to step, if it is not, then going to step three；Step 2：Judge that Memory access channel whether there is the read-write requests to memory BLOCK N, if it is, going to step three, such as Fruit is no, then goes to step four；Step 3：Peripheral hardware DMA channel M there is no corresponding arbitration power, if passage M has effective memory read/write behaviour Make, then following clock cycle front end input register needs to keep the value in a upper cycle；If there is respective memory in Memory access channel Read-write requests read and write arbitration power corresponding to then obtaining；Step 4：Memory BLOCK P atomic operation instruction protective emblem is detected, if it is valid, three are gone to step, if nothing Effect, then go to step five；Step 5：Peripheral hardware DMA channel M obtains memory BLOCK P access arbitration power, and its read-write can be chosen to accordingly Memory input mouth, for read operation, it is also necessary to arbitration result is updated into rear two-stage with streamline, to generate reading number According to effective marker.
- It is 3. a kind of for the referee method of the data storage arbitration concurrently accessed, it is characterised in that：Specifically include following step：Step 1：Judge that peripheral hardware DMA channel M whether there is the read-write requests to memory BLOCK N, and whether passage M locates The limit priority in all peripheral hardware DMA channels, if it is, two are gone to step, if it is not, then going to step three；Step 2：Judge that Memory access channel whether there is the read-write requests to memory BLOCK N, if it is, going to step three, such as Fruit is no, then goes to step four；Step 3：Peripheral hardware DMA channel M there is no corresponding arbitration power, if passage M has effective memory read/write behaviour Make, then following clock cycle front end input register needs to keep the value in a upper cycle；If there is respective memory in Memory access channel Read-write requests read and write arbitration power corresponding to then obtaining；Step 4：Memory BLOCK P atomic operation instruction protective emblem is detected, if it is valid, three are gone to step, if nothing Effect, then go to step five；Step 5：Peripheral hardware DMA channel M obtains memory BLOCK P access arbitration power, and its read-write can be chosen to accordingly Memory input mouth, for read operation, it is also necessary to arbitration result is updated into rear two-stage with streamline, to generate reading number According to effective marker.
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| CN201410519692.0A CN104298628B (en) | 2014-09-30 | 2014-09-30 | A kind of data storage arbitration circuit and referee method for concurrently accessing |
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| CN106294233B (en) * | 2015-06-29 | 2019-05-03 | 华为技术有限公司 | A kind of transfer control method and device of direct memory access |
| CN105812279B (en) * | 2016-03-04 | 2019-05-07 | 北京左江科技股份有限公司 | A kind of network data dispatching method |
| CN107301143B (en) * | 2017-05-08 | 2020-09-04 | 浙江大学 | Asynchronous arbiter based on double-track coding four-phase handshake protocol |
| CN107992675B (en) * | 2017-11-29 | 2020-12-15 | 中国电子科技集团公司第五十四研究所 | Method for testing arbitration circuit in EDA (electronic design automation) verification stage |
| CN109062661B (en) * | 2018-07-10 | 2021-10-26 | 中国电子科技集团公司第三十八研究所 | Multi-channel arbitration circuit of online simulation debugger and scheduling method thereof |
| CN110532205B (en) * | 2019-07-17 | 2021-04-06 | 浙江大华技术股份有限公司 | Data transmission method, data transmission device, computer equipment and computer readable storage medium |
| CN112100097B (en) * | 2020-11-17 | 2021-01-26 | 杭州长川科技股份有限公司 | Multi-test channel priority adaptive arbitration method and memory access controller |
| CN112650697B (en) * | 2020-12-24 | 2023-04-18 | 西安翔腾微电子科技有限公司 | Arbitration circuit of multiple main devices based on DDR3 storage controller interface |
| CN113138802B (en) * | 2021-04-29 | 2024-03-05 | 上海阵量智能科技有限公司 | Command distribution device, method, chip, computer device and storage medium |
| CN113301285A (en) * | 2021-05-11 | 2021-08-24 | 深圳市度信科技有限公司 | Multi-channel data transmission method, device and system |
| CN115269467B (en) * | 2022-09-29 | 2023-01-10 | 沐曦科技(成都)有限公司 | Bus arbitration method and device, storage medium and electronic equipment |
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