CN109062661B - Multi-channel arbitration circuit of online simulation debugger and scheduling method thereof - Google Patents
Multi-channel arbitration circuit of online simulation debugger and scheduling method thereof Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
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- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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Abstract
The invention relates to a multi-channel arbitration circuit of an online simulation debugger, which comprises: the multi-channel acquisition unit is used for acquiring trace events of the kernel and the peripheral equipment, and classifying each trace event according to the attribute, the property and the source of the event so as to represent the type of the currently acquired trace event; the cross switch is used for completing the many-to-one or one-to-one gating of the multi-channel acquisition unit channel and the main buffer area channel; the main buffer area is used for buffering trace data of each channel; the multiplexer is used for completing the many-to-one gating from the main buffer area channel to the output channel; and the arbiter completes the channel queue scheduling of the main buffer area and completes the channel selection arbitration of the multi-path selector. The invention also discloses a scheduling method of the multi-channel arbitration circuit of the online simulation debugger. The method can effectively control the loss of the buffered data, change the exhaustive service mode, ensure that each channel can obtain the arbitration response, further reduce the risk of buffer overflow and reduce the data loss times.
Description
Technical Field
The invention relates to the technical field of digital integrated circuit design, in particular to a multi-channel arbitration circuit of an online simulation debugger and a scheduling method thereof.
Background
The single-step and breakpoint-based emulation debugging system destroys the running environment of the processor program, is difficult to track the concurrent behavior of the program, and cannot observe the internal running environment of the program in real time. The Trace simulation debugging system adopts an online real-time tracing debugging technology, records program execution and data read-write information non-invasively through special hardware, realizes online program tracing and debugging processes in a mode of not damaging a kernel operating environment, and is the research direction of the mainstream online debugging technology at present. However, the existing Trace emulation debugger has the following disadvantages in terms of scheduling algorithm: when a Round-Robin scheduling algorithm is adopted to select a plurality of trace channels, scheduling strategy adjustment cannot be carried out according to the conditions of all the channels, and the problem of buffer data loss exists; when a Funnel scheduling algorithm is adopted to serve multiple trace channels, the problem of data loss of a low-priority channel also exists because the high-priority channel always occupies service and the low-priority channel cannot respond in time.
Disclosure of Invention
The invention mainly aims to provide a multi-channel arbitration circuit of an online simulation debugger, which can effectively reduce the loss of buffer data.
In order to achieve the purpose, the invention adopts the following technical scheme: a multi-channel arbitration circuit for an online emulation debugger, comprising:
the multi-channel acquisition unit is used for acquiring trace events of the kernel instruction buffer channel and the peripheral instruction buffer channel, and classifying each trace event according to the attribute, the property and the source of the event so as to represent the type of the currently acquired trace event;
the cross switch is used for completing the many-to-one or one-to-one gating of the multi-channel acquisition unit channel and the main buffer area channel;
the main buffer area is used for buffering trace data of each channel of the main buffer area, wherein a first main buffer area channel and a second main buffer area channel are called as kernel instruction buffer area channels, and a third main buffer area channel to an Nth main buffer area channel are called as peripheral instruction buffer area channels;
the multiplexer is used for completing the many-to-one gating from the main buffer area channel to the output channel;
and the arbiter completes the channel queue scheduling of the main buffer area and completes the channel selection arbitration of the multi-path selector.
The number of the multi-channel acquisition units is more than or equal to the number of trace events which occur in parallel.
The number of the channels of the main buffer area is configured according to the bandwidth requirement and the concurrent number of the trace events, and is less than or equal to the number of the channels of the multi-channel acquisition unit.
Another object of the present invention is to provide a method for scheduling a multi-channel arbitration circuit of an online emulation debugger, the method comprising the following sequential steps:
(1) when the dispatching is initial, the service priority of each channel is configured the same, and a Round-Robin dispatching algorithm is adopted to complete a dispatching task;
(2) when the state of the main buffer area channel enters an emergency state from a holding state, the arbiter raises the priority of the main buffer area channel, changes a scheduling strategy and adopts a Funnel scheduling algorithm to complete a scheduling task;
(3) reading N data from a main buffer channel by a Funnel scheduling algorithm each time, observing the state of the channel after reading, and reading the N data again if the channel is still in an emergency state or a holding state until the channel state enters an accumulation state from the holding state;
(4) when the channel state of the main buffer area enters an accumulation state from a holding state, the scheduling strategy is changed, the priority of the channel is reduced, and a Round-Robin scheduling algorithm is recovered to finish scheduling tasks until the channel state enters an emergency state from the holding state again.
In the step (3), when the channel state of the kernel instruction buffer enters an emergency state, the arbiter gates the kernel instruction buffer channel and sequentially reads a segment of data, and then the arbiter determines the channel state of the kernel instruction buffer channel, and if the channel state of the kernel instruction buffer is still in the emergency state or in a holding state, the arbiter continues to read a segment of data and then performs arbitration again.
In the step (4), when the kernel instruction buffer area channel enters the accumulation state from the retention state, the priority of the channel is set to be the highest, the arbiter gates each channel in sequence, switches the channel after reading out a section of data each time, and arbitrates the channel state of the kernel instruction buffer area; if the channel state of the peripheral instruction buffer area is still in an accumulation state or a holding state, the scheduling strategy is kept unchanged until the channel state of the kernel instruction buffer area enters an emergency state.
According to the technical scheme, the invention has the advantages that: firstly, the invention effectively reduces the data loss times of the acquisition channel and improves the online data tracking capability of the Trace simulation debugger; secondly, compared with the existing scheduling strategy and arbitration method, the method has better multi-channel adaptability, can complete adaptive scheduling strategy adjustment according to different buffer channel states, and adopts a non-cost-exhaustive scheduling mode to enable each channel to obtain response; thirdly, compared with other scheduling strategies and arbitration methods, the method can restore the system operating environment more accurately.
Drawings
FIG. 1 is a block circuit diagram of the present invention;
FIG. 2 is a schematic diagram of a 7-channel based K-K buffer structure;
fig. 3 is a schematic diagram of the states of the synchronization FIFO.
Detailed Description
As shown in fig. 1, a multi-channel arbitration circuit of an online emulation debugger comprises:
the multi-channel acquisition unit 3 is used for acquiring trace events of the kernel instruction buffer channel and the peripheral instruction buffer channel, and classifying each trace event according to the attribute, the property and the source of the event so as to represent the type of the currently acquired trace event; in addition, the multi-channel acquisition unit 3 also needs to deal with the problem of inconsistency of the core clock, the peripheral clock and the acquisition clock. The use of a buffer circuit with an asynchronous FIFO or other clock domain crossing processing circuit is one solution to this problem. The number of the multi-channel acquisition units 3 is more than or equal to the number of trace events which occur in parallel. The specific number of channels of the multi-channel acquisition unit 3 is configurable, but at least can not be less than the number of trace events occurring in parallel.
The cross switch 4 completes the many-to-one or one-to-one gating of the multi-channel acquisition unit 3 channel and the main buffer area 5 channel;
the main buffer area 5 is used for buffering trace data of each channel of the main buffer area 5, wherein a first main buffer area channel and a second main buffer area channel are called as kernel instruction buffer area channels, and a third main buffer area channel to an Nth main buffer area channel are called as peripheral instruction buffer area channels; the use of a buffer with a synchronous FIFO buffer structure circuit or other buffer structure circuit is one main buffer 5 implementation. The number of channels of the main buffer 5 is configured according to the bandwidth requirement and the concurrent number of trace events, but the maximum number of channels should not be more than the number of channels of the acquisition unit. The structure of K acquisition unit channels corresponding to N main buffer channels is called a K-N blocking buffer structure. When the number of the channels of the acquisition units is the same as that of the channels of the main buffer area 5, trace data of the acquisition units can enter the main buffer area 5 without blocking, so that a K-K blocking-free buffer structure is formed. The number of the channels of the main buffer area 5 is configured according to the bandwidth requirement and the concurrent number of the trace events, and is less than or equal to the number of the channels of the multi-channel acquisition unit 3.
The multiplexer 6 completes the many-to-one gating from the channel of the main buffer area 5 to the output channel;
and the arbiter completes the channel queue scheduling of the main buffer 5 and completes the channel selection arbitration of the multiplexer 6. The scheduling method considers the buffer overflow risk as much as possible and reduces the data overflow risk of the trace buffer channel. The main buffer 5 states are classified, and the arbitration circuit realizes different channel scheduling methods according to different main buffer 5 channel states. Generally, the kernel trace event has the largest information amount and the largest times, and the scheduling method should serve the channel as preferentially as possible.
The method comprises the following steps in sequence:
(1) when the dispatching is initial, the service priority of each channel is configured the same, and a Round-Robin dispatching algorithm is adopted to complete a dispatching task;
(2) when the channel state of the main buffer 5 enters an emergency state from a holding state, the arbiter raises the priority of the channel of the main buffer 5, changes a scheduling strategy and adopts a fuel scheduling algorithm to complete a scheduling task;
(3) reading N data from a main buffer 5 channel by a Funnel scheduling algorithm each time, observing the channel state after reading, and reading the N data again if the channel state is still in an emergency state or a holding state until the channel state enters an accumulation state from the holding state;
(4) when the channel state of the main buffer 5 enters an accumulation state from a holding state, the scheduling strategy is changed, the priority of the channel is reduced, and a Round-Robin scheduling algorithm is recovered to complete a scheduling task until the channel state enters an emergency state from the holding state again.
In the step (3), when the channel state of the kernel instruction buffer enters an emergency state, the arbiter gates the kernel instruction buffer channel and sequentially reads a segment of data, and then the arbiter determines the channel state of the kernel instruction buffer channel, and if the channel state of the kernel instruction buffer is still in the emergency state or in a holding state, the arbiter continues to read a segment of data and then performs arbitration again.
In the step (4), when the kernel instruction buffer area channel enters the accumulation state from the retention state, the priority of the channel is set to be the highest, the arbiter gates each channel in sequence, switches the channel after reading out a section of data each time, and arbitrates the channel state of the kernel instruction buffer area; if the channel state of the peripheral instruction buffer area is still in an accumulation state or a holding state, the scheduling strategy is kept unchanged until the channel state of the kernel instruction buffer area enters an emergency state.
For the same trace simulation debugger structure, under the condition of the same clock frequency, the method can achieve fewer data loss times.
As shown in fig. 2, the present embodiment is a multi-channel K-K non-blocking buffer structure based on the scheduling policy and arbitration method. The trace data types collected by each channel are respectively as follows: kernel instructions, kernel data move events, and peripheral data move events. In the embodiment, a plurality of groups of asynchronous FIFO are used for realizing the processing of an acquisition channel and a clock domain crossing; a main buffer area 5 structure is realized by using a plurality of groups of synchronous FIFOs, and data are transmitted between the synchronous FIFOs and the asynchronous FIFOs in a direct connection mode; except the kernel instruction channel, other channels are gated in a mode of cascading two stages of multiplexers 6; the kernel instruction channel can be output only by the first-level multiplexer 6, so that the kernel instruction channel has a high-level priority on a hardware architecture, and the gating speed of the instruction channel is increased; the arbiter will complete the channel scheduling policy and arbitration according to the status of each channel synchronization FIFO.
As shown in fig. 3, the asynchronous FIFO collects the source type of trace information and adds the corresponding trace information. The data enters the synchronous FIFO from the asynchronous FIFO and is added with the time stamp information, so that the data width of the synchronous FIFO is larger than that of the asynchronous FIFO. Defining that when the current data depth of the synchronous FIFO is more than a certain value, the channel 5 of the main buffer enters an emergency state; when the current depth of the synchronous FIFO is smaller than a certain value, the channel 5 of the main buffer enters an accumulation state; when the synchronization FIFO current depth is within a certain period of time, the main buffer 5 channel is in hold state. Particularly, when the synchronous FIFO does not have data buffering at present, the channel of the main buffer area 5 is in an empty state; when the synchronization FIFO is currently full of data, the main buffer 5 channel is full.
In summary, the present invention switches different scheduling strategies through different channel states, such as an emergency state and an accumulation state; the method can effectively control the loss of the buffered data, change the exhaustive service mode, ensure that each channel can obtain the arbitration response, further reduce the risk of buffer overflow and reduce the data loss times.
Claims (6)
1. A multi-channel arbitration circuit of an online simulation debugger is characterized in that: the method comprises the following steps:
the multi-channel acquisition unit is used for acquiring trace events of the kernel instruction buffer channel and the peripheral instruction buffer channel, and classifying each trace event according to the attribute, the property and the source of the event so as to represent the type of the currently acquired trace event;
the cross switch is used for completing the many-to-one or one-to-one gating of the multi-channel acquisition unit channel and the main buffer area channel;
the main buffer area is used for buffering trace data of each channel of the main buffer area, wherein a first main buffer area channel and a second main buffer area channel are called as kernel instruction buffer area channels, and a third main buffer area channel to an Nth main buffer area channel are called as peripheral instruction buffer area channels;
when the number of the channels of the acquisition units is the same as that of the channels of the main buffer area, the trace data of the acquisition units enter the main buffer area without blocking to form a K-K blocking-free buffer structure;
the multiplexer is used for completing the many-to-one gating from the main buffer area channel to the output channel;
and the arbiter completes the channel queue scheduling of the main buffer area and completes the channel selection arbitration of the multi-path selector.
2. The multi-channel arbitration circuit of an online emulation debugger of claim 1, wherein: the number of the multi-channel acquisition units is more than or equal to the number of trace events which occur in parallel;
the number of the multi-channel acquisition units is more than or equal to the number of trace events which occur in parallel; the specific channel number of the multi-channel acquisition unit can be configured, and the minimum number is not less than the number of trace events which occur in parallel.
3. The multi-channel arbitration circuit of an online emulation debugger of claim 1, wherein: the number of the channels of the main buffer area is configured according to the bandwidth requirement and the concurrent number of trace events, and is less than or equal to the number of the channels of the multi-channel acquisition unit;
the main buffer area states are classified, and the arbitration circuit realizes different channel scheduling methods according to different main buffer area channel states.
4. The scheduling method of the multi-channel arbitration circuit of the online emulation debugger of any of claims 1 to 3, wherein: the method comprises the following steps in sequence:
(1) when the dispatching is initial, the service priority of each channel is configured the same, and a Round-Robin dispatching algorithm is adopted to complete a dispatching task;
(2) when the state of the main buffer area channel enters an emergency state from a holding state, the arbiter raises the priority of the main buffer area channel, changes a scheduling strategy and adopts a Funnel scheduling algorithm to complete a scheduling task;
(3) reading N data from a main buffer channel by a Funnel scheduling algorithm each time, observing the state of the channel after reading, and reading the N data again if the channel is still in an emergency state or a holding state until the channel state enters an accumulation state from the holding state;
(4) when the channel state of the main buffer area enters an accumulation state from a holding state, changing a scheduling strategy, reducing the priority of the channel, and recovering a Round-Robin scheduling algorithm to finish a scheduling task until the channel state enters an emergency state from the holding state again;
(5) when the kernel instruction buffer area channel enters an accumulation state from a holding state, setting the priority of the channel to be the highest, sequentially gating each channel by an arbiter, switching the channels after reading a section of data each time, and arbitrating the channel state of the kernel instruction buffer area; if the channel state of the peripheral instruction buffer area is still in an accumulation state or a holding state, the scheduling strategy is kept unchanged until the channel state of the kernel instruction buffer area enters an emergency state.
5. The scheduling method of claim 4, wherein: in the step (3), when the channel state of the kernel instruction buffer enters an emergency state, the arbiter gates the kernel instruction buffer channel and sequentially reads a segment of data, and then the arbiter determines the channel state of the kernel instruction buffer channel, and if the channel state of the kernel instruction buffer is still in the emergency state or in a holding state, the arbiter continues to read a segment of data and then performs arbitration again.
6. The scheduling method of claim 4, wherein: in the step (4), when the kernel instruction buffer area channel enters the accumulation state from the retention state, the priority of the channel is set to be the highest, the arbiter gates each channel in sequence, switches the channel after reading out a section of data each time, and arbitrates the channel state of the kernel instruction buffer area; if the channel state of the peripheral instruction buffer area is still in an accumulation state or a holding state, the scheduling strategy is kept unchanged until the channel state of the kernel instruction buffer area enters an emergency state.
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| US20090259457A1 (en) * | 2008-04-14 | 2009-10-15 | Mentor Graphics Corporaton | Trace Routing Network |
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| CN101887382A (en) * | 2010-06-28 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for arbitrating dynamic priority |
| CN102231142A (en) * | 2011-07-21 | 2011-11-02 | 浙江大学 | Multi-channel direct memory access (DMA) controller with arbitrator |
| CN103218326A (en) * | 2013-04-24 | 2013-07-24 | 上海华力创通半导体有限公司 | Comprehensive arbiter device |
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