CN103685116A - Realizing method for carrier synchronization by nonlinear dual-loop structure - Google Patents
Realizing method for carrier synchronization by nonlinear dual-loop structure Download PDFInfo
- Publication number
- CN103685116A CN103685116A CN201210345218.1A CN201210345218A CN103685116A CN 103685116 A CN103685116 A CN 103685116A CN 201210345218 A CN201210345218 A CN 201210345218A CN 103685116 A CN103685116 A CN 103685116A
- Authority
- CN
- China
- Prior art keywords
- steps
- phase
- signal
- value
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention provides a realizing method for carrier synchronization by a nonlinear dual-loop structure and belongs to the technical field of digital communications. The realizing method is characterized in that the carrier synchronization of a system can be quickly realized by using the realizing method based on the direct processing of the phase of a received signal under the condition that code element synchronization is realized by the system. The method comprises the following steps: first, estimating the carrier frequency offset estimated value of the received signal through a carrier frequency offset estimating module, then estimating a carrier phase error through a carrier phase estimating module according to the estimated value, and finally carrying out corresponding regulation on the carrier phase. A simple structure is adopted in the method, and main functional modules are realized through a delay and feedback circuit and an adder, so that the realizing complexity is low. Meanwhile, the method has the characteristics of high synchronous capture speed, stable synchronous tracking and the like, and a contradiction between algorithm performance and realizing cost is well eliminated.
Description
Technical field the present invention relates to a kind of digital demodulation carrier synchronization implementation method, belongs to digital communication technology field.
Background technology M-PSK signal modulation has permanent envelope, power validity advantages of higher, is widely used and the field such as satellite communication, mobile communication.The particularly application of advanced chnnel coding, making to realize reliable communication under low signal-to-noise ratio environment becomes possibility.But this also has higher requirement for whole system, it is exactly one of key technology that will solve that the carrier synchronization under low signal-to-noise ratio realizes technology.
According to the difference of business model, communication system generally can be divided into burst mode communication and communicate by letter with continuous mode.Under burst mode, data frame format is generally comprised of frame head and data division, as shown in Figure 1.Receiving terminal is realized the extraction to carrier information by the synchronous code of frame head, and then realizes the parsing of data portion.And under continuous communiction pattern, data send continuously, middle some unique code words of periodically transmission, for eliminating the problem of phase ambiguity, as shown in Figure 2.Due to the restriction of efficiency of transmission, generally very short for synchronous code sequence, particularly, under burst communication pattern, in limited synchronous code, realize fast synchronous.This has higher requirement to synchronous circuit.
Realize at present during how the synchronous technology of M-PSK signal carrier have, conventional technology has based on phase-locked loop (PLL) structure, as Coase tower ring (Costas) with and improve structure.But there is the defect of phase ambiguity in this structure, although can be by adding the mode of unique code word to eliminate the phenomenon of phase ambiguity under continuous mode.But this structure locking signal time is longer, is not suitable for burst mode communication, and, when signal to noise ratio is lower, the phenomenon (being also cycle-skipping phenomenon) that Coase tower ring (Costas) also there will be carrier phase ambiguities to repeat.For further improving carrier synchronization performance, some new structures are suggested, as synchronous method and the carrier synchronization method based on maximal possibility estimation estimating and compensate based on frequency deviation.But the method proposing at present, some synchronization accuracies are greatly improved, but operand is larger; Some algorithms are simple but estimated accuracy is not high enough.
Summary of the invention the object of the invention is the deficiency for existing carrier wave implementation method, has proposed the MPSK system carrier synchronization realizing method that a kind of non-linear carrier phase based on twin nuclei is estimated.The method has the features such as implementation complexity is low, synchronization accuracy is high, catching range is wide.
The invention is characterized in that the method comprises two signal treatment steps, Nonlinear Transformation in Frequency Offset Estimation and estimating based on carrier phase, described process has following steps successively:
A: after system realizes bit synchronization, search the sampled point of maximum signal to noise ratio in code element as optimum sampling point, the best sample value of adjacent two code elements is obtained to differential phase, then estimate carrier wave frequency deviation by the differential phase of trying to achieve,
Steps A 1: receive signal and be divided into in-phase branch and quadrature branch, be expressed as I (kT) and Q (kT), receive signal X (kT)=I (kT)+jQ (kT), obtain the phase value θ of signal X (kT)
in(kT).
Steps A 2: according to the signal phase of obtaining in steps A 1, utilize difference channel to obtain the differential phase value Δ θ (k) between adjacent two code elements.
Steps A 3: according to upper one constantly, i.e. k-1 frequency deviation estimated value constantly, the differential phase value that steps A 2 is obtained is adjusted.
Steps A 4: steps A 3 is processed to output signal and carry out modulo operation, determine corresponding delivery parameter according to the modulation system of selecting, introduce simultaneously and adjust factor k
1according to actual tests situation, adjust frequency deviation estimated value.
Steps A 5: the frequency deviation of previous step result is estimated to need further to revise, and the method for employing was according to the estimated value in a upper code element moment (k-1), and steps A 4 is revised.
Steps A 6: the frequency deviation estimated value of previous step output is transported to next module, and is saved in buffer, feed back to steps A 3 and steps A 5, for revising next code element frequency offset estimation constantly.
B: this module is exactly to utilize the frequency deviation estimated value Δ f (k) of the reception signal that steps A 5 obtains, and carrier phase deviation is estimated to received signal.
Step B1: phase of received signal value θ
in(k) with a upper moment (k-1) carrier phase error valuation Δ θ
c(k-1) subtract each other, estimate phase error Δ θ
p1(k)
Step B2: the frequency offset estimation obtaining according to steps A 5, the phase error that step B1 is calculated is revised, and draws correction value Δ θ
p2(k)
Step B3: step B2 is processed to output signal Δ θ
p2(k) carry out modulo operation, according to the modulation system of selecting, determine corresponding delivery parameter, such as restituted signal is QPSK, parameter is decided to be 4.Introduce simultaneously and adjust factor k
2according to actual tests situation, adjust phase error estimation and phase error value.
Step B4: according to steps A 5 output frequency deviation estimated signal and a upper moment (k-1) carrier phase error valuation Δ θ
c(k-1) step B3 output signal is revised to outgoing carrier phase error estimation and phase error value Δ θ
c(k).
Step B5: the phase estimation value of previous step output is transported to next module, and is saved in buffer, feed back to steps A 3 and steps A 5, for revising next code element frequency offset estimation constantly.
Step B6: according to step B4 output phase estimated value, to received signal carrier phase θ
in(k) revise, draw actual reception signal carrier phase valuation θ
m(k).
The present invention propose based on outer shroud reaction type symbol synchronization method, there are following several advantages:
1, simple in structure, amount of calculation is less, is easy to use the chips such as FPGA to realize;
2,, owing to directly error being revised according to estimate of error, synchronous seizure is rapid, catching range is wide;
3, synchronization accuracy is high, and synchronous tracking stablized;
4, under continuous mode and burst mode, can obtain better effects;
5, technology maturation has obtained successful Application in product.
Accompanying drawing explanation
Fig. 1 burst mode frame format figure
Fig. 2 continuous mode frame format
Fig. 3 carrier synchronization schematic diagram
Fig. 4 Nonlinear Transformation in Frequency Offset Estimation schematic diagram
Fig. 5 carrier phase estimation principle figure
Embodiment
The present invention is a kind of non-linear twin nuclei Fast carrier synchronization realizing method.Main process divides two parts, and Nonlinear Transformation in Frequency Offset Estimation and carrier phase are estimated, as shown in Figure 3, below the specific implementation process of each functional module are described:
A: after system realizes bit synchronization, search the sampled point of maximum signal to noise ratio in code element as optimum sampling point, the best sample value of adjacent two code elements is obtained to differential phase, then estimate carrier wave frequency deviation by the differential phase of trying to achieve.Schematic diagram is Fig. 4
Steps A 1: receive signal and be divided into in-phase branch and quadrature branch, be expressed as I (kT) and Q (kT), receive signal X (kT)=I (kT)+jQ (kT), obtain the phase value θ of signal X (kT)
in(kT).Now phase value is:
θ
in(kT)＝arg[Q(kT)/I(kT)]＝2∏Δf(k)kT+Φ
mod(kT)+ΔΦ
0(kT)+Φ
n(kT) (1)
Wherein, T is the signal period, and Δ f (k) is transmitting-receiving carrier wave frequency deviation, Φ
mod(kT) be k receiving symbol phase place, ΔΦ
0(kT) be k code element transmitting-receiving carrier wave initial phase difference, Φ
n(kT) be K code element random noise phase place statistic.
Steps A 2: according to the signal phase of obtaining in steps A 1, utilize difference channel to obtain the differential phase value Δ θ (k) between adjacent two code elements.Its Output rusults is:
Δθ(k)＝θ(kT)-θ((k-1)T)＝ΔΦ
mod(k)+Δω(k)+ΔΦ
n(k) (2)
Wherein, Δ ω (k)=2 ∏ Δ f (k), ΔΦ
mod(k)=n (∏/2) (n is integer), ΔΦ
n(k) random noise that is 0 for average.
Steps A 3: adjust according to the upper one differential phase value that (being the k-1 moment) estimation frequency deviation value Δ f (k-1) obtains steps A 2 constantly, obtain estimated value and adjust Δ θ (k) `, adjusting method is:
Δθ(k)`＝Δθ(k)-Δf(k-1) (3)
Steps A 4: steps A 3 is processed to output signal and carry out modulo operation, determine corresponding delivery parameter according to the modulation system of selecting, (such as restituted signal is QPSK, parameter is decided to be 4).Introduce simultaneously and adjust factor k
1according to actual tests situation, adjust frequency deviation estimated value.
Δf`(k)＝(Δθ(k)`mod(∏/M))*k
1 (4)
Steps A 5: the frequency deviation of previous step result is estimated to need further to revise, and the method for employing was according to the estimated value in a upper code element moment (k-1), and steps A 4 is revised.
Δf(k)＝Δf`(k)+Δf(k-1) (5)
Steps A 6: the frequency deviation estimated value of previous step output is transported to next module, and is saved in buffer, feed back to steps A 3 and steps A 5, for revising next code element frequency offset estimation constantly.
B: this module is exactly to utilize the frequency deviation estimated value Δ f (k) of the reception signal that steps A 5 obtains, and carrier phase is estimated to received signal.Principle schematic is as Fig. 5:
Step B1: phase of received signal value θ
in(k) with a upper moment (k-1) carrier phase error valuation Δ θ
c(k-1) subtract each other, estimate phase error Δ θ
p1(k), that is:
Δθ
p1(k)＝θ(k)-Δθ
c(k-1) (6)
Step B2: the frequency offset estimation obtaining according to steps A 5, the phase error that step B1 is calculated is revised, and obtains correction value Δ θ
p2(k), that is:
Δθ
p2(k)＝Δθ
p1(k)-Δf(k) (7)
Step B3: step B2 is processed to output signal and carry out modulo operation, determine corresponding delivery parameter according to the modulation system of selecting, introduce simultaneously and adjust factor k
2according to actual tests situation, adjust phase error estimation and phase error value Δ θ
p3(k).
Δθ
p3(k)＝(Δθ
p2(k)mod(∏/M))*k
2 (8)
Step B4: according to steps A 5 output frequency deviation estimated signal and a upper moment (k-1) carrier phase error valuation Δ θ
c(k-1) step B3 output signal is revised, exported final carrier phase error estimated value.That is:
Δθ
c(k)＝Δθ
p3(k)+Δf(k)+Δθ
c(k-1) (9)
Step B5: the phase estimation value of previous step output is transported to next module, and is saved in buffer, feed back to step B1 and step B4, for revising next code element frequency offset estimation constantly.
Step B6: according to step B4 output phase estimated value, to received signal carrier phase θ
in(k) revise, draw actual reception signal carrier phase valuation θ
m(k), that is:
θ
m(k)＝θ(k)-Δθ
c(k) (10)
Claims (1)
1. realize a method for carrier synchronization, it is characterized in that the method comprises two signal treatment steps, Nonlinear Transformation in Frequency Offset Estimation and estimating based on carrier phase, described process has following steps successively:
A: after system realizes bit synchronization, search the sampled point of maximum signal to noise ratio in code element as optimum sampling point, the best sample value of adjacent two code elements is obtained to differential phase, then estimate carrier wave frequency deviation by the differential phase of trying to achieve:
Steps A 1: receive signal and be divided into in-phase branch and quadrature branch, be expressed as I (kT) and Q (kT), receive signal X (kT)=I (kT)+jQ (kT), obtain the phase value θ of signal X (kT)
in(kT).
Steps A 2: according to the signal phase of obtaining in steps A 1, utilize difference channel to obtain the differential phase value Δ θ (k) between adjacent two code elements.
Steps A 3: according to (being the k-1 moment) frequency deviation estimated value of the upper moment, the differential phase value that steps A 2 is obtained is adjusted.
Steps A 4: steps A 3 is processed to output signal and carry out modulo operation, determine corresponding delivery parameter according to the modulation system of selecting, introduce simultaneously and adjust factor k
1according to actual tests situation, adjust frequency deviation estimated value.
Steps A 5: the frequency deviation of previous step result is estimated to need further to revise, and the method for employing was according to the estimated value in a upper code element moment (k-1), and steps A 4 is revised.
Steps A 6: the frequency deviation estimated value of previous step output is transported to next module, and is saved in buffer, feed back to steps A 3 and steps A 5, for revising next code element frequency offset estimation constantly.
B: this module is exactly to utilize the frequency deviation estimated value Δ f (k) of the reception signal that steps A 5 obtains, and carrier phase deviation is estimated to received signal:
Step B1: phase of received signal value θ
in(k) with a upper moment (k-1) carrier phase error valuation Δ θ
c(k-1) subtract each other, estimate phase error Δ θ
p1(k)
Step B2: the frequency offset estimation obtaining according to steps A 5, the phase error that step B1 is calculated is revised, and draws correction value Δ θ
p2(k)
Step B3: step B2 is processed to output signal Δ θ
p2(k) carry out modulo operation, according to the modulation system of selecting, determine corresponding delivery parameter, such as restituted signal is QPSK, parameter is decided to be 4.Introduce simultaneously and adjust factor k
2according to actual tests situation, adjust phase error estimation and phase error value.
Step B4: according to steps A 5 output frequency deviation estimated signal and a upper moment (k-1) carrier phase error valuation Δ θ
c(k-1) step B3 output signal is revised to outgoing carrier phase error estimation and phase error value Δ θ
c(k).
Step B5: the phase estimation value of previous step output is transported to next module, and is saved in buffer, feed back to steps A 3 and steps A 5, for revising next code element frequency offset estimation constantly.
Step B6: according to step B4 output phase estimated value, to received signal carrier phase θ
in(k) revise, draw actual reception signal carrier phase valuation θ
m(k).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210345218.1A CN103685116A (en) | 2012-09-18 | 2012-09-18 | Realizing method for carrier synchronization by nonlinear dual-loop structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210345218.1A CN103685116A (en) | 2012-09-18 | 2012-09-18 | Realizing method for carrier synchronization by nonlinear dual-loop structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103685116A true CN103685116A (en) | 2014-03-26 |
Family
ID=50321460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210345218.1A Pending CN103685116A (en) | 2012-09-18 | 2012-09-18 | Realizing method for carrier synchronization by nonlinear dual-loop structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103685116A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015149199A1 (en) * | 2014-04-03 | 2015-10-08 | 中兴通讯股份有限公司 | Differential phase-based frequency offset estimation method and apparatus |
| CN105721374A (en) * | 2015-12-22 | 2016-06-29 | 中国电子科技集团公司第五十研究所 | Method for 8PSK vector analysis through carrier wave synchronization |
| CN107342959A (en) * | 2016-04-29 | 2017-11-10 | 财团法人交大思源基金会 | Four-phase shift keying demodulation modulator |
| WO2021042852A1 (en) * | 2019-09-05 | 2021-03-11 | 大唐移动通信设备有限公司 | Deviation elimination and acquisition method and device for carrier phase measurement, and receiver |
| CN112838998A (en) * | 2020-12-30 | 2021-05-25 | 深圳市极致汇仪科技有限公司 | IQ imbalance estimation method and system suitable for single carrier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101626357A (en) * | 2009-09-22 | 2010-01-13 | 北京理工大学 | Carrier synchronization method of MPSK system based on maximum likelihood estimation |
| CN102209058A (en) * | 2011-06-02 | 2011-10-05 | 北京理工大学 | Low density parity check (LDPC)-coding-assisted mary phase-shift keying (MPSK) system carrier synchronization method |
-
2012
- 2012-09-18 CN CN201210345218.1A patent/CN103685116A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101626357A (en) * | 2009-09-22 | 2010-01-13 | 北京理工大学 | Carrier synchronization method of MPSK system based on maximum likelihood estimation |
| CN102209058A (en) * | 2011-06-02 | 2011-10-05 | 北京理工大学 | Low density parity check (LDPC)-coding-assisted mary phase-shift keying (MPSK) system carrier synchronization method |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015149199A1 (en) * | 2014-04-03 | 2015-10-08 | 中兴通讯股份有限公司 | Differential phase-based frequency offset estimation method and apparatus |
| CN105721374A (en) * | 2015-12-22 | 2016-06-29 | 中国电子科技集团公司第五十研究所 | Method for 8PSK vector analysis through carrier wave synchronization |
| CN105721374B (en) * | 2015-12-22 | 2019-08-30 | 中国电子科技集团公司第五十研究所 | Carrier synchronization is used for 8PSK vector analysis method |
| CN107342959A (en) * | 2016-04-29 | 2017-11-10 | 财团法人交大思源基金会 | Four-phase shift keying demodulation modulator |
| CN107342959B (en) * | 2016-04-29 | 2019-09-13 | 财团法人交大思源基金会 | Four-phase shift keying demodulation modulator |
| WO2021042852A1 (en) * | 2019-09-05 | 2021-03-11 | 大唐移动通信设备有限公司 | Deviation elimination and acquisition method and device for carrier phase measurement, and receiver |
| CN112838998A (en) * | 2020-12-30 | 2021-05-25 | 深圳市极致汇仪科技有限公司 | IQ imbalance estimation method and system suitable for single carrier |
| CN112838998B (en) * | 2020-12-30 | 2022-08-12 | 深圳市极致汇仪科技有限公司 | IQ imbalance estimation method and system suitable for single carrier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3200547B2 (en) | CDMA mobile communication system | |
| CN103685116A (en) | Realizing method for carrier synchronization by nonlinear dual-loop structure | |
| CN108494714B (en) | GMSK coherent demodulation method for rapidly overcoming Doppler frequency shift | |
| CN103414674B (en) | A kind of MAPSK adaptive de adjusting system | |
| CN111600823B (en) | Parallel OQPSK offset quadriphase shift keying demodulator | |
| CN104092635B (en) | carrier frequency offset estimation method, carrier compensation method and device | |
| CN111343125A (en) | Synchronization method for 32APSK modulation system receiver | |
| CN104079518A (en) | Polarity diversity reception device and method based on SOQPSK-TG signal | |
| CN110300079A (en) | A kind of msk signal coherent demodulation method and system | |
| US20170288922A1 (en) | Frequency estimation and tracking in a receiver | |
| CN109379314A (en) | High-speed burst digital demodulation method and equipment | |
| CN104378129B (en) | A kind of ground-to-air wideband communication system for unmanned plane | |
| CN113037671A (en) | Low-complexity efficient SOQPSK symbol timing and phase joint synchronization algorithm | |
| JP2009177341A (en) | Radio receiver, and radio reception method | |
| CN109889461B (en) | Low-complexity parallel carrier recovery system and method thereof | |
| CN113364717A (en) | 32APSK soft information calculation method suitable for DVBS2 modulation | |
| CN102316058B (en) | Coherent demodulation device of non-geostationary orbit satellite DQPSK (Differential Quadrature Phase Shift Keying) communication | |
| CN204180063U (en) | A kind of receiving terminal for unmanned plane ground-to-air wideband communication system | |
| CN1305285C (en) | Method and device for realing differential-deviation four-phase key-control coherent demodulation | |
| CN105049172A (en) | Short burst carrier frequency offset estimation method | |
| CN103391269B (en) | The method of 8QAM receiver and extraction local carrier-phase error thereof | |
| CN107070832B (en) | A kind of high dynamic UAV TT & C signal carrier tracking method | |
| CN104378130A (en) | Receiving terminal for unmanned aerial vehicle land-to-air wideband communication system | |
| US20220385391A1 (en) | Systems and methods for signal modulation of a plurality of downlink signal representative of a communication signal | |
| JP2000082976A (en) | Cdma system mobile communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information |
Inventor after: Ma Zhengxin Inventor after: Wang Yuhan Inventor after: Li Gang Inventor after: Zhang Zhen Inventor after: Li Tao Inventor after: Ning Wei Inventor before: Ma Zhengxin Inventor before: Wang Yuhan Inventor before: Li Gang |
|
| COR | Change of bibliographic data | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140326 |