CN103681992A - Semiconductor substrate, semiconductor device and semiconductor substrate manufacturing method - Google Patents
Semiconductor substrate, semiconductor device and semiconductor substrate manufacturing method Download PDFInfo
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- CN103681992A CN103681992A CN201410006568.4A CN201410006568A CN103681992A CN 103681992 A CN103681992 A CN 103681992A CN 201410006568 A CN201410006568 A CN 201410006568A CN 103681992 A CN103681992 A CN 103681992A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 418
- 239000000758 substrate Substances 0.000 title claims abstract description 137
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 28
- 229910002601 GaN Inorganic materials 0.000 claims description 22
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 17
- 238000010276 construction Methods 0.000 claims description 14
- 229910017083 AlN Inorganic materials 0.000 claims description 11
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims description 2
- 102000013275 Somatomedins Human genes 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 150000004678 hydrides Chemical class 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 2
- 238000004857 zone melting Methods 0.000 claims description 2
- 239000002131 composite material Substances 0.000 abstract description 16
- 230000006378 damage Effects 0.000 abstract description 3
- 238000010494 dissociation reaction Methods 0.000 abstract 1
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- 230000015572 biosynthetic process Effects 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910004541 SiN Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000013467 fragmentation Methods 0.000 description 3
- 238000006062 fragmentation reaction Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
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- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
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Abstract
The invention discloses a semiconductor substrate, a semiconductor device and a semiconductor substrate manufacturing method. The semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer which is arranged on the first semiconductor layer, wherein both the first semiconductor layer and the second semiconductor layer are respectively provided with a different dissociation surface in the vertical direction after symmetrically rotating along respective crystal lattice. The semiconductor substrate has a unique crystal lattice structure and a unique mechanical structure, the semiconductor substrate is set as a composite substrate structure, the harm of the stress applied to a semiconductor epitaxial layer on the semiconductor substrate can be reduced under the condition of the same substrate thickness, and the breaking probability of the semiconductor substrate can be reduced; meanwhile, the technological difficulty also can be alleviated, and the reliability of the semiconductor device can be enhanced.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to a kind of Semiconductor substrate, semiconductor device and Semiconductor substrate manufacture method.
Background technology
The III group-III nitride that the gallium nitride of take is representative is more and more subject to people's attention, because III group-III nitride can be widely used as light-emitting diode (LED) and the high power electronic device of semiconductor lighting.Due to the shortage of intrinsic substrate, gallium nitride device is generally prepared in foreign substrate, such as sapphire, carborundum and silicon.Silicon substrate is due to its application widely, and its size and quality are all best in the middle of above-mentioned several backing materials.The mainstream technology of complementary metal oxide semiconductors (CMOS) (CMOS) is exactly the silicon substrate based on 12 cun at present, and the price of silicon is also that other different materials can not be compared.So, on large scale silicon substrate, prepare gallium nitride material, be the optimum method that reduces gallium-nitride-based devices cost.
But, owing to having huge lattice mismatch and thermal mismatching between gallium nitride and silicon, can a large amount of stress of introducing in preparation and cooling process.This stress can cause the warpage of epitaxial wafer and the be full of cracks of epitaxial film, in addition silicon substrate itself is also had to very large injury.Due to stress remaining in silicon substrate, the epitaxy of gallium nitride sector-meeting in technical process on silicon occurs broken, causes huge loss.For fear of this situation, common way is to adopt thick silicon substrate, but processing line all exists a upper limit to the thickness of substrate.After the thickness of silicon substrate surpasses certain critical value, process equipment cannot be processed, and such as mask aligner cannot focus on aligning, technique cannot realize.
Therefore, for above-mentioned technical problem and improve one's methods, be necessary to provide a kind of Semiconductor substrate, semiconductor device and Semiconductor substrate manufacture method.
Summary of the invention
In order to address the above problem, the present invention proposes the concept of a composite substrate structure.As a rule, due to symmetric reason, gallium nitride epitaxial slice is all preferably to prepare on Si (111) substrate, makes the epitaxial film of preparation have good crystal mass, electrical properties and optical property.The lattice structure of gallium nitride has the feature of hexagonal symmetry, also follows same relation in Stress Release.And the face that dissociates of Si (111) also has the feature of triangular symmetrical, silicon substrate is because being triangular symmetrical when being subject to stress and damaging.Due to symmetrical matching relationship, best in quality at the gallium nitride of the upper preparation of Si (111), but corresponding, when being subject to stress, be also hold most breakable.For fear of this situation, the present invention proposes and utilize silicon asymmetric compound substrate to prepare epitaxial layer of gallium nitride.
Stress in Si semiconductor is along with the thickness of the silicon in same crystal orientation increases and constantly accumulation, and when the surface of silicon in same crystal orientation and the silicon in another crystal orientation contact, stress can reduce and can not accumulate.The present invention is by introducing the Si (111) of two-layer or multilayer different crystal orientations, the face that dissociates of Si (111) semiconductor layer that is in contact with one another is not overlapped, thereby reduce stress by the damage of silicon substrate, prevent breaking of gallium nitride semiconductor layers that silicon substrate be full of cracks causes, reach the object that improves gallium nitride semiconductor layers robustness and reliability.
Above-mentioned compound substrate also can by by the silicon semiconductor layer of two kinds of different crystal orientations in conjunction with formation, as by Si (111) semiconductor layer and Si (100) semiconductor layer in conjunction with forming composite substrate structure.Angle during by control wafer bonding, can be so that the face that dissociates of Si (111) semiconductor layer and Si (100) semiconductor layer overlap, so the defect that epitaxial layer of gallium nitride produces will greatly reduce while being delivered in one of them silicon semiconductor layer, thereby avoid being extended to another kind of silicon semiconductor layer, reduce the probability of the substrate fragmentation that the stress of epitaxial layer of gallium nitride causes, strengthened robustness and the reliability of substrate.
The manufacture of above-mentioned compound substrate can complete by the method for bonding chip, for example, two thinner substrates can be carried out to bonding and generate compound substrate according to the different crystal orientation certain angle that staggers.
To achieve these goals, the technical scheme that the embodiment of the present invention provides is as follows:
A kind of Semiconductor substrate, described Semiconductor substrate comprises the first semiconductor layer and is positioned at the second semiconductor layer on described the first semiconductor layer, described the first semiconductor layer and the second semiconductor layer, described the first semiconductor layer by its lattice symmetry rotation after with described the second semiconductor layer, described the first semiconductor layer and described the second semiconductor layer by its lattice symmetry rotation after and described the first semiconductor layer by its lattice symmetry rotation after and described the second semiconductor layer all there is in vertical direction the different faces that dissociates after rotating by its lattice symmetry.
As a further improvement on the present invention, the material of described the first semiconductor layer and the second semiconductor layer is identical or different.
As a further improvement on the present invention, described the first semiconductor layer and the second semiconductor layer have identical lattice structure, and the first semiconductor layer and the second semiconductor layer have identical crystal orientation in vertical direction, crystal orientation in the horizontal direction does not overlap.
As a further improvement on the present invention, described the first semiconductor layer is different with the crystal structure of the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer crystal orientation in the horizontal direction do not overlap.
As a further improvement on the present invention, the material shape of described the first semiconductor layer comprises one or more combination of crystalline state, amorphous state and amorphous state.
As a further improvement on the present invention, described amorphous materials also comprises non-semiconductor material, and described non-semiconductor material comprises aluminium nitride, polycrystal carborundum, pottery and quartzy.
As a further improvement on the present invention, when described the first semiconductor layer is amorphous materials, the bonding direction of the first semiconductor layer and the second semiconductor layer is unrestricted.
As a further improvement on the present invention, described the second semiconductor layer is crystal layer.
As a further improvement on the present invention, described the first semiconductor layer and the second semiconductor layer alternately form three layers or three layers of above stepped construction successively.
As a further improvement on the present invention, described stepped construction comprises the dielectric layer between the first semiconductor layer and/or the second semiconductor layer.
As a further improvement on the present invention, described dielectric layer has identical crystal orientation in vertical direction with adjacent the first semiconductor layer and/or the second semiconductor layer, crystal orientation does not overlap in the horizontal direction.
As a further improvement on the present invention, described dielectric layer is different from the crystal structure of adjacent the first semiconductor layer and/or the second semiconductor layer, and crystal orientation does not overlap in the horizontal direction.
Correspondingly, a kind of semiconductor device, described semiconductor device comprises Semiconductor substrate and is positioned at the semiconductor epitaxial layers in described Semiconductor substrate, described Semiconductor substrate comprises the first semiconductor layer and is positioned at the second semiconductor layer on described the first semiconductor layer, described the first semiconductor layer and the second semiconductor layer, described the first semiconductor layer is rear and described the second semiconductor layer by its lattice symmetry rotation, after described the first semiconductor layer and described the second semiconductor layer rotate by its lattice symmetry, and described the first semiconductor layer all has the different faces that dissociates after rotating by its lattice symmetry with described the second semiconductor layer after by the rotation of its lattice symmetry in vertical direction.
As a further improvement on the present invention, described semiconductor epitaxial layers comprises one or more the combination in silicon, GaAs, gallium nitride, aluminum gallium nitride, indium gallium nitrogen, Al-Ca-In-N.
As a further improvement on the present invention, described semiconductor device comprises light-emitting diode, laser diode, High Electron Mobility Transistor, field-effect transistor, Schottky diode, PIN diode and solar cell.
Correspondingly, a kind of manufacture method of Semiconductor substrate, described method comprises:
S1, provide the first semiconductor layer;
S2, on described the first semiconductor layer, prepare the second semiconductor layer, described the first semiconductor layer and the second semiconductor layer, described the first semiconductor layer by its lattice symmetry rotation after with described the second semiconductor layer, described the first semiconductor layer and described the second semiconductor layer by its lattice symmetry rotation after and described the first semiconductor layer by its lattice symmetry rotation after and described the second semiconductor layer all there is in vertical direction the different faces that dissociates after rotating by its lattice symmetry.
As a further improvement on the present invention, after described step S2, also comprise:
On described the second semiconductor layer, prepare semiconductor epitaxial layers.
As a further improvement on the present invention, the preparation method of described the first semiconductor layer and described the second semiconductor layer comprises one or more the combination in Czochralski method, zone-melting process, physical vapour deposition (PVD) and chemical vapour deposition (CVD).
As a further improvement on the present invention, the method for preparing the second semiconductor layer in described step S2 on described the first semiconductor layer comprises bonding chip.
As a further improvement on the present invention, the preparation method of described semiconductor epitaxial layers comprises one or more the combination in metal-organic chemical vapor deposition equipment, molecular beam epitaxy and hydride gas-phase epitaxy.
As a further improvement on the present invention, after described step S2, also comprise:
On described the second semiconductor layer, alternately prepare successively the first semiconductor layer or the first semiconductor layer and the second semiconductor layer, form three layers or three layers of above stepped construction.
As a further improvement on the present invention, described method also comprises:
Somatomedin layer between the first semiconductor layer and/or the second semiconductor layer.
As a further improvement on the present invention, dielectric layer is made by the method for deposition, thermal oxidation or nitrogenize, and the method for deposition comprises one or more the combination in CVD, PECVD, LPCVD, RTCVD, MOCVD, MBE, ALD.
Semiconductor substrate provided by the invention, semiconductor device and Semiconductor substrate manufacture method make Semiconductor substrate have special lattice structure and mechanical structure, Semiconductor substrate is made as to compound substrat structure, under the condition of same substrate thickness, can reduce the infringement that stress that semiconductor epitaxial layers applies produces silicon substrate, thereby reduce the probability of silicon substrate fragmentation; Can reduce technology difficulty, strengthen the reliability of semiconductor device simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic diagram in each crystal orientation of silicon of relating in the present invention;
Fig. 2 is the first embodiment of the invention <-211> direction Semiconductor substrate structure chart parallel with the <1-10> direction of the Si of lower floor (111) of Si (111) at the middle and upper levels;
Fig. 3 is the <-211> direction Semiconductor substrate structure chart parallel with the <-101> direction of the Si of lower floor (111) of second embodiment of the invention Si (111) at the middle and upper levels;
Fig. 4 (a) is the Semiconductor substrate structure chart that the <-211> direction of third embodiment of the invention Si (111) at the middle and upper levels and the <-211> direction of the Si of lower floor (111) exist a drift angle, and Fig. 4 (b) and Fig. 4 (c) are respectively upper strata Si(111) and the Si(111 of lower floor) vertical view;
Fig. 5 (a) is the Semiconductor substrate structure chart that the <-211> direction of four embodiment of the invention Si (111) at the middle and upper levels and the <-110> direction of the Si of lower floor (100) exist a drift angle, and Fig. 5 (b) and Fig. 5 (c) are respectively upper strata Si(111) and the Si(100 of lower floor) vertical view;
Fig. 6 has Si (111) layer and Si (100) layer of Semiconductor substrate structure chart that replaces composite substrate structure in fifth embodiment of the invention;
Fig. 7 has Si (110) layer and Si (100) layer of Semiconductor substrate structure chart that replaces composite substrate structure in sixth embodiment of the invention;
Fig. 8 has Si (111) layer and Si (110) layer of Semiconductor substrate structure chart that replaces composite substrate structure in seventh embodiment of the invention.
Embodiment
Below with reference to embodiment shown in the drawings, describe the present invention.But these execution modes do not limit the present invention, the conversion in the structure that those of ordinary skill in the art makes according to these execution modes, method or function is all included in protection scope of the present invention.
In addition in different embodiment, may use, label or the sign of repetition.These only repeat, in order simply clearly to narrate the present invention, not represent between discussed different embodiment and/or structure and to have any relevance.
Figure 1 shows that the schematic diagram in each crystal orientation of silicon relating in the present invention, below in conjunction with Fig. 1, for different execution modes, the invention will be further described.
Fig. 2 is the structural representation of Semiconductor substrate in first embodiment of the invention, i.e. the <-211> direction of upper strata Si (111) the Semiconductor substrate structure chart parallel with the <1-10> direction of the Si of lower floor (111).In present embodiment, Semiconductor substrate 1 comprises: the first semiconductor layer 11; The second semiconductor layer 12, the second semiconductor layers 12 that are positioned on the first semiconductor layer 11 can be used for preparing semiconductor epitaxial layers 2.Wherein, the first semiconductor layer 11 and the second semiconductor layer 12 have the different faces that dissociates in vertical direction.
Preferably, the first semiconductor layer 11 can be one or more the combination in semi-conducting material, amorphous materials and crystal, the semi-conducting material that the first semiconductor layer 11 is selected comprises one or more in Si, GaN, AlN, SiC, GaAs, InP, diamond, amorphous materials comprises aluminium nitride, pottery and quartzy etc., when the first semiconductor layer 11 is amorphous materials, the bonding direction of the first semiconductor layer 11 and the second semiconductor layer 12 is unrestricted.
The first semiconductor layer 12 can be crystal layer, the semi-conducting material that the first semiconductor layer 12 is selected comprises one or more in Si, GaN, AlN, SiC, GaAs, InP, diamond, the material of the first semiconductor layer 11 and the second semiconductor layer 12 can be identical or different, but adopt different crystal orientation.As the first semiconductor layer and the second semiconductor layer have identical lattice structure, the first semiconductor layer and the second semiconductor layer have identical crystal orientation in vertical direction, crystal orientation in the horizontal direction does not overlap; Or the first semiconductor layer is different with the crystal structure of the second semiconductor layer, the first semiconductor layer and the second semiconductor layer crystal orientation in the horizontal direction do not overlap.
In present embodiment, the first semiconductor layer 11 and the second semiconductor layer 12 have identical lattice structure Si (111), have in vertical direction identical crystal orientation, but crystal symmetry is in the horizontal direction different.
Above-mentioned semiconductor epitaxial layers 2 can comprise one or more the combination in silicon, GaAs, gallium nitride, aluminum gallium nitride, indium gallium nitrogen, Al-Ca-In-N.When semiconductor epitaxial layers is nitride, can, for making multiple device architecture, comprise light-emitting diode (LED), laser diode, High Electron Mobility Transistor (HEMT), field-effect transistor (FET), Schottky diode, PIN diode and solar cell etc.
In present embodiment, provide the manufacture method of above-mentioned Semiconductor substrate 1 simultaneously, comprised the following steps:
S1, provide the first semiconductor layer 11;
S2, on described the first semiconductor layer 11, prepare the second semiconductor layer 12, the first semiconductor layers 11 and the second semiconductor layer 12 has the different faces that dissociates in vertical direction.
Further, after step S2, also comprise: on the second semiconductor layer 12, prepare semiconductor epitaxial layers 2.
In present embodiment, the first semiconductor layer or the first semiconductor layer and the second semiconductor layer be can also on the second semiconductor layer 12, alternately prepare successively, three layers or three layers of above stepped construction formed.
In present embodiment, the first semiconductor layer 11 and the second semiconductor layer 12 all comprise Si (111) semiconductor layer, wherein, the second semiconductor layer 12 is that the <-211> direction of upper strata Si (111) semiconductor layer and the <1-10> direction of the first semiconductor layer 11Ji Si of lower floor (111) semiconductor layer are parallel to each other.Certainly angle between the <-211> direction of the second semiconductor layer 12 and the <1-10> direction of the first semiconductor layer 11, can be provided with angle in other embodiments, if can be 10 °, 20 ° or 30 ° etc.; The first semiconductor layer 11 and the second semiconductor layer 12 can alternately laminated formation composite constructions, make like this face that dissociates of upper strata Si (111) semiconductor layer and the Si of lower floor (111) semiconductor layer mutually stagger, compare with single silicon semiconductor layer, this method can reduce in upper strata Si (111) semiconductor layer and the Si of lower floor (111) semiconductor layer interface the accumulation of stress, can avoid arriving whole silicon semiconductor layer due to the cumulative stress of silicon semiconductor layer part, cause whole silicon substrate to chap.
Fig. 3 is the structural representation of Semiconductor substrate in second embodiment of the invention, i.e. the <-211> direction of the Si on upper strata (111) the Semiconductor substrate structure chart parallel with the <-101> direction of the Si of lower floor (111).In present embodiment, Semiconductor substrate 1 comprises: the first semiconductor layer 11; The second semiconductor layer 12, the second semiconductor layers 12 that are positioned on the first semiconductor layer 11 can be used for preparing semiconductor epitaxial layers 2.
The first semiconductor layer 11 comprises the Si of lower floor (111) semiconductor layer, the second semiconductor layer 12 comprises Si (111) semiconductor layer on upper strata, and the <-101> direction of the <-211> direction of upper strata Si (111) semiconductor layer and the Si of lower floor (111) layer is parallel to each other.Preferably, the first semiconductor layer 11 and the second semiconductor layer 12 can alternately laminated formation composite constructions.Can guarantee that like this face that dissociates that upper strata Si (111) semiconductor layer and the Si of lower floor (111) semiconductor layer have is not in same direction, thereby avoid the be full of cracks of the silicon substrate that the accumulation of stress causes, can greatly improve the reliability of silicon substrate.
Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c) are the structural representation of Semiconductor substrate in third embodiment of the invention, and the <-211> direction of the <-211> direction of the Si on upper strata (111) and the Si of lower floor (111) exists the Semiconductor substrate structure chart of a drift angle.Wherein, the generalized section that Fig. 4 (a) is this structure, Fig. 4 (b) and Fig. 4 (c) are respectively upper strata Si(111) and the Si(111 of lower floor) vertical view.In present embodiment, Semiconductor substrate 1 comprises: the first semiconductor layer 11; The second semiconductor layer 12, the second semiconductor layers 12 that are positioned on the first semiconductor layer 11 can be used for preparing semiconductor epitaxial layers 2.
The first semiconductor layer 11 comprises the Si of lower floor (111) semiconductor layer, the second semiconductor layer 12 comprises Si (111) semiconductor layer on upper strata, and there is a drift angle in the <-211> direction of the <-211> direction of upper strata Si (111) semiconductor layer and the Si of lower floor (111) layer, the differing in size in the integral multiple of 60 ° or 60 ° of this drift angle.Preferably, the first semiconductor layer 11 and the second semiconductor layer 12 can alternately laminated formation composite constructions.Can guarantee that like this face that dissociates that upper strata Si (111) semiconductor layer and the Si of lower floor (111) semiconductor layer have is not in same direction, thereby avoid the be full of cracks of the silicon substrate that the accumulation of stress causes, can greatly improve the reliability of silicon substrate.
Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c) are the structural representation of Semiconductor substrate in four embodiment of the invention, and the <-110> direction of the <-211> direction of the Si on upper strata (111) and the Si of lower floor (100) exists the Semiconductor substrate structure chart of a drift angle.Wherein, the generalized section that Fig. 5 (a) is this structure, Fig. 5 (b) and Fig. 5 (c) are respectively upper strata Si(111) and the Si(100 of lower floor) vertical view.Semiconductor substrate 1 comprises: the first semiconductor layer 11; The second semiconductor layer 12, the second semiconductor layers 12 that are positioned on the first semiconductor layer 11 can be used for preparing semiconductor epitaxial layers 2.In present embodiment, the first semiconductor layer 11 is different with the crystal structure of the second semiconductor layer 12, and the first semiconductor layer 11 and the second semiconductor layer 12 crystal orientation in the horizontal direction do not overlap.
The first semiconductor layer 11 comprises the Si of lower floor (100) semiconductor layer, the second semiconductor layer 12 comprises Si (111) semiconductor layer on upper strata, and there is a drift angle in the <-110> direction of the <-211> direction of upper strata Si (111) semiconductor layer and the Si of lower floor (100) layer, the differing in size in the integral multiple of 90 ° or 90 ° of this drift angle.Preferably, the first semiconductor layer and the second semiconductor layer can alternately laminated formation composite constructions.Can guarantee that like this face that dissociates that upper strata Si (111) semiconductor layer and the Si of lower floor (100) semiconductor layer have is not in same direction, thereby avoid the be full of cracks of the silicon substrate that the accumulation of stress causes, can greatly improve the reliability of silicon substrate.
Fig. 6 is the structural representation of Semiconductor substrate in fifth embodiment of the invention, has the alternately Semiconductor substrate structure chart of composite substrate structure of Si (111) layer and Si (100) layer.In present embodiment, Semiconductor substrate 1 comprises three layers or three layers of above alternately laminated formation of semiconductor layer, is prepared with semiconductor epitaxial layers 2 in Semiconductor substrate 1.
Wherein, the first semiconductor layer 11 comprises the Si of lower floor (111) semiconductor layer, and the second semiconductor layer 12 comprises Si (100) semiconductor layer on upper strata.Two kinds of stacked composite substrate structures that form Si (111), Si (100), Si (111) and Si (100) of semiconductor layer.This method can guarantee that the face that dissociates that each silicon semiconductor layer has is not in same direction equally, thereby has avoided the be full of cracks of the silicon substrate that the accumulation of stress causes, and can greatly improve the reliability of silicon substrate.
Further, stepped construction also comprises the dielectric layer between the first semiconductor layer and/or the second semiconductor layer, and dielectric layer material comprises SiO
2, SiN, AlN etc.Dielectric layer has identical crystal orientation in vertical direction with adjacent the first semiconductor layer and/or the second semiconductor layer, crystal orientation does not overlap in the horizontal direction; Or dielectric layer is different from the crystal structure of adjacent the first semiconductor layer and/or the second semiconductor layer, and crystal orientation does not overlap in the horizontal direction.On the one hand, dielectric material can be also amorphous state, as the resilient coating of backing material, reduces the accumulation of stress; On the other hand, dielectric material has higher dielectric constant (as SiO
2dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN dielectric constant is 8.5) and critical breakdown electric field, guaranteeing that substrate bears under the prerequisite of enough puncture voltages, the dielectric material that can have adequate thickness, can guarantee the quality of dielectric material, increase robustness and the reliability of backing material.
Fig. 7 is the structural representation of Semiconductor substrate in sixth embodiment of the invention, has the alternately Semiconductor substrate structure chart of composite substrate structure of Si (110) layer and Si (100) layer.In present embodiment, Semiconductor substrate 1 comprises three layers or three layers of above alternately laminated formation of semiconductor layer, is prepared with semiconductor epitaxial layers 2 in Semiconductor substrate 1.
Wherein, the first semiconductor layer 11 comprises the Si of lower floor (110) semiconductor layer, and the second semiconductor layer 12 comprises Si (100) semiconductor layer on upper strata.Two kinds of stacked composite substrate structures that form Si (110), Si (100), Si (110) and Si (100) of semiconductor layer.This method can guarantee that the face that dissociates that each silicon semiconductor layer has is not in same direction equally, thereby has avoided the be full of cracks of the silicon substrate that the accumulation of stress causes, and can greatly improve the reliability of silicon substrate.
Further, stepped construction also comprises the dielectric layer between the first semiconductor layer and/or the second semiconductor layer, and dielectric layer material comprises SiO
2, SiN, AlN etc.Dielectric layer has identical crystal orientation in vertical direction with adjacent the first semiconductor layer and/or the second semiconductor layer, crystal orientation does not overlap in the horizontal direction; Or dielectric layer is different from the crystal structure of adjacent the first semiconductor layer and/or the second semiconductor layer, and crystal orientation does not overlap in the horizontal direction.On the one hand, dielectric material can be used as the resilient coating of backing material, reduces the accumulation of stress; On the other hand, dielectric material has higher dielectric constant (if SiO2 dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN dielectric constant is 8.5), guaranteeing that substrate bears under the prerequisite of enough puncture voltages, the dielectric material that can have adequate thickness, can guarantee the quality of dielectric material, increases robustness and the reliability of backing material.
Fig. 8 is the structural representation of Semiconductor substrate in seventh embodiment of the invention, has the alternately Semiconductor substrate structure chart of composite substrate structure of Si (111) layer and Si (110) layer.In present embodiment, Semiconductor substrate 1 comprises three layers or three layers of above alternately laminated formation of semiconductor layer, is prepared with semiconductor epitaxial layers 2 in Semiconductor substrate 1.
Wherein, the first semiconductor layer 11 comprises the Si of lower floor (111) semiconductor layer, and the second semiconductor layer 12 comprises Si (110) semiconductor layer on upper strata.Two kinds of stacked composite substrate structures that form Si (111), Si (110), Si (111) and Si (110) of semiconductor layer.This method can guarantee that the face that dissociates that each silicon semiconductor layer has is not in same direction equally, thereby has avoided the be full of cracks of the silicon substrate that the accumulation of stress causes, and can greatly improve the reliability of silicon substrate.
Further, stepped construction also comprises the dielectric layer between the first semiconductor layer and/or the second semiconductor layer, and dielectric layer material comprises SiO
2, SiN, AlN etc.Dielectric layer has identical crystal orientation in vertical direction with adjacent the first semiconductor layer and/or the second semiconductor layer, crystal orientation does not overlap in the horizontal direction; Or dielectric layer is different from the crystal structure of adjacent the first semiconductor layer and/or the second semiconductor layer, and crystal orientation does not overlap in the horizontal direction.On the one hand, dielectric material can be also amorphous state, as the resilient coating of backing material, reduces the accumulation of stress; On the other hand, dielectric material has higher dielectric constant (if SiO2 dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN dielectric constant is 8.5) and critical breakdown electric field, guaranteeing that substrate bears under the prerequisite of enough puncture voltages, the dielectric material that can have adequate thickness, can guarantee the quality of dielectric material, increases robustness and the reliability of backing material.
In sum, as long as the first semiconductor layer in substrate and the second semiconductor layer and separately by all thering is in vertical direction the different faces that dissociates after its lattice symmetry rotation, all can reduce in the first semiconductor layer and the second semiconductor layer interface the accumulation of stress, can avoid arriving whole semiconductor layer due to the cumulative stress of the second semiconductor layer part, cause whole substrate to chap.
As can be seen from the above technical solutions, Semiconductor substrate provided by the invention, semiconductor device and Semiconductor substrate manufacture method make Semiconductor substrate have special lattice structure and mechanical structure, Semiconductor substrate is made as to compound substrat structure, under the condition of same substrate thickness, can reduce the infringement that stress that semiconductor epitaxial layers applies produces silicon substrate, thereby reduce the probability of silicon substrate fragmentation; Can reduce technology difficulty, strengthen the reliability of semiconductor device simultaneously.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and in the situation that not deviating from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, is therefore intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in scope.Any Reference numeral in claim should be considered as limiting related claim.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, and the technical scheme in each embodiment also can, through appropriately combined, form other execution modes that it will be appreciated by those skilled in the art that.
Claims (23)
1. a Semiconductor substrate, it is characterized in that, described Semiconductor substrate comprises the first semiconductor layer and is positioned at the second semiconductor layer on described the first semiconductor layer, described the first semiconductor layer and the second semiconductor layer, described the first semiconductor layer is rear and described the second semiconductor layer by its lattice symmetry rotation, after described the first semiconductor layer and described the second semiconductor layer rotate by its lattice symmetry, and described the first semiconductor layer all has the different faces that dissociates after rotating by its lattice symmetry with described the second semiconductor layer after by the rotation of its lattice symmetry in vertical direction.
2. Semiconductor substrate according to claim 1, is characterized in that, the material of described the first semiconductor layer and the second semiconductor layer is identical or different.
3. Semiconductor substrate according to claim 2, it is characterized in that, described the first semiconductor layer and the second semiconductor layer have identical lattice structure, and the first semiconductor layer and the second semiconductor layer have identical crystal orientation in vertical direction, crystal orientation in the horizontal direction does not overlap.
4. Semiconductor substrate according to claim 2, is characterized in that, described the first semiconductor layer is different with the crystal structure of the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer crystal orientation in the horizontal direction do not overlap.
5. Semiconductor substrate according to claim 1, is characterized in that, the material shape of described the first semiconductor layer comprises one or more combination of crystalline state, amorphous state and amorphous state.
6. Semiconductor substrate according to claim 5, is characterized in that, described amorphous materials also comprises non-semiconductor material, and described non-semiconductor material comprises aluminium nitride, polycrystal carborundum, pottery and quartzy.
7. Semiconductor substrate according to claim 5, is characterized in that, when described the first semiconductor layer is amorphous materials, the bonding direction of the first semiconductor layer and the second semiconductor layer is unrestricted.
8. Semiconductor substrate according to claim 1, is characterized in that, described the second semiconductor layer is crystal layer.
9. Semiconductor substrate according to claim 1, is characterized in that, described the first semiconductor layer and the second semiconductor layer alternately form three layers or three layers of above stepped construction successively.
10. Semiconductor substrate according to claim 9, is characterized in that, described stepped construction comprises the dielectric layer between the first semiconductor layer and/or the second semiconductor layer.
11. Semiconductor substrate according to claim 10, is characterized in that, described dielectric layer has identical crystal orientation in vertical direction with adjacent the first semiconductor layer and/or the second semiconductor layer, crystal orientation does not overlap in the horizontal direction.
12. Semiconductor substrate according to claim 10, is characterized in that, described dielectric layer is different from the crystal structure of adjacent the first semiconductor layer and/or the second semiconductor layer, and crystal orientation does not overlap in the horizontal direction.
13. 1 kinds comprise in claim 1～12 semiconductor device of Semiconductor substrate in any one, it is characterized in that, described semiconductor device comprises Semiconductor substrate and is positioned at the semiconductor epitaxial layers in described Semiconductor substrate, described Semiconductor substrate comprises the first semiconductor layer and is positioned at the second semiconductor layer on described the first semiconductor layer, described the first semiconductor layer and the second semiconductor layer, described the first semiconductor layer is rear and described the second semiconductor layer by its lattice symmetry rotation, after described the first semiconductor layer and described the second semiconductor layer rotate by its lattice symmetry, and described the first semiconductor layer all has the different faces that dissociates after rotating by its lattice symmetry with described the second semiconductor layer after by the rotation of its lattice symmetry in vertical direction.
14. semiconductor device according to claim 13, is characterized in that, described semiconductor epitaxial layers comprises one or more the combination in silicon, GaAs, gallium nitride, aluminum gallium nitride, indium gallium nitrogen, Al-Ca-In-N.
15. semiconductor device according to claim 13, is characterized in that, described semiconductor device comprises light-emitting diode, laser diode, High Electron Mobility Transistor, field-effect transistor, Schottky diode, PIN diode and solar cell.
The manufacture method of 16. 1 kinds of Semiconductor substrate as claimed in claim 1, is characterized in that, described method comprises:
S1, provide the first semiconductor layer;
S2, on described the first semiconductor layer, prepare the second semiconductor layer, described the first semiconductor layer and the second semiconductor layer, described the first semiconductor layer by its lattice symmetry rotation after with described the second semiconductor layer, described the first semiconductor layer and described the second semiconductor layer by its lattice symmetry rotation after and described the first semiconductor layer by its lattice symmetry rotation after and described the second semiconductor layer all there is in vertical direction the different faces that dissociates after rotating by its lattice symmetry.
17. manufacture methods according to claim 16, is characterized in that, after described step S2, also comprise:
On described the second semiconductor layer, prepare semiconductor epitaxial layers.
18. manufacture methods according to claim 16, is characterized in that, the preparation method of described the first semiconductor layer and described the second semiconductor layer comprises one or more the combination in Czochralski method, zone-melting process, physical vapour deposition (PVD) and chemical vapour deposition (CVD).
19. manufacture methods according to claim 16, is characterized in that, the method for preparing the second semiconductor layer in described step S2 on described the first semiconductor layer comprises bonding chip.
20. manufacture methods according to claim 16, is characterized in that, the preparation method of described semiconductor epitaxial layers comprises one or more the combination in metal-organic chemical vapor deposition equipment, molecular beam epitaxy and hydride gas-phase epitaxy.
21. manufacture methods according to claim 16, is characterized in that, after described step S2, also comprise:
On described the second semiconductor layer, alternately prepare successively the first semiconductor layer or the first semiconductor layer and the second semiconductor layer, form three layers or three layers of above stepped construction.
22. manufacture methods according to claim 21, is characterized in that, described method also comprises:
Somatomedin layer between the first semiconductor layer and/or the second semiconductor layer.
23. manufacture methods according to claim 22, it is characterized in that, described dielectric layer is made by the method for deposition, thermal oxidation or nitrogenize, and the method for deposition comprises one or more the combination in CVD, PECVD, LPCVD, RTCVD, MOCVD, MBE, ALD.
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| CN201410006568.4A CN103681992A (en) | 2014-01-07 | 2014-01-07 | Semiconductor substrate, semiconductor device and semiconductor substrate manufacturing method |
| JP2016544829A JP2017507478A (en) | 2014-01-07 | 2015-01-07 | Semiconductor substrate, semiconductor device, and method for manufacturing semiconductor substrate |
| SG11201605542RA SG11201605542RA (en) | 2014-01-07 | 2015-01-07 | Semiconductor substrate, semiconductor device and manufacturing method for semiconductor substrate |
| EP15735020.8A EP3093891B1 (en) | 2014-01-07 | 2015-01-07 | Semiconductor substrate, semiconductor device and manufacturing method for semiconductor substrate |
| KR1020167021367A KR20160104723A (en) | 2014-01-07 | 2015-01-07 | Semiconductor substrate, semiconductor device and manufacturing method for semiconductor substrate |
| DK15735020.8T DK3093891T3 (en) | 2014-01-07 | 2015-01-07 | Semiconductor substrate, semiconductor device and method for producing semiconductor substrate |
| PCT/CN2015/070251 WO2015103976A1 (en) | 2014-01-07 | 2015-01-07 | Semiconductor substrate, semiconductor device and manufacturing method for semiconductor substrate |
| US15/201,533 US10249788B2 (en) | 2014-01-07 | 2016-07-04 | Semiconductor substrate, semiconductor device and manufacturing method of semiconductor substrate |
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| EP (1) | EP3093891B1 (en) |
| JP (1) | JP2017507478A (en) |
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| WO2015103976A1 (en) * | 2014-01-07 | 2015-07-16 | 苏州晶湛半导体有限公司 | Semiconductor substrate, semiconductor device and manufacturing method for semiconductor substrate |
| CN114759126A (en) * | 2022-06-13 | 2022-07-15 | 江苏第三代半导体研究院有限公司 | Semiconductor device structure based on nitride single crystal substrate and preparation method thereof |
| CN116779688A (en) * | 2023-07-28 | 2023-09-19 | 合肥安芯睿创半导体有限公司 | Silicon carbide Schottky diode with junction P+ protection groove structure and manufacturing method |
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| WO2017222513A1 (en) * | 2016-06-22 | 2017-12-28 | Intel Corporation | Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors |
| DE102016013540A1 (en) * | 2016-11-14 | 2018-05-17 | 3 - 5 Power Electronics GmbH | III-V semiconductor diode |
| JP6863423B2 (en) * | 2019-08-06 | 2021-04-21 | 信越半導体株式会社 | Substrates for electronic devices and their manufacturing methods |
| WO2023100577A1 (en) * | 2021-12-01 | 2023-06-08 | 信越半導体株式会社 | Substrate for electronic device and production method therefor |
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| US10249788B2 (en) | 2019-04-02 |
| WO2015103976A1 (en) | 2015-07-16 |
| EP3093891B1 (en) | 2019-03-06 |
| KR20160104723A (en) | 2016-09-05 |
| SG11201605542RA (en) | 2016-08-30 |
| EP3093891A1 (en) | 2016-11-16 |
| US20160315220A1 (en) | 2016-10-27 |
| DK3093891T3 (en) | 2019-05-06 |
| EP3093891A4 (en) | 2017-01-25 |
| JP2017507478A (en) | 2017-03-16 |
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