CN112951897A - Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method - Google Patents

Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method Download PDF

Info

Publication number
CN112951897A
CN112951897A CN201911266693.8A CN201911266693A CN112951897A CN 112951897 A CN112951897 A CN 112951897A CN 201911266693 A CN201911266693 A CN 201911266693A CN 112951897 A CN112951897 A CN 112951897A
Authority
CN
China
Prior art keywords
semiconductor layer
semiconductor
layer
substrate
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201911266693.8A
Other languages
Chinese (zh)
Inventor
陈�峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201911266693.8A priority Critical patent/CN112951897A/en
Publication of CN112951897A publication Critical patent/CN112951897A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The invention discloses a semiconductor substrate, a semiconductor device and a semiconductor substrate manufacturing method. The semiconductor substrate has a special lattice structure and a special mechanical structure, is a composite substrate structure, and can reduce the damage of stress applied by a semiconductor epitaxial layer on the semiconductor substrate under the condition of the same substrate thickness, thereby reducing the probability of breaking the semiconductor substrate; meanwhile, the process difficulty can be reduced, and the reliability of the semiconductor device can be enhanced.

Description

Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method
Technical Field
The present invention relates to the field of microelectronic technologies, and in particular, to a semiconductor substrate, a semiconductor device, and a method for manufacturing the semiconductor substrate.
Background
Group iii nitrides, represented by gallium nitride, are gaining increasing attention because of their widespread use as Light Emitting Diodes (LEDs) for semiconductor lighting and as high power electronic devices. Due to the lack of intrinsic substrates, gallium nitride devices are commonly fabricated on foreign substrates such as sapphire, silicon carbide, and silicon. Silicon substrates, because of their wide applicability, are best sized and quality among the several substrate materials mentioned above. The current mainstream technology of Complementary Metal Oxide Semiconductor (CMOS) is based on a 12 inch silicon substrate, and the price of silicon is incomparable with several other materials. Therefore, the preparation of gallium nitride materials on large-size silicon substrates is the best method for reducing the cost of gallium nitride-based devices.
However, due to the large lattice and thermal mismatch between gallium nitride and silicon, a large amount of stress is introduced during fabrication and cooling. This stress causes warpage of the epitaxial wafer and cracking of the epitaxial film, and also causes a great damage to the silicon substrate itself. Due to the residual stress in the silicon substrate, the gan epitaxial wafer on the silicon may be broken during the process, causing a huge loss. To avoid this, it is common practice to use thick silicon substrates, but there is an upper limit to the thickness of the substrate for the process line. When the thickness of the silicon substrate exceeds a certain critical value, the processing equipment cannot process the silicon substrate, for example, the lithography machine cannot focus and align the silicon substrate, and the process cannot be realized.
Therefore, in view of the above technical problems and the improved methods, it is necessary to provide a semiconductor substrate, a semiconductor device and a semiconductor substrate manufacturing method.
Disclosure of Invention
In order to solve the above problems, the present invention proposes a concept of a composite substrate structure. Generally, for symmetry reasons, it is desirable to fabricate gan epitaxial wafers on Si (111) substrates so that the resulting epitaxial films have good crystal quality, electrical and optical properties. The lattice structure of gallium nitride has the characteristic of hexagonal symmetry, and the same relation is also followed when stress is released. The dissociation plane of Si (111) is also characterized by triangular symmetry, and the silicon substrate is triangular symmetrical when damaged by stress. Due to the symmetrical matching relationship, the gallium nitride crystals produced on Si (111) are the best quality, but correspondingly, are the most brittle when stressed. To avoid this, the invention proposes to prepare an epitaxial layer of gallium nitride using a silicon asymmetric composite substrate.
Stress in a silicon semiconductor is accumulated as the thickness of silicon of the same crystal orientation increases, and when the surface of silicon of the same crystal orientation is in contact with silicon of another crystal orientation, the stress is reduced without accumulation. The invention introduces two or more layers of Si (111) with different crystal orientations, so that the dissociation planes of the Si (111) semiconductor layers which are mutually contacted are not overlapped, thereby reducing the damage of stress through a silicon substrate, preventing the cracking of a gallium nitride semiconductor layer caused by the cracking of the silicon substrate and achieving the aim of improving the firmness and the reliability of the gallium nitride semiconductor layer.
The composite substrate can also be formed by combining two silicon semiconductor layers with different crystal orientations, such as combining a Si (111) semiconductor layer and a Si (100) semiconductor layer to form a composite substrate structure. By controlling the angle of the silicon wafer bonding, the dissociation planes of the Si (111) semiconductor layer and the Si (100) semiconductor layer are not coincident, so that the defects generated by the gallium nitride epitaxial layer are greatly reduced when being transmitted to one silicon semiconductor layer, the defects are prevented from being transmitted to the other silicon semiconductor layer, the probability of substrate breakage caused by the stress of the gallium nitride epitaxial layer is reduced, and the firmness and the reliability of the substrate are enhanced.
The composite substrate can be manufactured by wafer bonding, for example, two thin substrates can be bonded by shifting different crystal directions at a certain angle to generate the composite substrate.
In order to achieve the above purpose, the technical solutions provided by the embodiments of the present invention are as follows:
a semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different dissociation planes in the vertical direction after the first semiconductor layer rotates according to the lattice symmetry of the first semiconductor layer and the second semiconductor layer, and after the first semiconductor layer rotates according to the lattice symmetry of the first semiconductor layer and the second semiconductor layer rotates according to the lattice symmetry of the second semiconductor layer.
As a further improvement of the present invention, the materials of the first semiconductor layer and the second semiconductor layer are the same or different.
As a further improvement of the present invention, the first semiconductor layer and the second semiconductor layer have the same lattice structure, and the first semiconductor layer and the second semiconductor layer have the same crystal orientation in the vertical direction and do not overlap in the horizontal direction.
As a further improvement of the present invention, the first semiconductor layer and the second semiconductor layer have different crystal structures, and the first semiconductor layer and the second semiconductor layer do not overlap with each other in the horizontal direction.
As a further improvement of the present invention, the material morphology of the first semiconductor layer includes one or a combination of more of crystalline state, amorphous state and amorphous state. As a further refinement of the invention, the amorphous material further comprises a non-semiconductor material including aluminum nitride, polycrystalline silicon carbide, ceramics and quartz.
As a further improvement of the present invention, when the first semiconductor layer is an amorphous material, the bonding direction of the first semiconductor layer and the second semiconductor layer is not limited.
As a further improvement of the present invention, the second semiconductor layer is a crystal layer.
As a further improvement of the present invention, the first semiconductor layer and the second semiconductor layer are sequentially and alternately formed into a three-layer or more stacked structure.
As a further development of the invention, the laminated structure comprises a dielectric layer between the first semiconductor layer and/or the second semiconductor layer.
As a further improvement of the present invention, the dielectric layer and the adjacent first semiconductor layer and/or second semiconductor layer have the same crystal orientation in the vertical direction and are not aligned in the horizontal direction.
As a further improvement of the present invention, the dielectric layer has a different crystal structure from the adjacent first semiconductor layer and/or second semiconductor layer, and the crystal orientation is not coincident in the horizontal direction.
Correspondingly, the semiconductor device comprises a semiconductor substrate and a semiconductor epitaxial layer located on the semiconductor substrate, wherein the semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer, after rotating according to the lattice symmetry of the first semiconductor layer, have different dissociation planes in the vertical direction with the second semiconductor layer, after rotating according to the lattice symmetry of the first semiconductor layer, and after rotating according to the lattice symmetry of the first semiconductor layer, and after rotating according to the lattice symmetry of the second semiconductor layer, the first semiconductor layer and the second semiconductor layer have different dissociation planes in the vertical direction.
As a further improvement of the invention, the semiconductor epitaxial layer comprises one or more of silicon, gallium arsenide, gallium nitride, aluminum gallium nitride, indium gallium nitride and aluminum gallium indium nitride.
As a further improvement of the present invention, the semiconductor device includes a light emitting diode, a laser diode, a high electron mobility transistor, a field effect transistor, a schottky diode, a PIN diode, and a solar cell.
Accordingly, a method of manufacturing a semiconductor substrate, the method comprising:
s1, providing a first semiconductor layer;
s2, preparing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different planes of dissociation in the vertical direction after the first semiconductor layer is rotated according to its lattice symmetry and the second semiconductor layer, after the first semiconductor layer is rotated according to its lattice symmetry and the second semiconductor layer is rotated according to its lattice symmetry.
As a further improvement of the present invention, after the step S2, the method further includes:
and preparing a semiconductor epitaxial layer on the second semiconductor layer.
As a further improvement of the present invention, the method for preparing the first semiconductor layer and the second semiconductor layer comprises one or more of czochralski method, floating zone method, physical vapor deposition and chemical vapor deposition.
As a further improvement of the present invention, the method for preparing the second semiconductor layer on the first semiconductor layer in the step S2 includes wafer bonding.
As a further improvement of the invention, the preparation method of the semiconductor epitaxial layer comprises one or more of metal organic chemical vapor deposition, molecular beam epitaxy and hydride vapor phase epitaxy.
As a further improvement of the present invention, after the step S2, the method further includes:
and sequentially and alternately preparing a first semiconductor layer or a first semiconductor layer and a second semiconductor layer on the second semiconductor layer to form a laminated structure with three or more layers.
As a further improvement of the present invention, the method further comprises:
and growing a dielectric layer between the first semiconductor layer and/or the second semiconductor layer.
As a further improvement of the invention, the dielectric layer is formed by deposition, thermal oxidation or nitridation, and the deposition method comprises one or more of CVD, PECVD, LPCVD, RTCVD, MOCVD, MBE and ALD.
The semiconductor substrate, the semiconductor device and the manufacturing method of the semiconductor substrate provided by the invention have the advantages that the semiconductor substrate has a special lattice structure and a special mechanical structure, the semiconductor substrate is set to be a composite substrate structure, and under the condition of the same substrate thickness, the damage of stress applied by a semiconductor epitaxial layer to a silicon substrate can be reduced, so that the probability of breakage of the silicon substrate is reduced; meanwhile, the process difficulty can be reduced, and the reliability of the semiconductor device can be enhanced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic representation of the various crystal orientations of silicon involved in the present invention;
FIG. 2 is a view showing a structure of a semiconductor substrate in which the < -211> direction of the upper layer Si (111) and the <1-10> direction of the lower layer Si (111) are parallel in the first embodiment of the present invention;
FIG. 3 is a view showing a structure of a semiconductor substrate in which the < -211> direction of the upper Si (111) layer and the < -101> direction of the lower Si (111) layer are parallel to each other in a second embodiment of the present invention;
FIG. 4(a) is a diagram showing a structure of a semiconductor substrate in which the < -211> direction of the upper Si (111) layer and the < -211> direction of the lower Si (111) layer are inclined at an angle in a third embodiment of the present invention, and FIG. 4(b)) and FIG. 4(c) are top views of the upper Si (111) layer and the lower Si (111) layer, respectively;
FIG. 5(a) is a diagram showing a structure of a semiconductor substrate in which the < -211> direction of the upper Si (111) layer and the < -110> direction of the lower Si (100) layer are inclined at an angle in accordance with a fourth embodiment of the present invention, and FIGS. 5(b) and 5(c) are top views of the upper Si (111) layer and the lower Si (100) layer, respectively;
FIG. 6 is a view showing a structure of a semiconductor substrate having a structure of an alternate composite substrate of Si (111) layer and Si (100) layer in a fifth embodiment of the present invention;
FIG. 7 is a view showing a structure of a semiconductor substrate having a structure of an alternate composite substrate of Si (110) layer and Si (100) layer in a sixth embodiment of the present invention;
fig. 8 is a structural view of a semiconductor substrate having a structure of an alternate composite substrate of Si (111) layer and Si (110) layer in the seventh embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely for simplicity and clarity of describing the present invention, and are not intended to represent any correlation between the various embodiments and/or structures discussed.
Fig. 1 shows a schematic view of the various crystal orientations of silicon involved in the present invention, and the present invention is further described below with respect to various embodiments in conjunction with fig. 1.
FIG. 2 is a schematic view showing the structure of a semiconductor substrate in the first embodiment of the present invention, i.e., a structure of a semiconductor substrate in which the < -211> direction of the upper layer Si (111) and the <1-10> direction of the lower layer Si (111) are parallel. In the present embodiment, the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, wherein the second semiconductor layer 12 can be used to prepare the semiconductor epitaxial layer 2. Wherein the first semiconductor layer 11 and the second semiconductor layer 12 have different planes of dissociation in the vertical direction.
Preferably, the first semiconductor layer 11 may be a combination of one or more of a semiconductor material, an amorphous material and a crystal, the semiconductor material selected for the first semiconductor layer 11 includes one or more of Si, GaN, AlN, SiC, GaAs, InP, diamond, the amorphous material includes aluminum nitride, ceramic, quartz, and the like, when the first semiconductor layer 11 is the amorphous material,
the bonding direction of the first semiconductor layer 11 and the second semiconductor layer 12 is not limited.
The first semiconductor layer 12 may be a crystal layer, the semiconductor material selected for the first semiconductor layer 12 includes one or more of Si, GaN, AlN, SiC, GaAs, InP, and diamond, and the materials of the first semiconductor layer 11 and the second semiconductor layer 12 may be the same or different, but adopt different crystal orientations. If the first semiconductor layer and the second semiconductor layer have the same lattice structure, the first semiconductor layer and the second semiconductor layer have the same crystal orientation in the vertical direction and do not coincide with each other in the horizontal direction; or the first semiconductor layer and the second semiconductor layer have different crystal structures, and the crystal directions of the first semiconductor layer and the second semiconductor layer in the horizontal direction are not overlapped.
In this embodiment, the first semiconductor layer 11 and the second semiconductor layer 12 have the same lattice structure Si (111) and have the same crystal orientation in the vertical direction, but have different crystal symmetries in the horizontal direction.
The semiconductor epitaxial layer 2 may include one or a combination of silicon, gallium arsenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum gallium indium nitride. When the semiconductor epitaxial layer is nitride, the epitaxial layer can be used for manufacturing various device structures, including Light Emitting Diodes (LEDs), laser diodes, High Electron Mobility Transistors (HEMTs), Field Effect Transistors (FETs), Schottky diodes, PIN diodes, solar cells and the like.
In this embodiment, a method for manufacturing the semiconductor substrate 1 is also provided, which includes:
s1, providing a first semiconductor layer 11;
s2, preparing a second semiconductor layer 12 on the first semiconductor layer 11, wherein the first semiconductor layer 11 and the second semiconductor layer 12 have different planes of dissociation in the vertical direction.
Further, step S2 is followed by: a semiconductor epitaxial layer 2 is prepared on the second semiconductor layer 12.
In this embodiment mode, the first semiconductor layer, or the first semiconductor layer and the second semiconductor layer may be alternately formed in this order on the second semiconductor layer 12 to form a three-layer or more-layer stacked structure.
In this embodiment, the first semiconductor layer 11 and the second semiconductor layer 12 both include Si (111) semiconductor layers, and the < -211> direction of the second semiconductor layer 12, i.e., the upper Si (111) semiconductor layer, and the <1-10> direction of the first semiconductor layer 11, i.e., the lower Si (111) semiconductor layer are parallel to each other. Of course, in other embodiments, an included angle may be set between the < -211> direction of the second semiconductor layer 12 and the <1-10> direction of the first semiconductor layer 11, for example, the included angle may be 10 °, 20 °, 30 °, or the like; the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately stacked to form a composite structure such that the planes of dissociation of the upper layer Si (111) semiconductor layer and the lower layer Si (111) semiconductor layer are staggered from each other, which can reduce the accumulation of stress at the interface of the upper layer Si (111) semiconductor layer and the lower layer Si (111) semiconductor layer and can prevent the entire silicon substrate from being cracked due to the accumulation of stress locally in the silicon semiconductor layer to the entire silicon semiconductor layer, as compared with a single silicon semiconductor layer.
FIG. 3 is a schematic view of the structure of a semiconductor substrate according to a second embodiment of the present invention, i.e., a structure of a semiconductor substrate in which the < -211> direction of Si (111) in the upper layer and the < -101> direction of Si (111) in the lower layer are parallel. In the present embodiment, the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, wherein the second semiconductor layer 12 can be used to prepare the semiconductor epitaxial layer 2.
The first semiconductor layer 11 includes a lower Si (111) semiconductor layer, the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the < -211> direction of the upper Si (111) semiconductor layer and the < -101> direction of the lower Si (111) layer are parallel to each other. Preferably, the first semiconductor layers 11 and the second semiconductor layers 12 may be alternately stacked to form a composite structure. Thus, the upper layer Si (111) semiconductor layer and the lower layer Si (111) semiconductor layer are ensured to have dissociation planes which are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress and greatly improving the reliability of the silicon substrate. FIG. 4(a), FIG. 4(b) and FIG. 4(c) are schematic structural diagrams of a semiconductor substrate according to a third embodiment of the present invention, in which the < -211> direction of the upper Si (111) layer and the < -211> direction of the lower Si (111) layer have an off-angle therebetween. Fig. 4(a) is a schematic cross-sectional view of the structure, and fig. 4(b) and 4(c) are plan views of the upper layer Si (111) and the lower layer Si (111), respectively. In the present embodiment, the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, wherein the second semiconductor layer 12 can be used to prepare the semiconductor epitaxial layer 2.
The first semiconductor layer 11 includes a lower Si (111) semiconductor layer, the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and there is an offset angle between the < -211> direction of the upper Si (111) semiconductor layer and the < -211> direction of the lower Si (111) layer, and the magnitude of the offset angle is not equal to 60 DEG or an integral multiple of 60 deg. Preferably, the first semiconductor layers 11 and the second semiconductor layers 12 may be alternately stacked to form a composite structure. Thus, the upper layer Si (111) semiconductor layer and the lower layer Si (111) semiconductor layer are ensured to have dissociation planes which are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress and greatly improving the reliability of the silicon substrate.
FIG. 5(a), FIG. 5(b) and FIG. 5(c) are schematic structural diagrams of a semiconductor substrate according to a fourth embodiment of the present invention, i.e., a structure of a semiconductor substrate in which the < -211> direction of the upper Si (111) layer and the < -110> direction of the lower Si (100) layer have an off-angle. Fig. 5(a) is a schematic cross-sectional view of the structure, and fig. 5(b) and 5(c) are plan views of the upper layer Si (111) and the lower layer Si (100), respectively. The semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, wherein the second semiconductor layer 12 can be used to prepare the semiconductor epitaxial layer 2. In this embodiment, the first semiconductor layer 11 and the second semiconductor layer 12 have different crystal structures, and the first semiconductor layer 11 and the second semiconductor layer 12 do not overlap in the horizontal direction.
The first semiconductor layer 11 comprises a lower Si (100) semiconductor layer, the second semiconductor layer 12 comprises an upper Si (111) semiconductor layer, and the < -211> direction of the upper Si (111) semiconductor layer and the < -110> direction of the lower Si (100) layer have an offset angle, and the size of the offset angle is not equal to 90 degrees or integral multiple of 90 degrees. Preferably, the first semiconductor layer and the second semiconductor layer may be alternately stacked to form a composite structure. Thus, the upper layer Si (111) semiconductor layer and the lower layer Si (100) semiconductor layer are ensured to have dissociation planes which are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress and greatly improving the reliability of the silicon substrate.
Fig. 6 is a schematic structural view of a semiconductor substrate in a fifth embodiment of the present invention, and is a structural view of a semiconductor substrate having a structure in which Si (111) layers and Si (100) layers are alternately combined. In this embodiment, the semiconductor substrate 1 includes three or more semiconductor layers alternately stacked, and the semiconductor epitaxial layers 2 are formed on the semiconductor substrate 1.
The first semiconductor layer 11 includes a lower Si (111) semiconductor layer, and the second semiconductor layer 12 includes an upper Si (100) semiconductor layer. Two semiconductor layers are stacked to form a composite substrate structure of Si (111), Si (100), Si (111), and Si (100). The method can also ensure that the dissociation planes of all the silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress and greatly improving the reliability of the silicon substrate.
Furthermore, the laminated structure also comprises a dielectric layer positioned between the first semiconductor layer and/or the second semiconductor layer, and the material of the dielectric layer comprises SiO2SiN, AlN, etc. The dielectric layer and the adjacent first semiconductor layer and/or second semiconductor layer have the same crystal orientation in the vertical direction and do not coincide in the horizontal direction; or a dielectric layer and an adjacent firstThe crystal structures of the semiconductor layer and/or the second semiconductor layer are different and do not coincide in the horizontal direction. On one hand, the dielectric material can also be in an amorphous state and used as a buffer layer of the substrate material to reduce the accumulation of stress; on the other hand, dielectric materials have a relatively high dielectric constant (e.g., SiO)2Dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN dielectric constant is 8.5) and critical breakdown electric field, and on the premise of ensuring that the substrate bears sufficient breakdown voltage, the substrate can possess a dielectric material with sufficient thickness, the quality of the dielectric material can be ensured, and the robustness and reliability of the substrate material can be increased.
Fig. 7 is a schematic structural view of a semiconductor substrate in a sixth embodiment of the present invention, which is a structural view of a semiconductor substrate having a structure in which Si (110) layers and Si (100) layers are alternately combined. In this embodiment, the semiconductor substrate 1 includes three or more semiconductor layers alternately stacked, and the semiconductor epitaxial layers 2 are formed on the semiconductor substrate 1.
Wherein the first semiconductor layer 11 includes a lower Si (110) semiconductor layer, and the second semiconductor layer 12 includes an upper Si (100) semiconductor layer. Two semiconductor layers are stacked to form a composite substrate structure of Si (110), Si (100), Si (110) and Si (100). The method can also ensure that the dissociation planes of all the silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress and greatly improving the reliability of the silicon substrate.
Furthermore, the laminated structure also comprises a dielectric layer positioned between the first semiconductor layer and/or the second semiconductor layer, and the material of the dielectric layer comprises SiO2SiN, AlN, etc. The dielectric layer and the adjacent first semiconductor layer and/or second semiconductor layer have the same crystal orientation in the vertical direction and do not coincide in the horizontal direction; or the dielectric layer and the adjacent first semiconductor layer and/or second semiconductor layer have different crystal structures and do not coincide in the horizontal direction.
On one hand, the dielectric material can be used as a buffer layer of the substrate material, so that the accumulation of stress is reduced; on the other hand, the dielectric material has a high dielectric constant (e.g. SiO2 dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN dielectric constant is 8.5,) and can have a sufficient thickness under the premise of ensuring that the substrate can bear a sufficient breakdown voltage, thereby ensuring the quality of the dielectric material and increasing the robustness and reliability of the substrate material.
Fig. 8 is a schematic structural view of a semiconductor substrate in a seventh embodiment of the present invention, a structural view of the semiconductor substrate having a structure in which Si (111) layers and Si (110) layers are alternately combined. In this embodiment, the semiconductor substrate 1 includes three or more semiconductor layers alternately stacked, and the semiconductor epitaxial layers 2 are formed on the semiconductor substrate 1.
The first semiconductor layer 11 includes a lower Si (111) semiconductor layer, and the second semiconductor layer 12 includes an upper Si (110) semiconductor layer. Two semiconductor layers are stacked to form a composite substrate structure of Si (111), Si (110), Si (111), and Si (110). The method can also ensure that the dissociation planes of all the silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress and greatly improving the reliability of the silicon substrate.
Furthermore, the laminated structure also comprises a dielectric layer positioned between the first semiconductor layer and/or the second semiconductor layer, and the material of the dielectric layer comprises SiO2SiN, AlN, etc. The dielectric layer and the adjacent first semiconductor layer and/or second semiconductor layer have the same crystal orientation in the vertical direction and do not coincide in the horizontal direction; or the dielectric layer and the adjacent first semiconductor layer and/or second semiconductor layer have different crystal structures and do not coincide in the horizontal direction. On one hand, the dielectric material can also be in an amorphous state and used as a buffer layer of the substrate material to reduce the accumulation of stress; on the other hand, the dielectric material has higher dielectric constant (such as SiO2 dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN dielectric constant is 8.5) and critical breakdown electric field, and can have enough thickness on the premise of ensuring that the substrate bears enough breakdown voltage, thereby ensuring the quality of the dielectric material and increasing the firmness and reliability of the substrate material.
In summary, as long as the first semiconductor layer and the second semiconductor layer in the substrate and the first semiconductor layer and the second semiconductor layer respectively have different dissociation planes in the vertical direction after rotating according to the lattice symmetry, the accumulation of stress at the interface of the first semiconductor layer and the second semiconductor layer can be reduced, and the cracking of the whole substrate caused by the accumulation of local stress of the second semiconductor layer to the whole semiconductor layer can be avoided.
According to the technical scheme, the semiconductor substrate, the semiconductor device and the manufacturing method of the semiconductor substrate provided by the invention have the advantages that the semiconductor substrate has a special lattice structure and a special mechanical structure, the semiconductor substrate is set to be a composite substrate structure, and the damage of stress applied by a semiconductor epitaxial layer to a silicon substrate can be reduced under the condition of the same substrate thickness, so that the probability of breakage of the silicon substrate is reduced; meanwhile, the process difficulty can be reduced, and the reliability of the semiconductor device can be enhanced.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (10)

1. A semiconductor substrate, comprising a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer, the first semiconductor layer rotated according to the lattice symmetry thereof and the second semiconductor layer, the first semiconductor layer and the second semiconductor layer rotated according to the lattice symmetry thereof, and the first semiconductor layer rotated according to the lattice symmetry thereof and the second semiconductor layer rotated according to the lattice symmetry thereof have different planes of dissociation in the vertical direction.
2. The semiconductor substrate according to claim 1, wherein materials of the first semiconductor layer and the second semiconductor layer are the same or different.
3. The semiconductor substrate according to claim 2, wherein the first semiconductor layer and the second semiconductor layer have the same lattice structure, and wherein the first semiconductor layer and the second semiconductor layer have the same crystal orientation in a vertical direction and do not overlap in a horizontal direction.
4. The semiconductor substrate according to claim 2, wherein the first semiconductor layer and the second semiconductor layer have different crystal structures, and crystal directions of the first semiconductor layer and the second semiconductor layer in a horizontal direction do not coincide.
5. The semiconductor substrate of claim 1, wherein the material morphology of the first semiconductor layer comprises a combination of one or more of crystalline, amorphous, and amorphous states.
6. The semiconductor substrate of claim 5, wherein the amorphous material further comprises a non-semiconductor material comprising aluminum nitride, polycrystalline silicon carbide, ceramics, and quartz.
7. The semiconductor substrate according to claim 5, wherein when the first semiconductor layer is an amorphous material, a bonding direction of the first semiconductor layer and the second semiconductor layer is not limited.
8. The semiconductor substrate according to claim 1, wherein the second semiconductor layer is a crystal layer.
9. The semiconductor substrate according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are sequentially and alternately formed into a stacked structure of three or more layers.
10. The semiconductor substrate according to claim 9, wherein the stacked structure comprises a dielectric layer between the first semiconductor layer and/or the second semiconductor layer.
CN201911266693.8A 2019-12-11 2019-12-11 Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method Withdrawn CN112951897A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911266693.8A CN112951897A (en) 2019-12-11 2019-12-11 Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911266693.8A CN112951897A (en) 2019-12-11 2019-12-11 Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method

Publications (1)

Publication Number Publication Date
CN112951897A true CN112951897A (en) 2021-06-11

Family

ID=76226477

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911266693.8A Withdrawn CN112951897A (en) 2019-12-11 2019-12-11 Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method

Country Status (1)

Country Link
CN (1) CN112951897A (en)

Similar Documents

Publication Publication Date Title
US10249788B2 (en) Semiconductor substrate, semiconductor device and manufacturing method of semiconductor substrate
US20180151359A1 (en) Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers
TWI455182B (en) Sandwich structure of nitride semiconductor device on the surface of the fourth group substrate
US7812357B2 (en) LED having vertical structure and method for fabricating the same
CN100505164C (en) Fabrication process of nitride semiconductor substrate and composite material substrate
JP2018087128A (en) Method for growing nitride semiconductor layer
KR20090100230A (en) Epitaxial semiconductor thin-film transfer using sandwich-structured wafer bonding and photon-beam
JP2001176823A (en) Method for manufacturing nitride semiconductor chip
WO2018150861A1 (en) Silicon carbide laminated substrate and production method therefor
KR20060113450A (en) Diamond substrate and method for fabricating the same
KR101926609B1 (en) Gallium nitride based semiconductor device and method of manufacturing the same
US10388518B2 (en) Epitaxial substrate and method of manufacturing the same
WO2024056041A1 (en) Epitaxial chip structure
TW201403790A (en) Stacked semiconductor device and a method of manufacturing the same
CN117080183A (en) Diamond-single crystal AlN-GaNAlGaN composite wafer and preparation method and application thereof
TW201438270A (en) Growth method for reducing defect density of gallium nitride
CN112951897A (en) Semiconductor substrate, semiconductor device, and semiconductor substrate manufacturing method
JP2017139266A (en) Composite substrate, semiconductor device, and method of manufacturing them
US20230154785A1 (en) N-face polar gan-based device and composite substrate thereof, and method of manufacturing composite substrate
KR100834698B1 (en) Method of forming gan layer and gan substrate manufactured using the same
US8552465B2 (en) Method for reducing stress in epitaxial growth
WO2024101774A1 (en) Method for manufacturing group 3 nitride semiconductor template
US20240006257A1 (en) Composite substrate, manufacturing method thereof, and semiconductor device
KR101901932B1 (en) Substrate having heterostructure, nitride-based semiconductor light emitting device and method for manufacturing the same
KR102621470B1 (en) Method for manufacturing group 3 nitride power semiconductor devices using epitaxy die

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20210611

WW01 Invention patent application withdrawn after publication