CN103681876A - 高压结场效晶体管 - Google Patents

高压结场效晶体管 Download PDF

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CN103681876A
CN103681876A CN201210334110.2A CN201210334110A CN103681876A CN 103681876 A CN103681876 A CN 103681876A CN 201210334110 A CN201210334110 A CN 201210334110A CN 103681876 A CN103681876 A CN 103681876A
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effect transistor
high voltage
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CN103681876B (zh
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陈立凡
陈永初
龚正
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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Abstract

本发明公开了一种高压结场效晶体管(High Voltage Junction Field Effect Transistor，HV JFET)。该高压结场效晶体管包括一衬底、一漏极、一源极及一P型顶层；漏极设置于衬底之上；源极设置于衬底之上；源极及漏极之间形成一通道；P型顶层设置于通道之上。

Description

高压结场效晶体管
技术领域
本发明是有关于一种结场效晶体管，且特别是有关于一种高压结场效晶体管。
背景技术
随着半导体技术的发展，一种结场效晶体管(Junction Field EffectTransistor，JFET)已广泛应用于各式电子产品中。
在结场效晶体管中，漏极与源极之间形成一通道。栅极位于通道的两侧。透过栅极的电压来控制空乏区的大小，以使通道产生夹止现象(pitchoff)，进而控制通道的开关。
结场效晶体管可以用来作为恒流二极管或者定值电阻。或者，结场效晶体管也可在低频和高频中被用来调节信号电压。
由于高压半导体技术的发展，更发展出一种高压结场效晶体管。目前研究人员努力改善高压结场效晶体管的效能。
发明内容
本发明是有关于一种高压结场效晶体管，其利用P型顶层的设计，以避免漏电流从表面穿越，进而有效降低高压结场效晶体管的阈值电压(breakdown voltage)。
根据本发明的一方面，提出一种高压结场效晶体管(High VoltageJunction Field Effect Transistor，HV JFET)。高压结场效晶体管包括一衬底、一漏极、一源极及一P型顶层。漏极设置于衬底之上。源极设置于衬底之上。源极及漏极之间形成一通道。P型顶层设置于通道之上。
为让本发明的上述内容能更明显易懂，下文特举各种实施例，并配合所附图式，作详细说明如下：
附图说明
图1绘示第一实施例的高压结场效晶体管(High Voltage Junction FieldEffect Transistor，HV JFET)的俯视图。
图2绘示图1的高压结场效晶体管的N型阱及P型阱的示意图。
图3绘示图1的高压结场效晶体管沿截面线3-3’的剖面图。
图4绘示图1的高压结场效晶体管沿截面线4-4’的剖面图。
图5绘示图1的高压结场效晶体管沿截面线5-5’的剖面图。
图6绘示第二实施例的高压结场效晶体管的俯视图。
图7绘示第三实施例的高压结场效晶体管的俯视图。
【主要元件符号说明】
100、200、300：高压结场效晶体管
110P：衬底
120N、220N、320N：漏极
130N、230N、330N：源极
140P：P型顶层
150、250、350：通道
160N：N型阱
170P、270P、370P：P型阱
171、271、371：缺口
180P：栅极
190、290、390：飘移区
191：场氧化层
192N：N型调整层
193P：P型调整层
194：绝缘层
具体实施方式
以下是提出各种实施例进行详细说明，其利用P型顶层的设计，以避免发生漏电流，进而有效降低高压结场效晶体管(High Voltage JunctionField Effect Transistor，HV JFET)的阈值电压(breakdown voltage)。然而，实施例仅用以作为范例说明，并不会限缩本发明欲保护的范围。此外，实施例中的图式是省略部份元件，以清楚显示本发明的技术特点。
第一实施例
请参照图1，其绘示第一实施例的高压结场效晶体管100的俯视图。高压结场效晶体管100包括一衬底110P(绘示于图5)、一漏极120N、一源极130N及一P型顶层140P。漏极120N及源极130N设置于衬底110P之上。源极120N及漏极130N之间形成一通道150。P型顶层140P设置于通道150之上。在通道150关闭时，P型顶层140P可以避免漏电流从衬底110P的表面穿越。
请参照图1～图2，图2绘示图1的高压结场效晶体管100的N型阱160N及P型阱170P的示意图。高压结场效晶体管100更包括一N型阱160N、二P型阱170P及二栅极180P。从图2可以更清楚了解N型阱160N与P型阱170P的关系。P型阱170P及N型阱160N设置于衬底110P上。由于衬底110P位于N型阱160N及P型阱170P之下，故以虚线标示。在本实施例中，衬底110P及P型阱170P皆为P型，N型阱160N则为N型。
如图1所示，源极130N及漏极120N设置于N型阱160N内，通道150是形成于N型阱160N内。在本实施例中，源极130N及漏极120N为N型重掺杂层。栅极180P设置于P型阱170P内。在本实施例中，栅极180P为P型重掺杂层。
请参照图3，其绘示图1的高压结场效晶体管300沿截面线3-3’的剖面图。从图3来看，此二P型阱170P设置于N型阱160N的两侧，使得N型阱160N在此处产生空乏区。空乏区宽度是逆向偏压的函数，空乏区的宽度到达一定程度时，可以使通道150(绘示于图1)被夹止(pinch off)。图3所绘示出的N型阱160N即为通道150的一部分。本实施例将P型顶层140P设置于通道150上，P型顶层140P可以避免漏电流从N型阱160N的表面穿越，进而有效降低高压结场效晶体管100的阈值电压(breakdownvoltage)。
请参照图2，P型阱170P沿一环状线排列，而相互连接成一C字形结构。环状线环绕N型阱160N。如图1所示，漏极120N位于环状线的几何中心点，而源极130N位于环状线之外。P型阱170P所环绕的区域形成一飘移区(drift region)190。飘移区190可以提供高压结场效晶体管100的耐高压的特性。
如图1所示，P型阱170P所连接的C字形结构具有一缺口171，P型顶层140P位于缺口171，源极130N位于缺口171之外。在缺口171处，P型阱170P位于通道150的两侧，而使缺口171处的通道150能够产生夹止现象。本实施例将P型顶层140P设置于缺口171处，当夹止现象发生时，可以有效地防止漏电流从缺口171的表面穿越。
请参照图4，其绘示图1的高压结场效晶体管100沿截面线4-4’的剖面图。图1的截面线4-4’是从漏极120N切向源极130N，并穿越缺口171。从图4来看，漏极120N及源极130N之间在N型阱160N中形成通道150。通道150的夹止现象将形成于缺口171处。P型顶层140P设置于通道150上，可以避免夹止现象发生时，漏电流从缺口171处的表面穿越。
此外，如图4所示，高压结场效晶体管100更包括多个场氧化层191、一N型调整层192N及一P型调整层193P。为避免俯视图过于复杂，图1并未绘示出此些场氧化层191。场氧化层191用以间隔漏极120N、P型顶层140P及源极130N。N型调整层192N及P型调整层193P设置N型阱160N内，并位于场氧化层191之下。P型调整层193P设置于N型调整层192N之下，使得通道150略为朝下偏移，以避免通道150过于接近表面。如此一来，更可改善高压结场效晶体管100的阈值电压。
请参照图5，其绘示图1的高压结场效晶体管100沿截面线5-5’的剖面图。图1的截面线5-5’是从漏极120N切向栅极180P，而没有穿越缺口171。从图5来看，场氧化层191用以间隔漏极120N与栅极180P。N型调整层192N及P型调整层193P也设置N型阱160N内，并位于场氧化层191之下。在漏极120N与栅极180P之间，形成上述的飘移区190，以提供高压结场效晶体管100的耐高压的特性。
关于高压结场效晶体管100的制造方法，以下搭配图3～图4详细说明如下。如图3所示，首先，提供衬底110P。接着，于衬底110P内形成N型阱160N及P型阱170P。
然后，如图4所示，形成P型调整层193P及N型调整层192N于N型阱160N内。接着，形成场氧化层191。
接着，如图4所示，掺杂N型材料以形成漏极120N及源极130N。然后，如图4所示，掺杂P材料以形成栅极180P(绘示于图3)及P型顶层140P。其中掺杂N型材料及掺杂P型材料的步骤可以交换顺序，端视设计及工艺需求而定。
然后，如图3所示，形成绝缘层194覆盖N型阱160N及P型阱170P。至此即完成本实施例的高压结场效晶体管100。
此外，本实施例的高压结场效晶体管100不仅可以避免漏电流从衬底110P的表面穿越以及改善阈值电压，并且适用于区域性硅表面氧化隔离(local oxidation of silicon，LOCOS)技术、浅沟道隔离(shallow trenchisolation，STI)技术、深沟道隔离(deep trench isolation，DTI)技术、绝缘层上覆硅(silicon-on insulator，SOI)技术及外延(EPI)技术。
第二实施例
请参照图6，其绘示第二实施例的高压结场效晶体管200的俯视图。本实施例的高压结场效晶体管200与第一实施例的高压结场效晶体管100不同之处在于通道250的数量，其余相同之处不再重复叙述。
如图6所示，本实施例的六个P型阱270P被六个缺口271所隔开。此些P型阱270P沿环状线对称地排列。此些缺口271也沿环状线对称地排列。
此外六个源极230N设置于六个缺口271之外，漏极220N与六个源极230N之间形成六个通道250。此些通道250均穿越飘移区290。六个通道250的阈值电压实质上相同。此些源极230N电性连接至同一端点，六个通道250的阈值电压的总和即为高压结场效晶体管200的阈值电压。
第三实施例
请参照图7，其绘示第三实施例的高压结场效晶体管300的俯视图。本实施例的高压结场效晶体管300与第二实施例的高压结场效晶体管200不同之处在于通道350的排列方式与数量，其余相同之处不再重复叙述。
如图7所示，本实施例的十二个P型阱370P被十二个缺口371所隔开。此些P型阱370P沿环状线对称地排列。此些缺口371也沿环状线对称地排列。在此实施例中，环状线实质上呈椭圆状。
此外十二个源极330N设置于十二个缺口371之外，漏极320N与十二个源极330N之间形成十二个通道350。此些通道350均穿越飘移区390。此些源极330N电性连接至同一端点，十二个通道350的阈值电压的总和即为高压结场效晶体管300的阈值电压。
综上所述，虽然本发明已以各种实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。

Claims (10)

1.一种高压结场效晶体管，包括：
一衬底；
一漏极，设置于该衬底之上；
一源极，设置于该衬底之上，该源极及该漏极之间形成一通道；以及
一P型顶层，设置于该通道之上。
2.根据权利要求1所述的高压结场效晶体管，更包括：
二栅极，设置于该通道的两侧。
3.根据权利要求1所述的高压结场效晶体管，其中该衬底为P型，该高压晶体管更包括：
一N型阱，设置于该衬底上，该源极及该漏极设置于该N型阱内；以及
二P型阱，设置于该N型阱的两侧。
4.根据权利要求3所述的高压结场效晶体管，其中该P型顶层设置于该N型阱上。
5.根据权利要求3所述的高压结场效晶体管，其中该二P型阱相互连接。
6.根据权利要求3所述的高压结场效晶体管，其中该二P型阱沿一环状线排列，该环状线环绕该N型阱。
7.根据权利要求6所述的高压结场效晶体管，其中该漏极位于该环状线的几何中心点。
8.根据权利要求6所述的高压结场效晶体管，其中该源极位于该环状线之外。
9.根据权利要求6所述的高压结场效晶体管，其中该二P型阱沿该环状线排列且连接成一C字形结构，该C字形结构具有一缺口，该P型顶层位于该缺口。
10.根据权利要求9所述的高压结场效晶体管，其中该源极位于该缺口之外。 
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