CN103681870B - Array base palte and manufacture method thereof - Google Patents
Array base palte and manufacture method thereof Download PDFInfo
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- CN103681870B CN103681870B CN201210340253.4A CN201210340253A CN103681870B CN 103681870 B CN103681870 B CN 103681870B CN 201210340253 A CN201210340253 A CN 201210340253A CN 103681870 B CN103681870 B CN 103681870B
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000009413 insulation Methods 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 51
- 239000011347 resin Substances 0.000 claims abstract description 47
- 229920005989 resin Polymers 0.000 claims abstract description 47
- 239000010409 thin film Substances 0.000 claims abstract description 34
- 238000002161 passivation Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 229910018540 Si C Inorganic materials 0.000 claims description 7
- 229910018557 Si O Inorganic materials 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000002927 oxygen compounds Chemical class 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- -1 indium tin metal-oxide Chemical class 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002023 wood Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of array base palte, including: underlay substrate, the oxide thin film transistor being formed on described underlay substrate and passivation layer and pixel layer, wherein, the material that the gate insulation layer in described oxide thin film transistor uses is non-photo-sensing type organic resin.The invention also discloses manufacture method and the display device of a kind of array base palte, use the present invention can effectively reduce power consumption, and make bottom planarize.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and manufacture method thereof.
Background technology
In thin film transistor (TFT) (Thin Film Transistor, TFT) array structure, often using silicon nitride (SiNx) as
Gate insulation layer, and gate insulation layer is formed between gate electrode and source and drain signal electrode, owing to the dielectric constant of silicon nitride own is higher,
Make gate insulation layer electric capacity higher, therefore can effective raising charging current value, shorten the charging interval.But, higher charged electrical
Flow valuve can make the electric capacity between gate electrode and source and drain signal electrode become relatively big, and this electric capacity directly affects the power consumption of display screen, from
And make the power consumption of display screen substantially become big；Meanwhile, with silicon nitride (SiNx) as gate insulation layer, its flatness is poor, concavo-convex
Liquid crystal aligning technique in box technique is caused large effect by rear end by uneven surface so that liquid crystal aligning is disorderly, easily
Cause display abnormal.
Summary of the invention
In view of this, a kind of array base palte of offer and manufacture method thereof are provided, charging can be prevented
Reduce power consumption while current loss, and bottom can be made to planarize.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that:
The invention provides a kind of array base palte, including: underlay substrate, the oxide being formed on described underlay substrate are thin
Film transistor, and passivation layer and pixel electrode, wherein, the gate insulation layer in described oxide thin film transistor uses non-photo-sensing
Type organic resin is formed.
Here, described non-photo-sensing type organic resin includes that the non-photo-sensing type containing Si-C and/or Si-O structure on main chain has
Machine resin；
The gate insulation layer that described non-photo-sensing type organic resin is formed has the surface texture of planarization；
The material that described passivation layer uses includes at least one in silicon nitride, organic resin material；
Described oxide thin film transistor includes: gate electrode, the gate insulation layer being formed on described gate electrode, be formed at institute
The source signal electrode, the leakage signal that state the oxide semiconductor layer on gate insulation layer, are formed on described oxide semiconductor layer are electric
Pole and raceway groove；Or,
Described oxide thin film transistor includes: source signal electrode, leakage signal electrode and raceway groove, and is formed at described source
Oxide semiconductor layer on signal electrode, leakage signal electrode and raceway groove, the grid being formed on described oxide semiconductor layer are exhausted
Edge layer, the gate electrode being formed on described gate insulation layer.
Present invention also offers the manufacture method of a kind of array base palte, comprise the following steps:
Underlay substrate is formed oxide thin film transistor, passivation layer and pixel electrode；Wherein, described oxide is thin
Gate insulation layer in film transistor uses non-photo-sensing type organic resin to be formed.
Here, described non-photo-sensing type organic resin includes that the non-photo-sensing type containing Si-C and/or Si-O structure on main chain has
Machine resin material；
The described step forming oxide thin film transistor on underlay substrate includes:
Underlay substrate is formed gate electrode；Described gate electrode is formed gate insulation layer；Shape on described gate insulation layer
Become oxide semiconductor layer；Described oxide semiconductor layer is formed source signal electrode, leakage signal electrode and raceway groove；Or
Person,
Underlay substrate is formed source signal electrode, leakage signal electrode and raceway groove；At described source signal electrode, leakage signal electricity
Oxide semiconductor layer is formed on pole and raceway groove；Described oxide semiconductor layer is formed gate insulation layer；At described gate insulation
Gate electrode is formed on Ceng.
The material that described passivation layer uses includes at least one in silicon nitride, organic resin material；
Invention further provides a kind of display device, described display device includes any one array disclosed by the invention
Substrate.
Array base palte provided by the present invention and manufacture method thereof, have the following advantages that and feature:
Gate insulation layer in the present invention uses the non-photo-sensing type organic resin material on main chain containing Si-C and/or Si-O structure
Material replaces silicon nitride material, so, on the one hand, owing to the dielectric constant of non-photo-sensing type organic resin material is compared with silicon nitride material
Dielectric constant is low, can effectively reduce display screen power consumption；On the other hand, due to organic resin material be planarization, uniformity good
Material, can be effectively improved the rough phenomenon of gate insulation layer so that gate insulation layer planarizes, and then makes array base palte entirety put down
Smooth, improve the controllability of subsequent technique.
Although it addition, the dielectric constant ratio of the non-photo-sensing type organic resin of present invention employing is relatively low, array base palte can be affected
Charging current, but, by use indium tin oxide material make oxide semiconductor layer, can effectively make up the damage of charging current
Lose；And owing to non-photo-sensing type organic resin material not containing H element, therefore, can preferably prevent oxide thin film transistor from filling
The characteristic of electricity electric current is deteriorated.
Accompanying drawing explanation
Fig. 1 is the composition structural representation of embodiment 1 array base palte；
Fig. 2 is the composition structural representation of embodiment 2 array base palte.
Description of reference numerals
1, underlay substrate, 2, gate electrode, 3, gate insulation layer, 4, oxide semiconductor layer, 5a, source signal electrode, 5b, leakage letter
Number electrode, 6, passivation layer, 7, via, 8, pixel electrode, 9, raceway groove
Detailed description of the invention
Below in conjunction with specific embodiment and accompanying drawing, embodiments of the present invention are described in detail.
Embodiment 1
Fig. 1 is the composition structural representation of embodiment 1 array base palte, as it is shown in figure 1, described array base palte includes: substrate
Substrate 1, the oxide thin film transistor being formed on described underlay substrate, and passivation layer 6 and pixel electrode 8；Wherein, described
Gate insulation layer in oxide thin film transistor uses non-photo-sensing type organic resin to be formed.
Gate insulation layer in array base palte of the present invention uses non-photo-sensing type organic resin material to replace silicon nitride material,
So, on the one hand, owing to the dielectric constant of non-photo-sensing type organic resin material is low compared with the dielectric constant of silicon nitride material, can be effective
Reduce display screen power consumption；On the other hand, due to the material that organic resin material is planarization, uniformity is good, grid can be effectively improved
The rough phenomenon of insulating barrier so that gate insulation layer planarizes, and then makes array base palte overall flat, improves subsequent technique
Controllability, the end to box friction (cell rubbing) technique such as can being greatly lowered in liquid crystal device manufacture process
Difference, improving product characteristic.
It addition, although the dielectric constant ratio of the non-photo-sensing type organic resin of array base palte of the present invention employing is relatively low, meeting
Affecting the charging current of array base palte, but, by using indium tin oxide material to make oxide semiconductor layer, can effectively make up
The loss of charging current；And owing to non-photo-sensing type organic resin material not containing H element, therefore, can preferably prevent oxide
The characteristic of thin film transistor (TFT) charging current is deteriorated.
Wherein, described oxide thin film transistor can at least include: gate electrode 2, the grid being formed on described gate electrode 2
Insulating barrier 3, the oxide semiconductor layer 4 being formed on described gate insulation layer 3, it is formed on described oxide semiconductor layer 4
Source and drain signal electrode layer and be formed at the raceway groove 9 on described source and drain signal electrode layer, described raceway groove 9 is at oxide semiconductor
Block source and drain signal electrode layer above layer 4, described source and drain signal electrode layer is truncated into source signal electrode 5a and leakage signal electrode
5b；
Here, the structure on described array base palte is not limited to above-mentioned listed structure, and oxide thin film transistor, blunt
The mode changing layer and pixel electrode formation does not limits, wherein, and the shape of oxide thin film transistor, passivation layer and pixel electrode
One-tenth mode can use the implementation of routine, such as 5 mask plate (5mask) techniques, 4 mask plate (4mask) techniques etc., goes back
The technology such as masstone technique and delamination technique can be utilized, these processes dawns the most known to those skilled in the art
, it is not described in detail herein.
Here, described non-photo-sensing type organic resin can include the non-photo-sensing on main chain containing Si-C and/or Si-O structure
Type organic resin material；
The material that described passivation layer uses can include the material such as silicon nitride, silicon oxide, it is also possible to includes organic resinous wood
Material, wherein, uses organic resin material to do passivation layer, can reduce end difference with improving product characteristic；
Described pixel electrode is transparent conductive material, and this transparent conductive material can include nano indium tin metal-oxide
(ITO), indium zinc metal-oxide (IZO) or indium gallium zinc oxide (IGZO).
In conjunction with the above, the concrete structure of the oxide thin film transistor on described array base palte is as it is shown in figure 1, wrap
Include:
Underlay substrate 1, is formed at the gate electrode 2 on described underlay substrate 1；It is formed at the gate insulation on described gate electrode 2
Layer 3；It is formed at the oxide semiconductor layer 4 on described gate insulation layer 3, and described oxide semiconductor layer 4 is by gate insulation layer 3
It is separated by with gate electrode 2；The source and drain signal electrode layer being formed on described oxide semiconductor layer；It is formed at described source and drain signal electricity
Raceway groove 9 on the layer of pole, described raceway groove 9 blocks source and drain signal electrode layer above oxide semiconductor layer 4, and by source and drain signal electricity
Pole layer is truncated into source signal electrode 5a and leakage signal electrode 5b；It is formed at and has formed gate electrode 2, gate insulation layer 3, oxidation above-mentioned
Passivation layer 6 on the array base palte of thing semiconductor layer 4, source signal electrode 5a, leakage signal electrode 5b and raceway groove 9；It is formed at blunt
Changing the via 7 on layer 6 and pixel electrode 8, described pixel electrode 8 is connected with leakage signal electrode 5b by via 7.
Also having grid line and data wire on array base palte, in the manufacture process of array base palte, grid line can form grid
Being formed while electrode, data wire can be formed while forming source signal electrode and leakage signal electrode.
Accordingly, the oxide thin film transistor on described array base palte and passivation layer and the manufacturer of pixel electrode
Method, including:
Gate electrode 2 is formed successively on underlay substrate 1；Described gate electrode is formed gate insulation layer 3；At described gate insulation
Oxide semiconductor layer 4 is formed on layer 3；Described oxide semiconductor layer 4 is formed source and drain signal electrode layer；In described source and drain
Forming raceway groove 9 on signal electrode layer, described raceway groove 9 blocks source and drain signal electrode layer above described oxide semiconductor layer 4, will
Source and drain signal electrode layer blocks as source signal electrode 5a and leakage signal electrode 5b；Described formed gate electrode 2, gate insulation layer 3,
Passivation layer 6 is formed on the array base palte of oxide semiconductor layer 4, source signal electrode 5a, leakage signal electrode 5b and raceway groove 9；?
Described passivation layer 6 etches via 7, and forms pixel electrode 8, and described pixel electrode 8 is by via 7 with leakage signal electrode 5b even
Connect.
Correspondingly, array base palte also having grid line and data wire, in the manufacture process of array base palte, grid line can be
Being formed while forming gate electrode, data wire can be formed while forming source signal electrode and leakage signal electrode.
The material that passivation layer described in the present embodiment uses is organic resin, is prone to planarization owing to organic resin has
Characteristic, therefore, from figure 1 it appears that the surface of described passivation layer is smooth, it is possible to be effectively reduced endmost surface poor, carry
Rise product attribute.
Embodiment 2
Fig. 2 is the composition structural representation of embodiment 2 array base palte, the oxide thin film transistor on this array base palte
Structure is top gate structure, as it can be seen, described array base palte includes: underlay substrate 1, the oxidation being formed on described underlay substrate
Thing thin film transistor (TFT) and passivation layer 6 and pixel electrode 8；Wherein, the gate insulation layer in described oxide thin film transistor uses
Non-photo-sensing type organic resin is formed.Also there is on array base palte grid line and data wire (not shown).
Gate insulation layer in array base palte of the present invention uses non-photo-sensing type organic resin material to replace silicon nitride material,
So, on the one hand, owing to the dielectric constant of non-photo-sensing type organic resin material is low compared with the dielectric constant of silicon nitride material, can be effective
Reduce display screen power consumption；On the other hand, due to the material that organic resin material is planarization, uniformity is good, grid can be effectively improved
The rough phenomenon of insulating barrier so that gate insulation layer planarizes, and then makes array base palte overall flat, improves subsequent technique
Controllability, the end to box friction (cell rubbing) technique such as can being greatly lowered in liquid crystal device manufacture process
Difference, improving product characteristic.
It addition, although the dielectric constant ratio of the non-photo-sensing type organic resin of array base palte of the present invention employing is relatively low, meeting
Affecting the charging current of array base palte, but, by using indium tin oxide material to make oxide semiconductor layer, can effectively make up
The loss of charging current；And owing to non-photo-sensing type organic resin material not containing H element, therefore, can preferably prevent oxide
The characteristic of thin film transistor (TFT) charging current is deteriorated.
Wherein, described oxide thin film transistor can at least include: source and drain signal electrode layer, be formed at described source and drain letter
Raceway groove 9 on number electrode layer, described raceway groove 9 blocks source and drain signal electrode layer, and described source and drain signal electrode layer is truncated into source
Signal electrode 5a and leakage signal electrode 5b, and it is formed at the oxygen on described source signal electrode 5a, leakage signal electrode 5b and raceway groove
Compound semiconductor layer 4, the gate insulation layer 3 being formed on described oxide semiconductor layer 4, it is formed on described gate insulation layer 3
Gate electrode 2.
Here, the structure on described array base palte is not limited to above-mentioned listed structure, and oxide thin film transistor, blunt
The mode changing layer and pixel electrode formation does not limits, wherein, and the shape of oxide thin film transistor, passivation layer and pixel electrode
One-tenth mode can use the implementation of routine, such as 5 mask plate (5mask) techniques, 4 mask plate (4mask) techniques etc., goes back
The technology such as masstone technique and delamination technique can be utilized, these processes dawns the most known to those skilled in the art
, it is not described in detail herein.
Here, described non-photo-sensing type organic resin can include the non-photo-sensing on main chain containing Si-C and/or Si-O structure
Type organic resin material；
The material that described passivation layer uses can include the material such as silicon nitride, silicon oxide, it is also possible to includes organic resinous wood
Material, wherein, uses organic resin material to do passivation layer, can reduce end difference with improving product characteristic；
Described pixel electrode is transparent conductive material, and this transparent conductive material can include nano indium tin metal-oxide
(ITO), indium zinc metal-oxide (IZO) or indium gallium zinc oxide (IGZO).
In conjunction with the above, oxide thin film transistor on described array base palte and passivation layer and the tool of pixel electrode
Body structure is as in figure 2 it is shown, include:
Underlay substrate 1, the source and drain signal electrode layer being formed on underlay substrate 1；It is formed on source and drain signal electrode layer
Raceway groove 9, described raceway groove 9 blocks source and drain signal electrode layer, and described source and drain signal electrode layer is truncated into source signal electrode 5a and
Leakage signal electrode 5b；It is formed at the oxide semiconductor layer 4 on source signal electrode 5a, leakage signal electrode 5b and raceway groove 9, and institute
State oxide semiconductor layer 4 and cut off source and drain signal electrode layer by described raceway groove 9；It is formed at and has formed source signal electrode above-mentioned
Gate insulation layer 3 on the array base palte of 5a, leakage signal electrode 5b, raceway groove 9 and oxide semiconductor layer 4；It is formed at gate insulation
Gate electrode 2 on layer 3, and described gate electrode 2 is separated by with oxide semiconductor layer 4 by gate insulation layer 3；Be formed at above-mentioned
Form source signal electrode 5a, leakage signal electrode 5b, raceway groove 9, oxide semiconductor layer 4, gate insulation layer 3 and the battle array of gate electrode 2
Passivation layer 6 on row substrate；Being formed at the via 7 on described passivation layer 6 and pixel electrode 8, described pixel electrode 8 passes through via
7 are connected 5b with drain electrode.
Also having grid line and data wire on array base palte, in the manufacture process of array base palte, grid line can form grid
Being formed while electrode, data wire can be formed while forming source signal electrode and leakage signal electrode.
Correspondingly, the oxide thin film transistor on described array base palte and passivation layer and the manufacturer of pixel electrode
Method, including:
Underlay substrate 1 is formed source and drain signal electrode layer；Described source and drain signal electrode layer is formed raceway groove 9, described
Raceway groove 9 blocks source and drain signal electrode layer, and described source and drain signal electrode layer is truncated into source signal electrode 5a and leakage signal electrode
5b；Described source signal electrode 5a, leakage signal electrode 5b and raceway groove 9 are formed oxide semiconductor layer 4, and described oxide half
Conductor layer 4 cuts off source and drain signal electrode layer by described raceway groove 9；Described formed source signal electrode 5a, leakage signal electrode 5b,
Gate insulation layer 3 is deposited on the array base palte of raceway groove 9 and oxide semiconductor layer 4；Depositing gate electrode on described gate insulation layer 3
2；Source signal electrode 5a, leakage signal electrode 5b, raceway groove 9, oxide semiconductor layer 4, gate insulation layer 3 and grid have been formed described
Passivation layer 6 is formed on the array base palte of electrode 2；Etch via 7 at described passivation layer 6, and form pixel electrode 8, described picture
Element electrode 8 is connected with leakage signal electrode 5b by via 7.
Correspondingly, array base palte also having grid line and data wire, in the manufacture process of array base palte, grid line can be
Being formed while forming gate electrode, data wire can be formed while forming source electrode and drain electrode.
The material that passivation layer described in the present embodiment uses is silicon nitride, owing to silicon nitride is non-planarization material, therefore,
From figure 2 it can be seen that the surface of described passivation layer is non-flat forms.
The structure of the array base palte enumerated in the embodiment of the present invention is optional scheme, each composition portion on array base palte
Point and thin film transistor (TFT) included by the position of each layer and formation order be not limited to the mode described in embodiment, but can
There to be a variety of change, such as can form pixel electrode at first, form source and drain signal electrode, gate electrode etc. the most again, as long as
The structure formed is capable of the driving of panel.
Present invention also offers a kind of display device, wherein, the array base palte in described display device is embodiment 1 or real
Execute any one array base palte described in example 2.
Here, described display device can be: liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, TV
Any product with display function or the parts such as machine, display, notebook computer, DPF, navigator.
The above, only presently preferred embodiments of the present invention, it is not intended to limit protection scope of the present invention.
Claims (7)
1. an array base palte, including: underlay substrate, the oxide thin film transistor being formed on described underlay substrate, and
Passivation layer and pixel electrode, wherein, the gate insulation layer in described oxide thin film transistor uses non-photo-sensing type organic resin shape
Become；
Described non-photo-sensing type organic resin includes the non-photo-sensing type organic resin on main chain containing Si-C and/or Si-O structure；Institute
State in non-photo-sensing type organic resin material without H element；The gate insulation layer that described non-photo-sensing type organic resin is formed has smooth
The surface texture changed.
Array base palte the most according to claim 1, it is characterised in that described passivation layer use material include silicon nitride,
At least one in organic resin material.
Array base palte the most according to claim 1, it is characterised in that described oxide thin film transistor includes: gate electrode,
Be formed at the gate insulation layer on described gate electrode, the oxide semiconductor layer being formed on described gate insulation layer, be formed at described
Source signal electrode, leakage signal electrode and raceway groove on oxide semiconductor layer；
Or, described oxide thin film transistor includes: source signal electrode, leakage signal electrode and raceway groove, and is formed at described
Oxide semiconductor layer on source signal electrode, leakage signal electrode and raceway groove, the grid being formed on described oxide semiconductor layer
Insulating barrier, the gate electrode being formed on described gate insulation layer.
4. a manufacture method for array base palte, comprises the following steps:
Underlay substrate is formed oxide thin film transistor, passivation layer and pixel electrode；Wherein, described sull is brilliant
Gate insulation layer in body pipe uses non-photo-sensing type organic resin to be formed；Described non-photo-sensing type organic resin includes containing on main chain
The non-photo-sensing type organic resin material of Si-C and/or Si-O structure；Without H element in described non-photo-sensing type organic resin material；
The gate insulation layer that described non-photo-sensing type organic resin is formed has the surface texture of planarization.
Manufacture method the most according to claim 4, it is characterised in that described formation sull crystalline substance on underlay substrate
The step of body pipe includes:
Underlay substrate is formed gate electrode；Described gate electrode is formed gate insulation layer；Described gate insulation layer is formed oxygen
Compound semiconductor layer；Described oxide semiconductor layer is formed source signal electrode, leakage signal electrode and raceway groove；
Or,
Underlay substrate is formed source signal electrode, leakage signal electrode and raceway groove；Described source signal electrode, leakage signal electrode and
Oxide semiconductor layer is formed on raceway groove；Described oxide semiconductor layer is formed gate insulation layer；On described gate insulation layer
Form gate electrode.
Manufacture method the most according to claim 4, it is characterised in that described passivation layer use material include silicon nitride,
At least one in organic resin material.
7. a display device, it is characterised in that described display device includes the array base described in any one of claims 1 to 3
Plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210340253.4A CN103681870B (en) | 2012-09-13 | 2012-09-13 | Array base palte and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210340253.4A CN103681870B (en) | 2012-09-13 | 2012-09-13 | Array base palte and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN103681870A CN103681870A (en) | 2014-03-26 |
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| CN101750821A (en) * | 2008-12-03 | 2010-06-23 | 株式会社半导体能源研究所 | Liquid crystal display device |
| TW201203557A (en) * | 2010-04-09 | 2012-01-16 | Dainippon Printing Co Ltd | Thin film transistor substrate |
| CN202948924U (en) * | 2012-09-13 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and display device |
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| CN101750821A (en) * | 2008-12-03 | 2010-06-23 | 株式会社半导体能源研究所 | Liquid crystal display device |
| TW201203557A (en) * | 2010-04-09 | 2012-01-16 | Dainippon Printing Co Ltd | Thin film transistor substrate |
| CN202948924U (en) * | 2012-09-13 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and display device |
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