CN103681780A - High-voltage super-junction terminal structure - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 21
- 230000000802 nitrating effect Effects 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 22
- 230000015556 catabolic process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910001415 sodium ion Inorganic materials 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005204 segregation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a high-voltage super-junction terminal structure which comprises a super-junction region and a terminal surface structure, wherein the super-junction region is composed of P +, N-, N + columns which are distributed at intervals, the terminal surface structure is provided with a metal field plate and a SIPOS field plate, a P-layer is arranged between the super-junction region and the terminal surface structure, and a high-resistance SIPOS layer and SiO are sequentially deposited on the terminal surface structure from bottom to top2The surface structure of the terminal can also be deposited with a high-resistance SIPOS layer and SiO from bottom to top in sequence2The layer, the metal field plate and the nitrogen-doped SIPOS layer are cut off by adopting a groove at the tail end. The high-voltage super-junction terminal structure provided by the invention can resist high voltage, improves the reliability of the terminal, reduces leakage current, and can be applied to terminal manufacturing of high-power devices (IGBT, VDMOS and the like).
Description
Technical field
The present invention relates to voltage-controlled type power device and make field, particularly a kind of high pressure superjunction termination structure.
Background technology
The ability of device blocking-up high pressure depends primarily on the anti-puncture voltage partially of specific PN junction in device architecture.In power device, be subject to the impact of PN junction bending or PN junction termination surface non-ideal factor, the anti-puncture voltage partially of PN junction is limited to again and occurs near surface or tie knee regional area and with respect to parallel plane in body, tie the punch-through occurring in advance.Knot terminal is exactly in order to reduce internal field, improve surface breakdown voltage and reliability, to make device actual breakdown voltage more approach parallel plane knot ideal value and custom-designed special construction.In longitudinal conductive devices, it is distributed in the periphery of device active region conventionally.
Knot terminal, as the important component part of power semiconductor, plays vital effect to the realization of systematic function and improvement.The requirement of junction termination structures is comprised to the many aspects such as area efficiency height and good reliability.Wherein the area efficiency of power device relies on junction termination structures very much, and when the shared area of knot terminal reduces, on same chip area, the area of active area increases, and so just can improve the disposal ability of electric current
Super-junction structure is because the withstand voltage principle of its uniqueness makes it have excellent performance aspect the characterisitic parameter compromise of device, and the design feature of super knot is N, and P intercolumniation is every staggered general layout.By this structure, introduce transverse electric field, utilize transverse electric field to realize high voltage bearing object to the impact of longitudinal electric field.Common super-junction laterally Electric Field Distribution is triangle, and longitudinal electric field is distributed as trapezoidal.The accurate super-junction structure better performances of charge balance in theory, otherwise parameter can degenerate to some extent, but actual process is difficult to accomplish absolute balance.
In patent US20100032791-A1, a kind of superjunction termination structure has been proposed.As shown in Figure 1, in this patent, the width of the highly doped post of terminal end surface structure and highly be gradual change, makes voltage comparatively even in terminal end surface structure distribution, and the outermost of terminal adopts deep trouth to end, and guarantees to improve withstand voltage time terminal reliability.But this superjunction termination structure has following shortcoming:
1) existing technique is difficult to ensure the super knot of card P, and the electric charge of N post reaches accurate balance, and this will cause the parameter degradation of device, for example BV just along with the reinforcement of charge unbalance degree decline terribly.
2) field uniformity on terminal end surface structural semiconductor surface is not good, easily near knot or the end of field plate there is punch-through.
3) in technique, cannot prevent ionic soil and the charge accumulated at interface, greatly affect the reliability of power device.
4) existing terminal technology is due to pressure-resistance structure, and the width of the terminal end surface domain of high pressure resistant needs is larger.Increase chip area, increased the production cost of chip.
Summary of the invention
Technical problem to be solved by this invention be to provide a kind of can be high pressure resistant, reliability is high, leakage current is little high pressure superjunction termination structure.
For solving the problems of the technologies described above, the invention provides a kind of high pressure superjunction termination structure, comprise by P+ spaced apart, N-, the super interface that N+ post forms and the terminal end surface structure that has Metal field plate and SIPOS field plate, between described super interface and terminal end surface structure, have one deck P-layer, described terminal end surface structure is deposited with high resistant SIPOS layer, SiO from down to up successively
2layer, low-resistance SIPOS layer, Metal field plate and nitrating SIPOS layer.
Further, the oxygen content in described high resistant SIPOS layer is 20%-35%.
Further, the oxygen content in described low-resistance SIPOS layer is 5%-20%.
Further, described terminal end surface structure can be the terminal end surface structure of SIPOS passivation, groove cut-off, and described terminal end surface structure is deposited with high resistant SIPOS layer, SiO from down to up successively
2layer, Metal field plate and nitrating SIPOS layer.
Further, the oxygen content in described high resistant SIPOS layer is 20%-35%.
Further, described high resistant SIPOS layer, low-resistance SIPOS layer and nitrating SIPOS layer are all under 650 ℃ of conditions, with the deposit of LPCVD method, become.
A kind of high pressure superjunction termination structure provided by the invention has the following advantages:
1. adopt P+ spaced apart, N-, N+ post forms follow-on super-junction structure, and raising termination environment is withstand voltage.
2. terminal end adopts deep trouth cut-off, in groove, fill high resistant SIPOS SiO
2nitrating SIPOS, and be connected with this structure of upper surface, prevent surface and corner breakdown, improve terminal reliability, reduce leakage current;
3. termination environment surface and cut-off rooved face Si and SiO
2between increase high resistant SIPOS layer, can effectively reduce ionic soil and charge accumulated, improve terminal reliability.
4. adopt Metal field plate to reduce the peak electric field at PN junction place, adopt low-resistance SIPOS resistor-type field plate to make the planarization of terminal end surface electric field, avoided the electric field concentration effect at Metal field plate edge.
5. termination environment upper surface, by the shallow P layer of Implantation, can effectively prevent the charge unbalance that super-junction structure causes due to impurity segregation.
6. nitrating SIPOS, as outermost passivation, can effectively stop steam and the such mobile ion of Na+ ion.
Accompanying drawing explanation
Fig. 1 is a kind of superjunction termination structural representation that patent US20100032791-A1 provides.
The superjunction termination structure chart that has Metal field plate and SIPOS field plate that Fig. 2 provides for the embodiment of the present invention.
The SIPOS passivation that Fig. 3 provides for the embodiment of the present invention, groove cut-off type superjunction termination structure chart.
Embodiment
Referring to Fig. 2, the invention provides a kind of high pressure superjunction termination structure, comprise by P+ spaced apart, N-, the super interface 1 that N+ post forms and the terminal end surface structure 2 that has Metal field plate and SIPOS field plate, between super interface 1 and terminal end surface structure 2, have one deck P-layer 3, terminal end surface structure 2 silicon chip surfaces are deposited with high resistant SIPOS layer 201, SiO from down to up successively
2 layer 202, low-resistance SIPOS layer 203, Metal field plate 204 and nitrating SIPOS layer 205.
Referring to Fig. 3, a kind of high pressure superjunction termination structure that the embodiment of the present invention provides, comprise by P+ spaced apart, N-, the super interface 1 that N+ post forms and the terminal end surface structure 2 that has Metal field plate and SIPOS field plate, between super interface 1 and terminal end surface structure 2, have one deck P-layer 3, terminal end surface structure 2 silicon chip surfaces are deposited with high resistant SIPOS layer 201, SiO from down to up successively
2 layer 202, Metal field plate 204 and nitrating SIPOS layer 205.
The super interface 1 of the superjunction termination structure that has Metal field plate and SIPOS field plate that the embodiment of the present invention provides is by P+ spaced apart, N-, N+ post forms, the width of doped column and doping content need guarantee P, the charge balance (in P+ post, electric charge equals electric charge sum in N-post and N+ post) that n type material is overall, improve the charge balance degree in super interface with shallow injection one deck P-on terminal end surface structure 2 surfaces, such structure has been introduced a trapezoidal electric field in the horizontal, can effectively improve the withstand voltage of termination environment.With terminal end surface structure 2 deposit high resistant SIPOS layer 201(oxygen content 20%-35% successively from down to up), SiO
2layer 202, low-resistance SIPOS layer 203(oxygen content 5%-20%), Metal field plate 204, nitrating SIPOS layer 205 is as outermost passivation.Low-resistance SIPOS layer 203 is as SIPOS field plate, and Metal field plate 204 is positioned on SIPOS field plate.Two kinds of field plate Integrated usings can make terminal end surface electric field even.SiO2 layer 202 between high resistant SIPOS layer 201 and low-resistance SIPOS layer 203 can reduce leakage current, and nitrating SIPOS layer 205 can effectively stop steam and the such mobile ion of Na+ ion as outermost passivation
The super interface 1 of the superjunction termination structure of the SIPOS passivation that the embodiment of the present invention provides, groove cut-off is by P+ spaced apart, N-, N+ post forms, the width of doped column and doping content need guarantee P, the charge balance that n type material is overall, surface shallow injection one deck P-of terminal end surface structure 2 improves the charge balance degree in super interface, terminal end surface structure 2 is deposit high resistant SIPOS layer 201(oxygen content 20%-35% successively from down to up), SiO2 layer 202, Metal field plate 204, nitrating SIPOS layer 205 is as outermost passivation.The cut-off groove inner stuffing of far-end and the deposit of silicon chip surface form simultaneously, connect together, and structure is identical with surface, guarantee that surface field and corner are tending towards evenly, preventing surface or corner breakdown.
The high resistant SIPOS layer relating in said structure, low-resistance SIPOS layer and nitrating SIPOS layer are all at 650 ℃, and the method deposit of use LPCVD becomes.
A kind of high pressure superjunction termination structure provided by the invention, the N being intervally arranged, P post forms super-junction structure.It is withstand voltage, and principle is introduced transverse electric field by transverse p/n junction exactly, utilizes transverse electric field to realize high voltage bearing object to the impact of longitudinal electric field.Common super-junction laterally Electric Field Distribution is triangle, and longitudinal electric field is distributed as trapezoidal.The super knot of horizontal varying doping of mentioning in the present invention is to tie to realize horizontal trapezoidal Electric Field Distribution by introducing horizontal P+N-N+, and longitudinal electric field distribution is still trapezoidal, thereby improves the withstand voltage of termination environment in situation of the same area.
Termination environment upper surface is by the shallow P layer of Implantation, and the P post can compensated part causing due to impurity segregation in annealing narrows down, and can effectively reduce the degree of charge unbalance, prevents parameter degradation.
Terminal end adopts groove cut-off, fills SIPOS, SiO
2combination layer and being connected with the passivating structure of upper surface, this structure can make surface and corner's electric field be tending towards evenly, preventing surface breakdown.
SIPOS film is semi-insulated in addition, almost electroneutral, when silicon device surface directly contacts with oxygen-doped high resistant SIP0S, the electric charge that ion on interface stains near the opposite polarity of responding to silicon face will float to SIPOS layer the inside, and the electric charge of induction by and the electric charge of outer surface.On the other hand, because hot carrier can not stayed in SIPOS layer for a long time, so the hot carrier that is injected into passivation layer due to PN junction avalanche breakdown storage effect can not occur.In addition, the half insulation of SIPOS film also makes it can release surface electric field.And add one deck SiO on high resistant SIPOS layer
2can reduce leakage current, therefore, each layer of integrated application, is conducive to improve the withstand voltage and reliability of device.Nitrating SIPOS, as outermost passivation, can effectively stop steam and the such mobile ion of Na+ ion.
Metal field plate improves the radius of curvature of finishing, and reduces near the peak electric field finishing; SIPOS resistive field plate makes silicon surface electric field planarization, has avoided the electric field concentration effect at Metal field plate edge.It is withstand voltage that this all contributes to improve terminal.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to example, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (6)
1. a high pressure superjunction termination structure, it is characterized in that: comprise by P+ spaced apart, N-, the super interface that N+ post forms and the terminal end surface structure that has Metal field plate and SIPOS field plate, between described super interface and terminal end surface structure, have one deck P-layer, described terminal end surface structure is deposited with high resistant SIPOS layer, SiO from down to up successively
2layer, low-resistance SIPOS layer, Metal field plate and nitrating SIPOS layer.
2. high pressure superjunction termination structure according to claim 1, is characterized in that: the oxygen content in described high resistant SIPOS layer is 20%-35%.
3. high pressure superjunction termination structure according to claim 1, is characterized in that: the oxygen content in described low-resistance SIPOS layer is 5%-20%.
4. high pressure superjunction termination structure according to claim 1, is characterized in that: described terminal end surface structure is the terminal end surface structure of SIPOS passivation, groove cut-off, and described terminal end surface structure is deposited with high resistant SIPOS layer, SiO from down to up successively
2layer, Metal field plate and nitrating SIPOS layer.
5. high pressure superjunction termination structure according to claim 4, is characterized in that: the oxygen content of described high resistant SIPOS layer is 20%-35%.
6. according to the high pressure superjunction termination structure described in claim 1-5 any one, it is characterized in that: described high resistant SIPOS layer, low-resistance SIPOS layer and nitrating SIPOS layer are all under 650 ℃ of conditions, with the deposit of LPCVD method, become.
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| CN201210345440.1A CN103681780B (en) | 2012-09-17 | 2012-09-17 | High-voltage super-junction terminal structure |
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| CN201210345440.1A CN103681780B (en) | 2012-09-17 | 2012-09-17 | High-voltage super-junction terminal structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390396A (en) * | 2015-10-27 | 2016-03-09 | 株洲南车时代电气股份有限公司 | Method for fractionally depositing semi-insulating polycrystalline silicon based on IGBT and IGBT terminal structure |
| CN109564932A (en) * | 2016-08-08 | 2019-04-02 | 三菱电机株式会社 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020130330A1 (en) * | 1999-10-28 | 2002-09-19 | Kim Jin-Kyeong | High voltage semiconductor device using sipos and methods for fabricating the same |
| US6512268B1 (en) * | 1999-08-23 | 2003-01-28 | Fuji Electric Co., Ltd. | Super-junction semiconductor device |
| US20050242411A1 (en) * | 2004-04-29 | 2005-11-03 | Hsuan Tso | [superjunction schottky device and fabrication thereof] |
| CN201699004U (en) * | 2010-03-04 | 2011-01-05 | 江阴新顺微电子有限公司 | Planar terminal passivating structure of controlled silicon device |
| CN102420240A (en) * | 2011-07-05 | 2012-04-18 | 上海华虹Nec电子有限公司 | Terminal protection structure of super junction device and manufacturing method of terminal protection structure |
-
2012
- 2012-09-17 CN CN201210345440.1A patent/CN103681780B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6512268B1 (en) * | 1999-08-23 | 2003-01-28 | Fuji Electric Co., Ltd. | Super-junction semiconductor device |
| US20020130330A1 (en) * | 1999-10-28 | 2002-09-19 | Kim Jin-Kyeong | High voltage semiconductor device using sipos and methods for fabricating the same |
| US20050242411A1 (en) * | 2004-04-29 | 2005-11-03 | Hsuan Tso | [superjunction schottky device and fabrication thereof] |
| CN201699004U (en) * | 2010-03-04 | 2011-01-05 | 江阴新顺微电子有限公司 | Planar terminal passivating structure of controlled silicon device |
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Non-Patent Citations (1)
| Title |
|---|
| 尹贤文，何林，黄平: "金属场板加SIPOS电阻场板的新型终端技术", 《微电子学》, vol. 22, no. 6, 31 December 1992 (1992-12-31), pages 4 - 7 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390396A (en) * | 2015-10-27 | 2016-03-09 | 株洲南车时代电气股份有限公司 | Method for fractionally depositing semi-insulating polycrystalline silicon based on IGBT and IGBT terminal structure |
| CN105390396B (en) * | 2015-10-27 | 2018-06-08 | 株洲南车时代电气股份有限公司 | Substep deposit semi-insulating polysilicon method and IGBT terminal structures based on IGBT |
| CN109564932A (en) * | 2016-08-08 | 2019-04-02 | 三菱电机株式会社 | Semiconductor device |
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