CN103681448A - Method for forming shallow trench isolation region - Google Patents
Method for forming shallow trench isolation region Download PDFInfo
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- CN103681448A CN103681448A CN201210337557.5A CN201210337557A CN103681448A CN 103681448 A CN103681448 A CN 103681448A CN 201210337557 A CN201210337557 A CN 201210337557A CN 103681448 A CN103681448 A CN 103681448A
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- oxide
- silicon nitride
- nitride layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
The invention discloses a method for forming a shallow trench isolation region. The method comprises the following steps: sequentially forming an isolation oxidation layer and a silicon nitride layer on a semiconductor substrate; sequentially etching the silicon nitride layer, the isolation oxidation layer and the semiconductor substrate, and forming a trench inside the semiconductor substrate; growing a liner silicon nitride layer on the surface inside the trench; filling and polishing an oxide inside the trench, forming the shallow trench isolation region, and eliminating the silicon nitride layer, wherein the step of filling the oxide inside the trench is performed by repeatedly using a method that the silicon nitride layer is formed through high-density plasma chemical vapor deposition with the combination of oxygen treatment. Through the adoption of the method, granular impurities can be effectively eliminated.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of method that forms shallow channel isolation area.
Background technology
The concrete manufacture method of prior art shallow channel isolation area comprises the steps:
Step 11, in Semiconductor substrate 100 thermal oxide growth isolating oxide layer 101, with protection active area, in the follow-up process of removing silicon nitride layer, avoiding chemistry stains, and as the stress-buffer layer between silicon nitride layer and silicon substrate, described Semiconductor substrate is silicon substrate;
Step 12, at the surface deposition silicon nitride layer 102 of described isolating oxide layer 101; Wherein, the silicon nitride layer that in this step, deposition obtains is the mask material that one deck is firm;
The etching of step 13, shallow trench: etch silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100 successively, at the interior formation groove of described Semiconductor substrate 100;
The growth of step 14, trench liner silica 103, at the inner superficial growth one deck of groove liner oxidation silicon 103, this liner oxidation silicon 103 is for improving the interfacial characteristics between Semiconductor substrate and the oxide of follow-up filling;
Step 15, trench oxide 104 are filled and polishing, adopt the method for high density plasma CVD (HDPCVD), and fill oxide in groove, then carries out the polishing of oxide; Wherein, the silicon nitride layer that deposition obtains in step 12 can be protected active area in the process of carrying out this step, serves as the barrier material of polishing, prevents the excessive polishing of oxide;
Concrete, HDPCVD adopts the method for deposition limit, limit etching to fill, and uses synchronous deposition and etching, and the speed of deposition is greater than the speed of etching, will reduce like this generation in cavity (via) in groove.
Step 16, remove described silicon nitride layer 102.
According to foregoing description, step 11 to the structural representation of 15 formation as shown in Figure 1a, the structural representation that step 16 forms is as shown in Figure 1 b.
It should be noted that, in forming the process of shallow channel isolation area, in reaction chamber, can form a lot of particle impurity.In HDPCVD method, etching adopts NF
3the nitrogen ion dissociateing can become new accessory substance, the fluorine ion dissociateing is attached on these particle impurity, though in groove in the process of fill oxide aspiration pump to the processing of bleeding of the impurity in reaction chamber simultaneously, also cannot thoroughly remove these impurity.If these impurity are present in trench oxide 104, and be just present in the position that oxide cmp stops, after step 15 pair oxide cmp stops, in this position, just there will be depression, as shown in Fig. 1 a '.Follow-uply on the active area of both sides, shallow channel isolation area, form polysilicon gate, very possible because the existence of depression makes etch polysilicon grid incomplete, cause two polysilicon gates on active area to be electrical connected.Therefore how effectively to remove these particle impurity and accessory substances, become the problem of paying close attention in the industry.
Summary of the invention
In view of this, the invention provides a kind of method that forms shallow channel isolation area, can effectively remove particle impurity.
Technical scheme of the present invention is achieved in that
A method that forms shallow channel isolation area, the method comprises:
In Semiconductor substrate, form successively isolating oxide layer and silicon nitride layer;
Etch silicon nitride layer, isolating oxide layer and Semiconductor substrate form groove in described Semiconductor substrate successively;
At the inner superficial growth one deck of described groove liner oxidation silicon;
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer;
In groove, carry out the filling employing high density plasma CVD HDPCVD formation silicon oxide layer of oxide and the method that oxygen treatments applied combines, repeatedly loop.
In groove in the process of fill oxide aspiration pump to the processing of bleeding of the impurity in reaction chamber simultaneously.
The flow that passes into oxygen in deposition reaction chamber is that 250～350 standard cubic centimeters are per minute.
From such scheme, can find out, the present invention carries out the filling employing high density plasma CVD formation silicon oxide layer of oxide and the method that oxygen treatments applied combines in groove, repeatedly loop, reduced adhering to of particle impurity, and increased the packed density of oxide, improved the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 b is the structural representation that prior art forms the detailed process of shallow channel isolation area.
After prior art stops oxide cmp, there is the schematic diagram of depression in Fig. 1 a '.
Fig. 2 is the schematic flow sheet of shallow channel isolation area of the present invention manufacture method.
Fig. 2 a to 2e is the structural representation that the present invention forms shallow channel isolation area detailed process.
Fig. 3 a and Fig. 3 b are respectively after prior art and the present invention carry out polishing to the oxide of filling in groove, and the scintigram of depression appears in each locational shallow channel isolation area of wafer.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The concrete manufacturing process schematic diagram of shallow channel isolation area of the present invention refers to Fig. 2 a to Fig. 2 e, and the schematic flow sheet of concrete manufacture method as shown in Figure 2, comprises the steps:
Particularly, thermal oxide growth isolating oxide layer 101 in Semiconductor substrate 100, stains to protect active area to avoid chemistry in the follow-up process of removing silicon nitride layer, and as the stress-buffer layer between silicon nitride layer and silicon substrate; Then at the surface deposition silicon nitride layer 102 of described isolating oxide layer 101; Wherein, the silicon nitride layer that in this step, deposition obtains is the mask material that one deck is firm;
The etching of step 22, shallow trench: etch silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100 successively, at the interior formation groove of described Semiconductor substrate 100;
The growth of step 23, trench liner silica 103, at the inner superficial growth one deck of groove liner oxidation silicon 103, this liner oxidation silicon 103 is for improving the interfacial characteristics between Semiconductor substrate and the oxide of follow-up filling;
The structural representation forming according to step 21 to step 23 as shown in Figure 2 a.
Wherein, in groove, carry out the filling employing HDPCVD formation silicon oxide layer of oxide and the method that oxygen treatments applied combines, repeatedly loop.Cycle-index can be carried out flexible according to the thickness of each deposition.And, in groove in the process of fill oxide aspiration pump to the processing of bleeding of the impurity in reaction chamber simultaneously.
Step 241, employing high density plasma CVD method are carried out silicon oxide layer deposition for the first time, form the first silicon oxide layer 201, as shown in Figure 2 b;
In the embodiment of the present invention, the filling thickness of oxide is 6000 dusts altogether, and the thickness of silicon oxide layer for the first time that limit deposition limit etching obtains is so about 3000 dusts.
Step 242, in deposition reaction chamber, pass into oxygen;
Wherein, the object that passes into oxygen in deposition reaction chamber is, further increase particle impurity is extracted into the dynamics outside reaction chamber, and oxygen can be oxidized STI film, makes STI film finer and close.Here, flow 250～350 standard cubic centimeters that pass into oxygen are per minute, and the time that passes into oxygen is longer, and effect is more obvious.
Step 243, employing high density plasma CVD method are carried out silicon oxide layer deposition for the second time, form the second silicon oxide layer 202, as shown in Figure 2 c;
In the embodiment of the present invention, the filling thickness of oxide is 6000 dusts altogether, and the thickness of silicon oxide layer for the second time that limit deposition limit etching obtains so is also about 3000 dusts.
Step 244, in deposition reaction chamber, pass into oxygen;
In like manner, flow 250～350 standard cubic centimeters that pass into oxygen are per minute, and the time that passes into oxygen is longer, and effect is more obvious.
Step 245, the oxide of filling in groove is carried out to polishing, as shown in Figure 2 d.Wherein, the silicon nitride layer that deposition obtains in step 21 can be protected active area in the process of carrying out this step, serves as the barrier material of polishing, prevents the excessive polishing of oxide;
From Fig. 2 d, can find out, because aspiration pump can be extracted into particle impurity outside reaction chamber, add oxygen treatments applied, further strengthened particle impurity to be extracted into the dynamics outside reaction chamber, so the depression that the position that polishing stops causes with regard to the existence there will not be due to particle impurity.
So far, embodiment of the present invention shallow channel isolation area forms.
The filling of above-described embodiment oxide forms at twice, this is the wherein a kind of mode of lifting just, can also divide more times to complete the filling of oxide, but need to adopt oxygen to process after each filling, in time reaction chamber and the particle impurity being attached on fill oxide are extracted into outside reaction chamber with oxygen, free nitrogen ion also can with oxygen reaction, with oxygen, be extracted into outside reaction chamber.The oxygen simultaneously passing into and each silicon oxide film generation chemical reaction forming, improved the density of silicon oxide film greatly.Fig. 3 a and Fig. 3 b are respectively after prior art and the present invention carry out polishing to the oxide of filling in groove, and the scintigram of depression appears in each locational shallow channel isolation area of wafer.Stain is recess, and from relatively can finding out of Fig. 3 a and Fig. 3 b, the depression in Fig. 3 b obviously reduces, and this explanation adopts method particle impurity of the present invention to greatly reduce, and so just can effectively avoid the problem that polysilicon gate is electrically connected to occur.
To sum up, by the present invention, form the method for shallow channel isolation area, reduced adhering to of particle impurity, and increased the packed density of oxide, improved the performance of semiconductor device.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (3)
1. a method that forms shallow channel isolation area, the method comprises:
In Semiconductor substrate, form successively isolating oxide layer and silicon nitride layer;
Etch silicon nitride layer, isolating oxide layer and Semiconductor substrate form groove in described Semiconductor substrate successively;
At the inner superficial growth one deck of described groove liner oxidation silicon;
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer;
It is characterized in that, in groove, carry out the filling employing high density plasma CVD HDPCVD formation silicon oxide layer of oxide and the method that oxygen treatments applied combines, repeatedly loop.
2. the method for claim 1, is characterized in that, in groove in the process of fill oxide aspiration pump to the processing of bleeding of the impurity in reaction chamber simultaneously.
3. method as claimed in claim 2, is characterized in that, the flow that passes into oxygen in deposition reaction chamber is that 250～350 standard cubic centimeters are per minute.
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| CN201210337557.5A CN103681448A (en) | 2012-09-13 | 2012-09-13 | Method for forming shallow trench isolation region |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725146A (en) * | 2021-08-30 | 2021-11-30 | 上海华虹宏力半导体制造有限公司 | Forming method of shallow trench isolation structure and manufacturing method of flash memory |
| CN114582791A (en) * | 2020-11-18 | 2022-06-03 | 和舰芯片制造(苏州)股份有限公司 | Method for effectively filling shallow trench isolation trench |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331472B1 (en) * | 2000-10-11 | 2001-12-18 | Macronix International Co., Ltd. | Method for forming shallow trench isolation |
| US20030207580A1 (en) * | 2002-05-03 | 2003-11-06 | Applied Materials, Inc. | HDP-CVD dep/etch/dep process for improved deposition into high aspect ratio features |
| CN101079391A (en) * | 2006-05-26 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
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- 2012-09-13 CN CN201210337557.5A patent/CN103681448A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331472B1 (en) * | 2000-10-11 | 2001-12-18 | Macronix International Co., Ltd. | Method for forming shallow trench isolation |
| US20030207580A1 (en) * | 2002-05-03 | 2003-11-06 | Applied Materials, Inc. | HDP-CVD dep/etch/dep process for improved deposition into high aspect ratio features |
| CN101079391A (en) * | 2006-05-26 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582791A (en) * | 2020-11-18 | 2022-06-03 | 和舰芯片制造(苏州)股份有限公司 | Method for effectively filling shallow trench isolation trench |
| CN113725146A (en) * | 2021-08-30 | 2021-11-30 | 上海华虹宏力半导体制造有限公司 | Forming method of shallow trench isolation structure and manufacturing method of flash memory |
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Application publication date: 20140326 |