CN103681257A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN103681257A CN103681257A CN201210356070.1A CN201210356070A CN103681257A CN 103681257 A CN103681257 A CN 103681257A CN 201210356070 A CN201210356070 A CN 201210356070A CN 103681257 A CN103681257 A CN 103681257A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 31
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000002019 doping agent Substances 0.000 claims description 25
- 238000005137 deposition process Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000010276 construction Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method for a semiconductor device which includes: providing a semiconductor substrate and forming gate structures on the semiconductor substrate and forming side-wall structures on the two sides of the gate structure; forming a groove in the semiconductor substrate at the two sides of the gate structures; forming a doped material layer so as to completely cover the side walls and bottom part of the groove; executing an annealing process so as to form a diffusion layer which surrounds the groove; and removing the doped material layer and forming an embedded germanium silicon layer in the groove. The manufacturing method for the semiconductor device is capable of reducing junction leakage of a border area of the embedded germanium silicon layer and the semiconductor substrate without affecting the performance of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method of junction leakage of the embedded germanium silicon area that reduces semiconductor device.
Background technology
In order to make to adopt 50nm to there is good performance with the semiconductor device of lower node technique manufacture, between the source/drain region of described semiconductor device and channel region, should form super shallow junction.For the PMOS part of described semiconductor device, conventionally in the source/drain region of PMOS part, form the carrier mobility that embedded germanium silicon improves the channel region of PMOS part, further to promote the performance of described semiconductor device.
Described embedded germanium silicon is generally ∑ shape, it adopts following processing step to form: first, need to combine and adopt dry etching and wet etching to form ∑ shape groove in the part that will form source/drain region of Semiconductor substrate, after described dry etching process finishes, in described source/drain region, form bowl-shape or perpendicular grooves; Then, utilize the difference of the etch-rate of wet etching on the different crystal orientations of described Semiconductor substrate, fast with respect to the level of described Semiconductor substrate and the etch-rate of vertical direction, the feature that other direction etch-rate is slow, bowl-shape or perpendicular grooves described in etching, to form ∑ shape groove in described Semiconductor substrate; Finally, adopt epitaxial growth technology in described ∑ shape groove, to form described embedded germanium silicon.In the region of described embedded germanium silicon and described Semiconductor substrate interfaces, there is larger junction leakage, it will reduce the performance of semiconductor device, and this is the problem of not expecting appearance.
Therefore, need to propose a kind of method, to reduce the junction leakage in the region of described embedded germanium silicon and described Semiconductor substrate interfaces, not affect the performance of semiconductor device.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure, and be formed with side wall construction in described grid structure both sides; In the Semiconductor substrate of described grid structure both sides, form groove; In described Semiconductor substrate, form a dopant material layer, to cover sidewall and the bottom of described groove completely; Carry out an annealing process, to form the diffusion layer that surrounds described groove; Remove described dopant material layer; In described groove, form embedded germanium silicon layer.
Further, described groove is ∑ shape or U-shaped.
Further, the technique that forms described dopant material layer is conformal deposition process.
Further, described conformal deposition process is atom layer deposition process or self-adjusting plasma deposition technique.
Further, described atom layer deposition process is induced with laser atom layer deposition process.
Further, the dopant in described dopant material layer comprises p type impurity.
Further, described p type impurity comprises the material of boron or boracic.
Further, the dosage of described p type impurity is 1.0 * 10
15-1.0 * 10
21atom/cm
3.
Further, in described annealing process, the dopant that is arranged in the sidewall of described groove and the dopant material layer on bottom is to described Semiconductor substrate diffusion and then form described diffusion layer.
Further, described annealing comprises laser annealing, peak value annealing or thermal annealing.
Further, the temperature of described annealing is 600-1500 ℃.
Further, adopt wet etching process to remove described dopant material layer.
Further, adopt epitaxial growth technology to form described embedded germanium silicon layer.
Further, after forming described embedded germanium silicon layer, also comprise the step of carrying out an Implantation annealing, with formation source/drain region in the Semiconductor substrate in described grid structure both sides.
Further, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer stacking gradually.
Further, described side wall construction comprises at least one oxide skin(coating) and/or at least one nitride layer.
According to the present invention, can reduce the junction leakage in the region of described embedded germanium silicon and described Semiconductor substrate interfaces, do not affect the performance of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 E is the schematic cross sectional view of each step of method of junction leakage of the embedded germanium silicon area of the minimizing semiconductor device that proposes of the present invention;
Fig. 2 is the flow chart of method of junction leakage of the embedded germanium silicon area of the minimizing semiconductor device that proposes of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the method for the junction leakage of the embedded germanium silicon area of the minimizing semiconductor device that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Below, the detailed step of method of junction leakage of the embedded germanium silicon area of the minimizing semiconductor device that the present invention proposes is described with reference to Figure 1A-Fig. 1 E and Fig. 2.
With reference to Figure 1A-Fig. 1 E, wherein show the schematic cross sectional view of each step of method of junction leakage of the embedded germanium silicon area of the minimizing semiconductor device that the present invention proposes.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to form.In described Semiconductor substrate 100, can also be formed with isolation channel, buried regions (not shown) etc.In addition, for PMOS, in described Semiconductor substrate 100, can also be formed with N trap (not shown), and before forming grid structure, can carry out once low dose of boron to whole N trap and inject, for adjusting the threshold voltage V of PMOS
th.
In described Semiconductor substrate 100, be formed with grid structure 101, as an example, described grid structure 101 can comprise gate dielectric, gate material layers and the grid hard masking layer stacking gradually from bottom to top.Gate dielectric can comprise oxide, as, silicon dioxide (SiO
2) layer.Gate material layers can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, and wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; Conductive metal oxide layer can comprise yttrium oxide (IrO
2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer.Grid hard masking layer can comprise one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon, wherein, oxide skin(coating) can comprise boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride layer can comprise silicon nitride (Si
3n
4) layer; Oxynitride layer can comprise silicon oxynitride (SiON) layer.
In addition,, as example, in described Semiconductor substrate 100, be also formed with and be positioned at described grid structure 101 both sides and near the side wall construction of described grid structure 101.Wherein, described side wall construction can comprise at least one oxide skin(coating) and/or at least one nitride layer.
Next, in the Semiconductor substrate 100 of described grid structure 101 both sides, form groove 102.Described groove 102 shown in Figure 1A is ∑ shape, and in other embodiments, described groove 102 also can take the shape of the letter U or other shape.In a preferred embodiment of the invention, the processing step that forms described ∑ shape groove 102 comprises: first adopt dry method etch technology to carry out longitudinal etching to the Semiconductor substrate 100 of described grid structure 101 both sides, to form groove in described Semiconductor substrate 100, in a preferred embodiment, the degree of depth of described groove is 300-700 dust, and the etching gas adopting is mainly HBr gas, power 300-500W, bias voltage 50-200V, temperature 40-60 ℃, the time determines according to etch depth; Then, adopt isotropic dry method etch technology to continue groove described in etching, making described groove transition is described bowl-shape groove, in a preferred embodiment, the innermost degree of depth of described bowl-shape groove is 400-800 dust, to the channel region of described Semiconductor substrate 200, the recessed degree of depth is 0-200 dust to its sidewall, adopts Cl
2and NF
3as main etching gas, power 100-500W, bias voltage 0-10V, temperature 40-60 ℃, time 5-50s; Finally, the etch-rate different characteristic (etch-rate in 100 and 110 crystal orientation higher than the etch-rate in 111 crystal orientation) of the etchant that utilizes wet etching on the different crystal orientations of the material of described Semiconductor substrate 100, bowl-shape groove is to form described ∑ shape groove 102 described in expansion etching.The temperature of described wet etching is 30-60 ℃, and the desired size of ∑ shape groove 102 described in basis of time and determining is generally 100-300s.
Then, as shown in Figure 1B, in described Semiconductor substrate 100, form a dopant material layer 103, to cover sidewall and the bottom of described groove 102 completely.The technique that forms described dopant material layer 103 is atom layer deposition process, preferred induced with laser atom layer deposition process (LI-ALD), or other conformal deposition process, for example self-adjusting plasma deposition technique (SRPD).Dopant in described dopant material layer 103 comprises p type impurity, the material of boron or boracic for example, and the dosage of described p type impurity is 1.0 * 10
15-1.0 * 10
21atom/cm
3.
Then, as shown in Figure 1 C, carry out an annealing process, so that be arranged in the dopant of the sidewall of described groove 102 and the dopant material layer 103 on bottom, to described Semiconductor substrate 100, spread, thereby form the diffusion layer 104 that surrounds described groove 102.Described annealing comprises laser annealing, peak value annealing or thermal annealing, and the temperature of described annealing is 600-1500 ℃.
Then,, as shown in Fig. 1 D, remove described dopant material layer 103.The various suitable technique that described removal process can be had the knack of by those skilled in the art completes, for example wet etching process.
Then,, as shown in Fig. 1 E, adopt epitaxial growth technology in described groove 102, to form embedded germanium silicon layer 105.Described epitaxial growth technology can adopt a kind of in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and molecular beam epitaxy (MBE).In order to ensure the channel region of semiconductor device is applied to suitable stress, described embedded germanium silicon layer 105 conventionally all can be higher than the upper surface of described Semiconductor substrate 100.
Next, carry out an Implantation annealing, with formation source/drain region (not shown) in the Semiconductor substrate 100 in described grid structure 101 both sides.
So far, completed whole processing steps that method is implemented according to an exemplary embodiment of the present invention, next, can by subsequent technique, complete the making of whole semiconductor device, described subsequent technique is identical with traditional process for fabricating semiconductor device.According to the present invention, by forming the diffusion layer that comprises p type impurity of the embedded germanium silicon layer of an encirclement, suppress the junction leakage in the region of embedded germanium silicon and Semiconductor substrate interfaces, unaffected to guarantee the performance of semiconductor device.
With reference to Fig. 2, wherein show the flow chart of method of junction leakage of the embedded germanium silicon area of the minimizing semiconductor device that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, in described Semiconductor substrate, be formed with grid structure, and be formed with side wall construction in described grid structure both sides;
In step 202, in the Semiconductor substrate of described grid structure both sides, form groove;
In step 203, in described Semiconductor substrate, form a dopant material layer, to cover sidewall and the bottom of described groove completely;
In step 204, carry out an annealing process, to form the diffusion layer that surrounds described groove;
In step 205, remove described dopant material layer;
In step 206, in described groove, form embedded germanium silicon layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure, and be formed with side wall construction in described grid structure both sides;
In the Semiconductor substrate of described grid structure both sides, form groove;
In described Semiconductor substrate, form a dopant material layer, to cover sidewall and the bottom of described groove completely;
Carry out an annealing process, to form the diffusion layer that surrounds described groove;
Remove described dopant material layer;
In described groove, form embedded germanium silicon layer.
2. method according to claim 1, is characterized in that, described groove is ∑ shape or U-shaped.
3. method according to claim 1, is characterized in that, the technique that forms described dopant material layer is conformal deposition process.
4. method according to claim 3, is characterized in that, described conformal deposition process is atom layer deposition process or self-adjusting plasma deposition technique.
5. method according to claim 4, is characterized in that, described atom layer deposition process is induced with laser atom layer deposition process.
6. according to the method described in claim 1 or 3, it is characterized in that, the dopant in described dopant material layer comprises p type impurity.
7. method according to claim 6, is characterized in that, described p type impurity comprises the material of boron or boracic.
8. method according to claim 6, is characterized in that, the dosage of described p type impurity is 1.0 * 10
15-1.0 * 10
21atom/cm
3.
9. method according to claim 1, is characterized in that, in described annealing process, the dopant that is arranged in the sidewall of described groove and the dopant material layer on bottom is to described Semiconductor substrate diffusion and then form described diffusion layer.
10. method according to claim 1, is characterized in that, described annealing comprises laser annealing, peak value annealing or thermal annealing.
11. methods according to claim 1, is characterized in that, the temperature of described annealing is 600-1500 ℃.
12. methods according to claim 1, is characterized in that, adopt wet etching process to remove described dopant material layer.
13. methods according to claim 1, is characterized in that, adopt epitaxial growth technology to form described embedded germanium silicon layer.
14. methods according to claim 1, is characterized in that, after forming described embedded germanium silicon layer, also comprise the step of carrying out an Implantation annealing, with formation source/drain region in the Semiconductor substrate in described grid structure both sides.
15. methods according to claim 1, is characterized in that, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer stacking gradually.
16. methods according to claim 1, is characterized in that, described side wall construction comprises at least one oxide skin(coating) and/or at least one nitride layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080032468A1 (en) * | 2006-08-01 | 2008-02-07 | United Microelectronics Corp. | Mos transistor and fabrication thereof |
| CN101593702A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The manufacture method of stress metal oxide semiconductor device |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080032468A1 (en) * | 2006-08-01 | 2008-02-07 | United Microelectronics Corp. | Mos transistor and fabrication thereof |
| CN101593702A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The manufacture method of stress metal oxide semiconductor device |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
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