CN101593702A - The manufacture method of stress metal oxide semiconductor device - Google Patents
The manufacture method of stress metal oxide semiconductor device Download PDFInfo
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- CN101593702A CN101593702A CNA2008101140009A CN200810114000A CN101593702A CN 101593702 A CN101593702 A CN 101593702A CN A2008101140009 A CNA2008101140009 A CN A2008101140009A CN 200810114000 A CN200810114000 A CN 200810114000A CN 101593702 A CN101593702 A CN 101593702A
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Abstract
A kind of manufacture method of stress metal oxide semiconductor device comprises: the semiconductor-based end with gate stack is provided; Carry out first step etching,, in the semiconductor-based end of described gate stack both sides, form groove with the semiconductor-based end of the described gate stack of etching both sides; Carry out the second step etching, with the described groove of etching to target depth; The described groove of etching forms strained epilayer in described groove to target depth, this epitaxial loayer makes the semiconductor-based end of gate stack bottom produce stress; Wherein, described first step etching is a dry etching, and the second step etching is a wet etching.Micro loading effect when the present invention can improve etching groove in the manufacturing of stress metal oxide semiconductor device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of stress metal oxide semiconductor device.
Background technology
Strain gauge technique can be applicable in the manufacturing process of metal oxide semiconductor device, to improve the performance of the metal oxide semiconductor device that forms.For example, in the conducting channel of N type metal oxide semiconductor device (NMOS), apply the electron mobility that tensile stress (Tensile stress) can improve this NMOS, in the conducting channel of P-type mos device (PMOS), apply compression (Compressive stress) and can improve the mobility in hole.
At publication number is in the Chinese patent application file of CN1830092A, a kind of method of the PMOS of raising device electron mobility is disclosed, it is by forming the epitaxial loayer of silicon germanium material in the source-drain electrode of PMOS device, thereby improve the compression in the conducting channel in the PMOS device, to improve electron mobility.Fig. 1 to Fig. 4 is the generalized section of each step corresponding structure of described Chinese patent application file disclosed method.
Please refer to Fig. 1, the semiconductor-based end 14 is provided, the described semiconductor-based end 14 can be a single crystal silicon material.On the described semiconductor-based end 14, be formed with the gate stack 25 of PMOS device and the gate stack 45 of nmos device.Gate stack 25 comprises sept 29 and the insulator cap layer 50 that gate dielectric 13, grid conductor layer 26 and sidewall thereof form.Gate stack 45 comprises sept 47 and the insulator cap layer 52 that gate dielectric 13, grid conductor layer 42 and sidewall thereof form.In the described semiconductor-based end 14, also has isolation structure 17.
Then, please refer to Fig. 2, on the surface 54 at the described semiconductor-based end 14, form cover layer 56.Described cover layer 56 can be a silicon nitride, and it forms by depositing operation.
Then, please refer to Fig. 3, on the described semiconductor-based end 14, form masking layer 58 and carry out composition, covering the zone on the nmos device, but do not cover the zone on the PMOS device.Described masking layer 58 preferably can be a photoresist.
Carry out anisotropic etch process, this etching technics can be that (ReactiveIon Etch RIE), the semiconductor-based end 14 of the both sides of etching gate stack 25, forms groove 60 to reactive ion etching.In etching process, gate stack 25 avoids the zone under this gate stack 25 to be etched as mask.Because masking layer 58 protections, the nmos device zone can not be etched.
Please refer to Fig. 4, in described groove, form germanium-silicon layer 62 and monocrystalline silicon layer 66 by selective epitaxial growth process.Further, form the other parts of nmos device and PMOS device.
In the described method, by forming germanium-silicon layer 62, can improve the mobility of charge carrier rate in the conducting channel of this PMOS device, thereby can improve the performance of this device at the source and drain areas of PMOS device.Yet, in the described method, form groove 60 by reactive ion etching, when 45nm even littler technology node are used this method, because the micro loading effect (Micro-loading effect) of reactive ion etching, be difficult to etch and satisfy the groove 60 that the degree of depth requires, and cause etch period longer, efficient is lower.
Summary of the invention
The invention provides a kind of manufacture method of stress metal oxide semiconductor device, the micro loading effect in the time of can improving etching groove in the manufacturing of stress metal oxide semiconductor device.
The manufacture method of a kind of stress metal oxide semiconductor device provided by the invention comprises:
The semiconductor-based end with gate stack, be provided;
Carry out first step etching, the semiconductor-based end of the described gate stack of etching both sides, in the semiconductor-based end of described gate stack both sides, form groove;
Carry out the second step etching, with the described groove of etching to target depth;
The described groove of etching forms strained epilayer in described groove to target depth;
Wherein, described first step etching is a dry etching, and the second step etching is a wet etching.
Optionally, described first step etching is a reactive ion etching.
Optionally, before carrying out the second step etching,
Also comprise successively the trenched side-wall carried out, form after the described first step etching of etching and the 3rd step etching and the 4th step etching of bottom,
Wherein, described the 3rd step etching is a wet etching, and the 4th step etching is a reactive ion etching.
Optionally, before carrying out the described second step etching, also comprise wet etching step and reactive ion etching step that multi-section is alternately carried out.
Optionally, the etching solution of described wet etching is the aqueous solution of potassium hydroxide and isopropyl alcohol.
Optionally, the target depth of described groove is 500 to 1000 dusts.
Optionally, when described device was N type metal oxide semiconductor device, described epitaxial loayer was a silicon carbon material; When described device was the P-type mos device, described epitaxial loayer was a silicon germanium material.
Optionally, when described device was the P-type mos device, described epitaxial loayer was a silicon germanium material, and the ratio of SiGe is 1: 9 to 3: 7 in the wherein said epitaxial loayer.
Optionally, when forming described epitaxial loayer, carry out in-situ doped or the ex situ doping, in described epitaxial loayer, mix impurity.
Optionally, form described epitaxial loayer after, to carrying out annealing process in the described semiconductor-based end.
Compared with prior art, the present invention has the following advantages:
At the semiconductor-based end of etching gate stack, when being formed for the groove of deposit epitaxial layers, carry out two step etching technics, the first step is a dry etching, second step was wet etching; By the described first step is anisotropic dry etching, and etch rate is very fast, and the groove that etches has more straight side wall profile; Wet etching by second step, clean in the anti-dry etch process at the polymer of trenched side-wall that etches and bottom and the accessory substance of generation, and then described channel bottom and sidewall are carried out etching, when described gash depth is increased, groove is etched at horizontal (along conducting channel), make the groove and the gate stack that form have overlapping, this overlapping makes the strained epilayer of follow-up filling and gate stack have overlapping, thereby make source electrode and drain electrode and gate stack have overlapping, can improve the performance of the semiconductor device of formation; That is to say, can improve the micro loading effect of reactive ion etching, improve etch rate by described two step etchings, and, can control the side wall profile of the groove of formation preferably, help to form the groove that side wall profile meets the demands;
In addition, adopt wet-etching technology can reduce the damage of only adopting dry etching to cause to the semiconductor substrate.
Description of drawings
Fig. 1 to Fig. 4 is existing a kind of generalized section that improves each step corresponding construction of method of PMOS device electron mobility;
Fig. 5 is the flow chart of embodiment of the manufacture method of stress metal oxide semiconductor device of the present invention;
Fig. 6 is for having the generalized section of the semiconductor device of gate stack in the embodiments of the invention;
Fig. 7 is to forming the generalized section of structure after the first step etching in the semiconductor-based end execution embodiments of the invention shown in Figure 6;
Fig. 8 is to forming the generalized section of structure after the second step etching in the semiconductor-based end execution embodiments of the invention shown in Figure 6;
Fig. 9 is a generalized section behind the formation epitaxial loayer in the groove of semiconductor structure shown in Figure 8.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail, for ease of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this; The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Source electrode and drain region at metal oxide semiconductor device form the epitaxial loayer (or being called strained epilayer) that produces strain in the conducting channel that can make between source electrode and the drain electrode, can improve the mobility of charge carrier rate.For example, form the epitaxial loayer of silicon germanium material in the source electrode of PMOS device and drain region, can improve the mobility in hole in the conducting channel of this PMOS device; Form the epitaxial loayer of silicon nitride material in the source electrode of nmos device and drain electrode, can improve the mobility of electronics in the conducting channel of this nmos device.In the existing processes, general earlier by source electrode and the drain region formation groove of reactive ion etching at metal oxide semiconductor device, and then, in groove, fill corresponding strained epilayer material according to the type (N type or P type) of the metal oxide semiconductor device that will form.Yet, because size of devices is constantly reducing, the size of corresponding described groove is also dwindled gradually, when forming groove by reactive ion etching, because micro loading effect, speed of etching increases along with etching depth and descends, and is difficult to etch the groove that satisfies degree of depth requirement, and etch period is long, and efficient is low.
A kind of manufacture method of stress metal oxide semiconductor device is provided among the present invention, by carrying out at least two step etchings and in described two step etchings, having at least a step to be the method etching source and the drain region of wet etching for dry etching, a step, form groove, then in described groove, fill the strained epilayer material; Carry out follow-up technology then, form stress metal oxide semiconductor device.In the described method, the step that adds wet etching, can improve existing micro loading effect when only adopting reactive ion etching, and can reduce etching injury to the semiconductor substrate, but and the side wall profile of the groove that forms of better controlled and groove in the laterally extension of (along the conducting channel direction).
Fig. 5 is the flow chart of the manufacture method embodiment of stress metal oxide semiconductor device of the present invention.Please refer to Fig. 5, step S100 is for providing the semiconductor-based end with gate stack.
Step S110 with the semiconductor-based end of the described gate stack of etching both sides, forms groove for carrying out first step etching in the semiconductor-based end of described gate stack both sides.
Step S120 is for carrying out the second step etching, with the described groove of etching to target depth.
Step S130 be the described groove of etching to target depth, in described groove, form strained epilayer.
Wherein, described first step etching is a dry etching, and the second step etching is a wet etching.
Be described in detail below in conjunction with the manufacture method of specific embodiment stress metal oxide semiconductor of the present invention.In the present embodiment, with strain PMOS device is that example describes, but it should unsuitable restriction claim scope, those skilled in the art are under the condition of the scope that does not deviate from claim, with recognize many other distortion, substitute or revise, for example, the manufacture method of metal oxide semiconductor device of the present invention can be applied to the manufacturing process of strain NMOS device, or the manufacturing process of stress CMOS device etc.When the method for using embodiments of the invention is made stress CMOS device, when the corresponding groove of etching N MOS or PMOS device, need protect other device by cover layer, repeat no more here, those skilled in the art can make corresponding change.
Fig. 6 to Fig. 9 is the generalized section of each step corresponding structure of manufacture method of strain PMOS device of the present invention.
Please refer to Fig. 6, the semiconductor-based end 100 with gate stack is provided.
The described semiconductor-based end 100 is a monocrystalline silicon, or has on the insulating barrier epitaxial layer structure on silicon or the silicon.The described semiconductor-based end 100, can also be other material or have other structure.
Have N trap 102 in the described semiconductor-based end 100, described N trap 102 forms by ion implantation technology, and the foreign ion that wherein mixes can be phosphorus or arsenic, or other material.
In the described semiconductor-based end 100, also has isolation structure, as specific embodiment, described isolation structure can be a fleet plough groove isolation structure, this fleet plough groove isolation structure can form with those skilled in the art's technology known, the dielectric of filling in this fleet plough groove isolation structure is silica or silicon nitride or its combination, also can be other material.Described fleet plough groove isolation structure is used to isolate active area, with in active area or on make metal oxide semiconductor device.
On the described semiconductor-based end 100, be formed with the gate stack of gate dielectric layer 106 and grid conductive layer 108.Wherein said gate dielectric layer 106 is silica or silicon oxynitride.Can adopt for example gate dielectric layer 106 of formation silica materials such as furnace oxidation, rapid thermal annealing oxidation (RTO), original position steam oxidation (ISSG) of those skilled in the art's oxidation technology known.Silica is carried out nitriding process can form silicon oxynitride, wherein, described nitriding process can be high temperature furnace pipe nitrogenize, rapid thermal annealing nitrogenize or pecvd nitride, certainly, can also adopt other nitriding process, repeats no more here.
Described grid conductive layer 108 can be the laminated construction of polycrystalline silicon material or polysilicon and metal silicide, or metal material, the perhaps laminated construction of polysilicon and dielectric layer, those skilled in the art can recognize many other distortion, substitute or modification, give unnecessary details no longer one by one here.In polycrystalline silicon material, can also mix impurity, resistivity with the grid that reduces to form, for example, grid for PMOS burning silicon semiconductor device, can in polysilicon, mix boron, for the grid of NMOS metal oxide semiconductor device, can in polysilicon, mix phosphorus or arsenic.
Described gate stack can comprise the side wall layer 110 and/or the insulator cap layer on the grid conductive layer 108 (figure does not show) of grid conductive layer 108 sidewalls.Described side wall layer 110 can be silica or the laminated construction of silicon nitride or silica and silicon nitride (ON) or laminated construction or other structure of silica, silicon nitride and silica (ONO).Described insulator cap layer can be silicon nitride or silica.
Please refer to Fig. 7, carry out first step etching, the semiconductor-based end 100 of the described gate stack of etching both sides, in the semiconductor-based end 100 of described gate stack, form groove 112.
Wherein, described first step etching is a dry etching, for example can be reactive ion etching, and etching gas can be the gas of chloride and/or fluorine, for example CCl
2, BCl
3, Cl
2, SiCl
4, C
2F
6, SF
6, CF
4Deng.
Then, carry out the second step etching, the described groove of etching 112 is to target depth, and this target depth is according to the electrology characteristic decision of metal oxide semiconductor device, and for example, the target depth of described groove can be 500 to 100 dusts.Wherein, the described second step etching is a wet etching, and wherein, the etching solution of described wet etching can be to contain solution hydroxy, for example ammonia spirit, the perhaps aqueous solution of potassium hydroxide and isopropyl alcohol.
The described first step is anisotropic reactive ion etching, and etch rate is very fast, and the groove that etches has more straight side wall profile.Along with the increase of etching depth, the speed of reactive ion etching can descend gradually; Execution wet etching by second step, clean out on the one hand in the reactive ion etching process that (this polymer and accessory substance are difficult in reactive ion etching process to be removed in by described groove at the polymer of groove 112 sidewalls that etch and bottom and the accessory substance of generation, thereby can cause reactive ion etching speed to descend, and, along with etching depth increases, the difficulty that described polymer and accessory substance are removed increases), and described groove 112 bottoms and sidewall are carried out etching, because wet etching is for waiting tropism's etching, thereby, when described groove 112 degree of depth are increased, groove 112 is etched at horizontal (along conducting channel), as shown in Figure 8, make groove 112 and described gate stack have overlapping, this overlapping makes the strained epilayer of follow-up filling and gate stack have overlapping, thereby makes source electrode and drain electrode and gate stack have overlapping, can improve the performance of the semiconductor device of formation.
That is to say, can improve the micro loading effect of reactive ion etching by wet etching, improve etch rate, and, can control the side wall profile of the groove of formation preferably, help to form the groove that side wall profile meets the demands, in addition, adopt wet-etching technology can reduce the damage of only adopting reactive ion etching to cause semiconductor substrate 100.
In a further embodiment, before carrying out the second step etching, also comprise the 3rd step etching and the 4th step etching carried out successively, wherein, described the 3rd step etching is a wet etching, and the 4th step etching is a reactive ion etching.By alternately carrying out reactive ion etching and wet etching, can further improve control, and effectively improve micro loading effect groove contour.
In a further embodiment, before carrying out the described second step etching, also comprise wet etching step and reactive ion etching step that multi-section is alternately carried out.Reactive ion etching and wet etching step by multi-section are alternately carried out; can form the groove 112 that the degree of depth and side wall profile meet the demands with fast speeds; improve micro loading effect; here no longer give unnecessary details; those skilled in the art can instruction according to the present invention make corresponding change, substitute and change, and the method for Huo Deing should be included within protection scope of the present invention therefrom.
Please refer to Fig. 9, form strained epilayer 114 in described groove 112, described strained epilayer 114 can make the semiconductor-based end (i.e. the conducting channel of the metal oxide semiconductor device of Xing Chenging) of described gate stack bottom produce stress.
In the present embodiment, the strained epilayer 114 that forms in described groove 112 can make and form compression in the conducting channel.Described strained epilayer 114 can be a silicon germanium material, and the ratio of SiGe is to be 1: 9 to 3: 7 in the wherein said epitaxial loayer.The method of its formation can be selective epitaxial growth process (Selective Epitaxial Growth, SEG) or other vapor phase epitaxial growth technology or other epitaxy technique, it will be recognized by those skilled in the art many changes, substitute or alter mode, enumerate no longer one by one here.
In addition, when forming the epitaxial loayer 114 of described silicon germanium material, can original position mix impurity material, in the present embodiment, can mix impurity such as boron.
In addition, when the method for using described embodiment forms strain NMOS, described epitaxial loayer is a carbofrax material, its formation method can adopt selective epitaxial growth process or other process for vapor phase epitaxy or other epitaxy technique, it will be recognized by those skilled in the art many changes, substitute or alter mode, enumerate no longer one by one here.
After forming described strained epilayer 114, carry out annealing process.
In addition,, do not have in-situ dopedly, can carry out ion implantation technology, in described strained epilayer 114, mix foreign ion if when forming described strained epilayer 114, boron for example, and then carry out annealing process.Here repeat no more.
Form described strained epilayer 114 and carry out after the annealing, on described strained epilayer 114 and form metal silicide on the grid, for example nickle silicide, cobalt silicide or titanium silicide etc.Can adopt those skilled in the art's method known to form, repeat no more here.
Then, carry out other step that forms metal oxide semiconductor device, give unnecessary details no longer one by one here.
In the described embodiment method, by at least one step dry etching and at least one step wet etching, form the source electrode of strain PMOS and the groove 112 of drain region, can improve micro loading effect, plasma etching damage when reducing only to adopt reactive ion etching, help forming the groove that side wall profile meets the demands and can raise the efficiency.
In addition; need to prove; above-mentioned step only is to utilize the manufacturing process of strain PMOS that the manufacture method of stress metal oxide semiconductor device of the present invention is described as embodiment; it should be as the restriction to the claim protection range; under the condition of the protection range that does not deviate from claim; those skilled in the art instruct according to an embodiment of the invention can be to the interpolation of the step of the above embodiments, remove, be equal to and replace or the change of order, and these all should be included within protection scope of the present invention.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1, a kind of manufacture method of stress metal oxide semiconductor device is characterized in that, comprising:
The semiconductor-based end with gate stack, be provided;
Carry out first step etching, the semiconductor-based end of the described gate stack of etching both sides, in the semiconductor-based end of described gate stack both sides, form groove;
Carry out the second step etching, with the described groove of etching to target depth;
The described groove of etching forms strained epilayer in described groove to target depth;
Wherein, described first step etching is a dry etching, and the second step etching is a wet etching.
2, the manufacture method of stress metal oxide semiconductor device as claimed in claim 1 is characterized in that: described first step etching is a reactive ion etching.
3, the manufacture method of stress metal oxide semiconductor device as claimed in claim 2 is characterized in that: before carrying out the second step etching,
Also comprise successively the trenched side-wall carried out, form after the described first step etching of etching and the 3rd step etching and the 4th step etching of bottom,
Wherein, described the 3rd step etching is a wet etching, and the 4th step etching is a reactive ion etching.
4, the manufacture method of stress metal oxide semiconductor device as claimed in claim 1 is characterized in that: before carrying out the described second step etching, also comprise wet etching step and reactive ion etching step that multi-section is alternately carried out.
5, as the manufacture method of the described stress metal oxide semiconductor device of the arbitrary claim of claim 1 to 4, it is characterized in that: the etching solution of described wet etching is the aqueous solution of potassium hydroxide and isopropyl alcohol.
6, as the manufacture method of the described stress metal oxide semiconductor device of the arbitrary claim of claim 1 to 4, it is characterized in that: the target depth of described groove is 500 to 1000 dusts.
7, as the manufacture method of the described stress metal oxide semiconductor device of the arbitrary claim of claim 1 to 4, it is characterized in that: when described device was N type metal oxide semiconductor device, described epitaxial loayer was a silicon carbon material; When described device was the P-type mos device, described epitaxial loayer was a silicon germanium material.
8, as the manufacture method of the described stress metal oxide semiconductor device of the arbitrary claim of claim 1 to 4, it is characterized in that: when described device is the P-type mos device, described epitaxial loayer is a silicon germanium material, and the ratio of SiGe is 1: 9 to 3: 7 in the wherein said epitaxial loayer.
9, the manufacture method of stress metal oxide semiconductor device as claimed in claim 1 is characterized in that: carry out in-situ doped when forming described epitaxial loayer or the ex situ doping, mix impurity in described epitaxial loayer.
10, the manufacture method of stress metal oxide semiconductor device as claimed in claim 1 is characterized in that: after forming described epitaxial loayer, to carrying out annealing process in the described semiconductor-based end.
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| CN101593702B (en) | 2010-12-22 |
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