CN103678750B - The radiofrequency model method of silicon via-hole array structure - Google Patents
The radiofrequency model method of silicon via-hole array structure Download PDFInfo
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Abstract
The invention discloses a kind of radiofrequency model method of silicon via-hole array structure, for setting up the radiofrequency model of silicon via-hole array structure, silicon via-hole array structure includes multiple bar shaped silicon through hole arranged in parallel.The inventive method take into account stray inductance, dead resistance and the Kelvin effect of bar shaped silicon through hole in silicon via-hole array structure, and the mutual inductance that the coupling between bar shaped silicon through hole is between electric capacity, bar shaped silicon through hole, and silicon through hole and the parasitic capacitance of substrate, and body effect etc., can well characterize the high-frequency characteristic of silicon via-hole array structure, simulate the relation of the stray inductance of silicon via-hole array structure, parasitic capacitance and frequency accurately.
Description
Technical field
The present invention relates to the model method of a kind of semiconductor integrated circuit, particularly relate to a kind of radiofrequency model method of silicon via-hole array structure.
Background technology
Silicon through hole (Through Si via, TSV) technique is a kind of emerging ic manufacturing process, as it is shown in figure 1, be the structure photo of existing silicon through hole；By be produced on the circuit of silicon chip 101 upper surface by the metal filled in silicon through hole 102 be connected to silicon chip 101 back side and and be formed at silicon chip 101 metal layer on back 103 and connect, thus the circuit of silicon chip 101 upper surface is drawn from the back side of silicon chip 101.Silicon via process combines three-dimension packaging technique so that IC layout is arranged side by side from conventional two-dimensional and develops into the most advanced three-dimensional stacked, and such component encapsulation is the compactest, is shortened by chip lead distance, can improve frequency characteristic and the power characteristic of circuit greatly.Silicon via process is widely used, and is suitable as many-sided device performance and promotes.As used it for WLAN and mobile phone intermediate power amplifier, frequency characteristic and the power characteristic of circuit will be improved greatly.
The introducing of silicon through hole can produce stray inductance and dead resistance, as shown in Figure 2, it it is the radiofrequency model of the radiofrequency model method of existing silicon through hole, this radiofrequency model is typically only applicable to the silicon through hole of block structure, the silicon through hole of block structure is isolated structure one by one, the spacing of each silicon through hole is remote, does not interact, and radiofrequency model includes:
Dead resistance R of silicon through hole and stray inductance L, dead resistance R and stray inductance L are connected between upper port and the lower port of silicon through hole.
Parasitic capacitance C between upper port position silicon through hole and substrate and stray inductance G, at lower port seat parasitic capacitance C between silicon through hole and substrate and stray inductance G.Parasitic capacitance C and stray inductance G at upper and lower port are connected in parallel between upper and lower port and ground respectively.
As shown in Figure 3A, it is the inductance using radiofrequency model as shown in Figure 2 to obtain and the relation curve of frequency；As shown in Figure 3 B, it is the resistance using radiofrequency model as shown in Figure 2 to obtain and the relation curve of frequency.The curve of Fig. 3 A and Fig. 3 B can be fine with what the inductance of silicon through hole of block structure and the frequecy characteristic of resistance met.
But in the actual application of silicon through hole, and being limited only to block structure, be additionally included on vertical view face, silicon through hole is in strip structure, and the situation of multiple bar shaped silicon sets of vias integrated array structure.For silicon via-hole array structure, influencing each other owing to can produce between each neighbouring bar shaped silicon through hole, using the radiofrequency model in Fig. 2 is the high frequency characteristics that cannot simulate silicon via-hole array structure.
Summary of the invention
The technical problem to be solved is to provide a kind of radiofrequency model method of silicon via-hole array structure, can well characterize the high-frequency characteristic of silicon via-hole array structure, simulates the relation of the stray inductance of silicon via-hole array structure, parasitic capacitance and frequency accurately.
For solving above-mentioned technical problem, the radiofrequency model method of the silicon via-hole array structure that the present invention provides is for setting up the radiofrequency model of silicon via-hole array structure, multiple bar shaped silicon through holes composition that described silicon via-hole array structure is formed from silicon substrate, described bar shaped silicon through hole is bar shaped silicon through hole one, each described bar shaped silicon through hole one is equally spaced arranged in parallel, the length of each described bar shaped silicon through hole one is equal, width is equal, and each described bar shaped silicon through hole one is mutually aligned with；nullOr，Multiple bar shaped silicon through holes composition that described silicon via-hole array structure is formed from silicon substrate，Described bar shaped silicon through hole includes multiple bar shaped silicon through hole one、Two bar shaped silicon through holes two and two bar shaped silicon through holes three，Each described bar shaped silicon through hole one is equally spaced arranged in parallel，The length of each described bar shaped silicon through hole one is equal、Width is equal，Each described bar shaped silicon through hole one is mutually aligned with，Described bar shaped silicon through hole two and described bar shaped silicon through hole three are surrounded on the outside of the homogeneous texture being made up of described bar shaped silicon through hole one，And described bar shaped silicon through hole two is parallel with described bar shaped silicon through hole one、And the length of described bar shaped silicon through hole two is more than the length of described bar shaped silicon through hole one，Described bar shaped silicon through hole three and described bar shaped silicon through hole one are vertical、And the length of described bar shaped silicon through hole three is more than the length of the homogeneous texture being made up of described bar shaped silicon through hole one，Described bar shaped silicon through hole two is identical with the width of described bar shaped silicon through hole one with the width of described bar shaped silicon through hole three.Described radiofrequency model includes:
Two ports, port one represents that the upper end of each described bar shaped silicon through hole, port two represent the lower end of each described bar shaped silicon through hole；The upper end of all described bar shaped silicon through holes all links together, the lower end of all described bar shaped silicon through holes all links together.
First inductance element and the second inductance element, for characterizing formed two stray inductances of described silicon via-hole array structure；There is mutual inductance between described first inductance element and described second inductance element, mutual inductance is K.
First coupling capacitance element and the second coupling capacitance element, described first coupling capacitance element is for characterizing the coupling electric capacity of the position of the close described port one of described silicon via-hole array structure, and described second coupling capacitance element is for characterizing the coupling electric capacity of the position of the close described port two of described silicon via-hole array structure.
Two ladder resistances and inductance network, for characterize described silicon via-hole array structure the dead resistance of bar shaped silicon through hole and Kelvin effect；First ladder resistance and inductance network be formed in parallel by N level electronic circuit, every one-level electronic circuit is in series by a sub-resistance and sub-inductance, second ladder resistance and inductance network be formed in parallel by N level electronic circuit, every one-level electronic circuit is in series by a sub-resistance and sub-inductance, N be more than or equal to 2.
Described first inductance element and described first ladder resistance and inductance network are series between described port one and described port two, and described second inductance element and described second ladder resistance and inductance network are series between described port one and described port two；The two ends of described first coupling capacitance element are all connected with described port one, and the two ends of described second coupling capacitance element are all connected with described port two.
Further improve and be, the inductance value of described first inductance element and described second inductance element is equal, and the inductance value of described first inductance element or described second inductance element is between 1.6 times to 2 times of the inductance value between port one and the port two of the sample of the described silicon via-hole array structure obtained under the test condition of 100MHz or frequencies below；K is between 0 to 1.
Further improving is that the capacitance of described first coupling capacitance element and described second coupling capacitance element is equal, and the formula of the capacitance of described first coupling capacitance element or described second coupling capacitance element is: Ccoupling1=Ccoupling2=n × w × w × ε/t, wherein Ccoupling1For the capacitance of described first coupling capacitance element, Ccoupling2For the capacitance of described second coupling capacitance element, n is the number of bar shaped silicon through hole in array, and w is the width of single bar shaped silicon through hole, and t is the degree of depth of single bar shaped silicon through hole, and ε is the dielectric coefficient of the silicon medium between bar shaped silicon through hole.
Further improving and be, from the first order electronic circuit of described first ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels increases successively and the value of sub-inductance at different levels reduces successively；From the first order electronic circuit of described second ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels increases successively and the value of sub-inductance at different levels reduces successively.
Further improve and be, N is equal to 4, described first ladder resistance is identical with the value of the sub-resistance of the same stages of inductance network with the at different levels sub-resistance of inductance network and described second ladder resistance, and described first ladder resistance is identical with the value of the sub-inductance of the same stages of inductance network with the at different levels sub-inductance of inductance network and described second ladder resistance；Described first ladder resistance and inductance network or described second ladder resistance are obtained by equation below with the at different levels sub-resistance of inductance network:
Wherein, αR=2.1246, x are between 1 to 2；RDCFor the dead resistance between port one and the port two of the sample of described silicon via-hole array structure obtained under the test condition of 100MHz or frequencies below, or RDCFor the resistance value obtained by the resistivity of each bar shaped silicon through hole of described silicon via-hole array structure and sectional area and depth calculation； R1For the sub-resistance value of the first order, R2For the sub-resistance value in the second level, R3For the sub-resistance value of the third level, R4For the sub-resistance value of the fourth stage；L1For the sub-inductance value of the first order, L2For the sub-inductance value in the second level, L3For the sub-inductance value of the third level, L4For the sub-inductance value of the fourth stage.
Described first ladder resistance and inductance network or described second ladder resistance are obtained by equation below with the at different levels sub-inductance of inductance network: Wherein LmainFor described first inductance element or the inductance value of described second inductance element.
Further improving and be, from the first order electronic circuit of described first ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels reduces successively and the value of sub-inductance at different levels increases successively；From the first order electronic circuit of described second ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels reduces successively and the value of sub-inductance at different levels increases successively.
Further improving is that described radiofrequency model also includes:
Parasitic capacitance between described bar shaped silicon through hole and the silicon substrate of described silicon via-hole array inside configuration of described silicon via-hole array structure, including the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity and the 6th electric capacity.
Parasitic capacitance between described bar shaped silicon through hole and the silicon substrate of described silicon via-hole array structural outer of described silicon via-hole array structure, including the 7th electric capacity, the 8th electric capacity, the 9th electric capacity and the tenth electric capacity.
The inner foundation network element of described silicon via-hole array structure, including inner foundation electric capacity and inner foundation resistance.
The external substrate network element of described silicon via-hole array structure, including the first external substrate electric capacity and the first external substrate resistance, second external substrate electric capacity and the second external substrate resistance, 3rd external substrate electric capacity and the 3rd external substrate resistance, the 4th external substrate electric capacity and the 4th external substrate resistance.
Described inner foundation electric capacity and described inner foundation resistor coupled in parallel connect, first end of described 3rd electric capacity is connected with described port one, the second end of described 3rd electric capacity is connected with the first end of described inner foundation electric capacity, and the first end of described 4th electric capacity is connected with described port two, the second end of described 4th electric capacity is connected with the first end of described inner foundation electric capacity；First end of described 5th electric capacity is connected with described port one, the second end of described 5th electric capacity is connected with the second end of described inner foundation electric capacity, and the first end of described 6th electric capacity is connected with described port two, the second end of described 6th electric capacity is connected with the second end of described inner foundation electric capacity.
Described first external substrate electric capacity and the first external substrate resistor coupled in parallel connect and the first end ground connection of described first external substrate electric capacity, described second external substrate electric capacity and the second external substrate resistor coupled in parallel connect and the first end ground connection of described second external substrate electric capacity, described 3rd external substrate electric capacity and the 3rd external substrate resistor coupled in parallel connect and the first end ground connection of described 3rd external substrate electric capacity, and described 4th external substrate electric capacity and the 4th external substrate resistor coupled in parallel connect and the first end ground connection of described 4th external substrate electric capacity.
First end of described 7th electric capacity is connected with described port one, second end of described 7th electric capacity is connected with the second end of described first external substrate electric capacity, first end of described 8th electric capacity is connected with described port two, second end of described 8th electric capacity is connected with the second end of described second external substrate electric capacity, first end of described 9th electric capacity is connected with described port one, second end of described 9th electric capacity is connected with the second end of described 3rd external substrate electric capacity, first end of described tenth electric capacity is connected with described port two, second end of described tenth electric capacity is connected with the second end of described second external substrate electric capacity.
Further improving is that the capacitance of described 3rd electric capacity, described 4th electric capacity, described 5th electric capacity and described 6th electric capacity is equal and this capacitance is determined by equation below:Wherein, t is the degree of depth of single bar shaped silicon through hole, l1For the inside length sum of all bar shaped silicon through holes, w1For the inboard width sum of all bar shaped silicon through holes, CsubFor the unit-area capacitance of substrate, kcBetween 2-5.
Further improving is that the capacitance of described 7th electric capacity, described 8th electric capacity, described 9th electric capacity and described tenth electric capacity is equal and this capacitance is determined by equation below:Determine；T is the degree of depth of single bar shaped silicon through hole, l2For the length of outer side sum of all bar shaped silicon through holes, w2For the outside width sum of all bar shaped silicon through holes, CsubFor the unit-area capacitance of substrate, kcBetween generally 2-5.
Further improving is that the capacitance of described inner foundation electric capacity is determined by equation below:Described inner foundation resistance equation below determines:The capacitance of described first external substrate electric capacity, described second external substrate electric capacity, described 3rd external substrate electric capacity and described 4th external substrate electric capacity is equal and this capacitance is determined by equation below:The resistance value of described first external substrate resistance, described second external substrate resistance, described 3rd external substrate resistance and described 4th external substrate resistance is equal and this resistance value is determined by equation below:In above-mentioned formula, t is the degree of depth of single bar shaped silicon through hole, l1For the inside length sum of all bar shaped silicon through holes, l2For the length of outer side sum of all bar shaped silicon through holes, w1For the inboard width sum of all bar shaped silicon through holes, w2For the outside width sum of all bar shaped silicon through holes, GsubFor the electrical conductivity of silicon substrate, CsubUnit-area capacitance for silicon substrate.
The radiofrequency model method of silicon via-hole array structure of the present invention take into account stray inductance, dead resistance and the Kelvin effect of bar shaped silicon through hole in silicon via-hole array structure, and the mutual inductance that the coupling between bar shaped silicon through hole is between electric capacity, bar shaped silicon through hole, and silicon through hole and the parasitic capacitance of substrate, and body effect etc., can well characterize the high-frequency characteristic of silicon via-hole array structure, simulate the relation of the stray inductance of silicon via-hole array structure, parasitic capacitance and frequency accurately.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structure photo of existing silicon through hole；
Fig. 2 is the radiofrequency model of the radiofrequency model method of existing silicon through hole；
Fig. 3 A is the inductance that obtains of the radiofrequency model method of existing silicon through hole and the relation curve of frequency；
Fig. 3 B is the resistance that obtains of the radiofrequency model method of existing silicon through hole and the relation curve of frequency；
Fig. 4 A is the schematic diagram of the silicon via-hole array structure one in the embodiment of the present invention；
Fig. 4 B is the schematic diagram of the silicon via-hole array structure two in the embodiment of the present invention；
Fig. 5 is the radiofrequency model of the radiofrequency model method of embodiment of the present invention silicon via-hole array structure；
Fig. 6 A is the inductance that obtains of embodiment of the present invention method and the relation curve of frequency；
Fig. 6 B is the inductance that obtains of embodiment of the present invention method and the relation curve of frequency.
Detailed description of the invention
The radiofrequency model method of embodiment of the present invention silicon via-hole array structure is for setting up the radiofrequency model of silicon via-hole array structure, as shown in Figure 4 A, is the schematic diagram of silicon via-hole array structure one in the embodiment of the present invention；Multiple bar shaped silicon through holes composition that described silicon via-hole array structure is formed from silicon substrate, described bar shaped silicon through hole is all connected with liner 1.nullDescribed bar shaped silicon through hole includes multiple bar shaped silicon through hole 1、Two bar shaped silicon through holes 23 and two bar shaped silicon through holes 34，Each described bar shaped silicon through hole 1 is equally spaced arranged in parallel，The length of each described bar shaped silicon through hole 1 is equal、Width is equal，Each described bar shaped silicon through hole 1 is mutually aligned with，Described bar shaped silicon through hole 23 and described bar shaped silicon through hole 34 are surrounded on the outside of the homogeneous texture being made up of described bar shaped silicon through hole 1，And described bar shaped silicon through hole 23 is parallel with described bar shaped silicon through hole 1、And the length of described bar shaped silicon through hole 23 is more than the length of described bar shaped silicon through hole 1，Described bar shaped silicon through hole 34 and described bar shaped silicon through hole 1 are vertical、And the length of described bar shaped silicon through hole 34 is more than the length of the homogeneous texture being made up of described bar shaped silicon through hole 1，The length direction of homogeneous texture is vertical with the length direction of described bar shaped silicon through hole 1，Described bar shaped silicon through hole 23 is identical with the width of described bar shaped silicon through hole 1 with the width of described bar shaped silicon through hole 34.
As shown in Figure 4 B, it is the schematic diagram of silicon via-hole array structure two in the embodiment of the present invention；Multiple bar shaped silicon through holes composition that described silicon via-hole array structure is formed from silicon substrate, described bar shaped silicon through hole is all connected with liner 1.Described bar shaped silicon through hole is that bar shaped silicon through hole 1 i.e. only includes bar shaped silicon through hole 1, and each described bar shaped silicon through hole 1 is equally spaced arranged in parallel, and the length of each described bar shaped silicon through hole 1 is equal, width is equal, and each described bar shaped silicon through hole 1 is mutually aligned with.
As it is shown in figure 5, be the radiofrequency model of the radiofrequency model method of embodiment of the present invention silicon via-hole array structure；Described radiofrequency model includes:
Two ports, port one Port1 represents that the upper end of each described bar shaped silicon through hole, port two Port2 represent the lower end of each described bar shaped silicon through hole.The upper end of all described bar shaped silicon through holes all links together, the lower end of all described bar shaped silicon through holes all links together.
First inductance component L main1 and the second inductance component L main2, for characterizing formed two stray inductances of described silicon via-hole array structure；There is mutual inductance between described first inductance component L main1 and described second inductance component L main2, mutual inductance is K.The inductance value of described first inductance component L main1 and described second inductance component L main2 is equal, and the inductance value of described first inductance component L main1 and described second inductance component L main2 is between 1.6 times to 2 times of the inductance value between port one Port1 and port two Port2 of the sample of the described silicon via-hole array structure obtained under the test condition of 100MHz or frequencies below；K is between 0 to 1.
First coupling capacitance element Ccoupling1 and the second coupling capacitance element Ccoupling2, described first coupling capacitance element Ccoupling1 is for characterizing the coupling electric capacity of the position of close described port one Port1 of described silicon via-hole array structure, and described second coupling capacitance element Ccoupling2 is for characterizing the coupling electric capacity of the position of close described port two Port2 of described silicon via-hole array structure.The capacitance of described first coupling capacitance element Ccoupling1 and described second coupling capacitance element Ccoupling2 is equal, and the formula of the capacitance of described first coupling capacitance element Ccoupling1 or described second coupling capacitance element Ccoupling2 is: Ccoupling1=Ccoupling2=n × w × w × ε/t, wherein Ccoupling1For the capacitance of described first coupling capacitance element, Ccoupling2For the capacitance of described second coupling capacitance element, n is the number of bar shaped silicon through hole in array, and w is the width of single bar shaped silicon through hole, and t is the degree of depth of single bar shaped silicon through hole, and ε is the dielectric coefficient of the silicon medium between bar shaped silicon through hole.
Two ladder resistances and inductance network, for characterize described silicon via-hole array structure the dead resistance of bar shaped silicon through hole and Kelvin effect.Part shown in first ladder resistance and inductance network i.e. dotted line frame 5a be formed in parallel by the N level electronic circuit more than or equal to 2, every one-level electronic circuit is in series by a sub-resistance and sub-inductance, the sub-resistance of electronic circuits at different levels is respectively Rs11, Rs12, Rs13 ... Rs1n, and the sub-inductance of electronic circuits at different levels is respectively Ls11, Ls12, Ls13 ... Ls1n.Part shown in second ladder resistance and inductance network i.e. dotted line frame 5b be formed in parallel by N level electronic circuit, every one-level electronic circuit is in series by a sub-resistance and sub-inductance, the sub-resistance of electronic circuits at different levels is respectively Rs21, Rs22, Rs23 ... Rs2n, and the sub-inductance of electronic circuits at different levels is respectively Ls21, Ls22, Ls2 ... Ls2n.From the first order electronic circuit of described first ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels increase successively i.e. Rs11<Rs12<Rs13<...<Rs1n, and the value of sub-inductance at different levels reduce i.e. Ls11>Ls12>Ls13 successively>...>Ls1n.From the first order electronic circuit of described second ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels increase successively i.e. Rs21<Rs22<Rs23<...<Rs2n, and the value of sub-inductance at different levels reduce i.e. Ls21>Ls22>Ls23 successively>...>Ls2n.Or, from the first order electronic circuit of described first ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels reduces i.e. Rs11>Rs12>Rs13 successively>...>Rs1n, and the value of sub-inductance at different levels increase successively i.e. Ls11<Ls12<Ls13<...<Ls1n.From the first order electronic circuit of described second ladder resistance and inductance network to N level electronic circuit, the value of sub-resistance at different levels reduces i.e. Rs21>Rs22>Rs23 successively>...>Rs2n, and the value of sub-inductance at different levels increase successively i.e. Ls21<Ls22<Ls23<...<Ls2n.
The calculating of above-mentioned sub-resistance at different levels and sub-inductance is referred to below embodiment of the present invention and obtains, separately, N is equal to 4, described first ladder resistance is identical with the value of the sub-resistance of the same stages of inductance network with the at different levels sub-resistance of inductance network and described second ladder resistance, and described first ladder resistance is identical with the value of the sub-inductance of the same stages of inductance network with the at different levels sub-inductance of inductance network and described second ladder resistance；Described first ladder resistance and inductance network or described second ladder resistance are obtained by equation below with the at different levels sub-resistance of inductance network:
Wherein, αR=2.1246, x are between 1 to 2；RDCFor the dead resistance between port one and the port two of the sample of described silicon via-hole array structure obtained under the test condition of 100MHz or frequencies below, or RDCFor the resistance value obtained by the resistivity of each bar shaped silicon through hole of described silicon via-hole array structure and sectional area and depth calculation；R1For the sub-resistance value of the first order, R2For the sub-resistance value in the second level, R3For the sub-resistance value of the third level, R4For the sub-resistance value of the fourth stage；L1For the sub-inductance value of the first order, L2For the sub-inductance value in the second level, L3For the sub-inductance value of the third level, L4For the sub-inductance value of the fourth stage.
Described first ladder resistance and inductance network or described second ladder resistance are obtained by equation below with the at different levels sub-inductance of inductance network: Wherein LmainFor described first inductance element or the inductance value of described second inductance element.
When N is equal to other value, the formula of x can expand to the ratio between sub-resistance or the sub-inductance of two adjacent levels in the sub-resistance of N level or sub-inductance, for the sub-resistance of the little adjacent one-level of the sub-resistance of the big one-level of value and value or be worth the sub-inductance of big one-level and be worth the sub-inductance of little adjacent one-level；RDCFormula expand to the parallel value of each sub-resistance of the sub-resistance of N level.
Above-mentioned be for from first order electronic circuit to N level electronic circuit, the situation that the value of sub-resistance at different levels increases successively.And for from first order electronic circuit to N level electronic circuit, the situation that the value of sub-resistance at different levels reduces successively, αRReformulation be:RNIt it is the sub-resistance value of N level.
Described first inductance component L main1 and described first ladder resistance and inductance network are series between described port one Port1 and described port two Port2, and described second inductance component L main2 and described second ladder resistance and inductance network are series between described port one Port1 and described port two Port2；The two ends of described first coupling capacitance element Ccoupling1 are all connected with described port one Port1, and the two ends of described second coupling capacitance element Ccoupling2 are all connected with described port two Port2.
Parasitic capacitance between described bar shaped silicon through hole and the substrate of described silicon via-hole array inside configuration of described silicon via-hole array structure, including the 3rd electric capacity Ctsv11, the 4th electric capacity Ctsv13, the 5th electric capacity Ctsv21 and the 6th electric capacity Ctsv23.Described 3rd electric capacity Ctsv11, described 4th electric capacity Ctsv13, described 5th electric capacity Ctsv21 and described 6th electric capacity Ctsv23 capacitance equal and this capacitance is determined by equation below:Wherein, t is the degree of depth of single bar shaped silicon through hole, l1For the inside length sum of all bar shaped silicon through holes, w1For the inboard width sum of all bar shaped silicon through holes, CsubFor the unit-area capacitance of substrate, kcBetween 2-5.
As shown in Figure 4 A, the inside length of the most all bar shaped silicon through holes includes: the length sides of all bar shaped silicon through holes 1, the length sides in the inner part of two bar shaped silicon through holes 23, the length sides in the inner part of two bar shaped silicon through holes 34, l1Sum for the inside length of above-mentioned all bar shaped silicon through holes.The inboard width of the most all bar shaped silicon through holes includes: the width edge of all bar shaped silicon through holes 1, the width edge of two bar shaped silicon through holes 34, w1Sum for the inboard width of above-mentioned all bar shaped silicon through holes.
As shown in Figure 4 B, the inside length of the most all bar shaped silicon through holes includes: the inside length limit of two outermost bar shaped silicon through holes 1, the length sides being positioned at other all bar shaped silicon through holes 1 within two outermost bar shaped silicon through holes 1 are all inside length limit；l1Sum for the inside length of above-mentioned all bar shaped silicon through holes.The width edge of the most all bar shaped silicon through holes is all outside width limit, w1It is zero.
Parasitic capacitance between described bar shaped silicon through hole and the substrate of described silicon via-hole array structural outer of described silicon via-hole array structure, including the 7th electric capacity Ctsv12, the 8th electric capacity Ctsv14, the 9th electric capacity Ctsv22 and the tenth electric capacity Ctsv24.Described 7th electric capacity Ctsv12, described 8th electric capacity Ctsv14, described 9th electric capacity Ctsv22 and described tenth electric capacity Ctsv24 capacitance equal and this capacitance is determined by equation below:Determine；T is the degree of depth of single bar shaped silicon through hole, l2For the length of outer side sum of all bar shaped silicon through holes, w2For the outside width sum of all bar shaped silicon through holes, CsubFor the unit-area capacitance of substrate, kcBetween 2-5.
As shown in Figure 4 A, the length of outer side of the most all bar shaped silicon through holes includes: the length sides in the outer part of two bar shaped silicon through holes 23 and the length sides in the outer part of two bar shaped silicon through holes 34, l2Sum for the length of outer side of above-mentioned all bar shaped silicon through holes.The outside width of the most all bar shaped silicon through holes includes: all width edge of two bar shaped silicon through holes 23, w2Sum for the outside width of above-mentioned all bar shaped silicon through holes.
As shown in Figure 4 B, the length of outer side of the most all bar shaped silicon through holes includes: the length of outer side limit of two outermost bar shaped silicon through holes 1；l2Sum for the length of outer side of above-mentioned all bar shaped silicon through holes.The outside width of the most all bar shaped silicon through holes includes: all width edge of all bar shaped silicon through holes 1, w2Sum for the outside width of above-mentioned all bar shaped silicon through holes.
The inner foundation network element of described silicon via-hole array structure, including inner foundation electric capacity Csub and inner foundation resistance Rsub.
The external substrate network element of described silicon via-hole array structure, including the first external substrate electric capacity Csub11 and the first external substrate resistance Rsub11, second external substrate electric capacity Csub12 and the second external substrate resistance Rsub12,3rd external substrate electric capacity Csub21 and the 3rd external substrate resistance Rsub21, the 4th external substrate electric capacity Csub22 and the 4th external substrate resistance Rsub22.
The capacitance of described inner foundation electric capacity Csub is determined by equation below:Described inner foundation resistance Rsub equation below determines:Described first external substrate electric capacity Csub11, described second external substrate electric capacity Csub12, described 3rd external substrate electric capacity Csub21 and described 4th external substrate electric capacity Csub22 capacitance equal and this capacitance is determined by equation below:Described first external substrate resistance Rsub11, described second external substrate resistance Rsub12, described 3rd external substrate resistance Rsub21 and described 4th external substrate resistance Rsub22 resistance value equal and this resistance value is determined by equation below:In above-mentioned formula, t is the degree of depth of single bar shaped silicon through hole, l1For the inside length sum of all bar shaped silicon through holes, l2For the length of outer side sum of all bar shaped silicon through holes, w1For the inboard width sum of all bar shaped silicon through holes, w2For the outside width sum of all bar shaped silicon through holes, GsubFor the electrical conductivity of silicon substrate, CsubUnit-area capacitance for silicon substrate.
Described inner foundation electric capacity Csub and described inner foundation resistance Rsub is connected in parallel, first end of described 3rd electric capacity Ctsv11 is connected with described port one Port1, second end of described 3rd electric capacity Ctsv11 is connected with first end of described inner foundation electric capacity Csub, and first end of described 4th electric capacity Ctsv13 is connected with described port two Port2, second end of described 4th electric capacity Ctsv13 is connected with first end of described inner foundation electric capacity Csub；First end of described 5th electric capacity Ctsv21 is connected with described port one Port1, second end of described 5th electric capacity Ctsv21 is connected with second end of described inner foundation electric capacity Csub, and first end of described 6th electric capacity Ctsv23 is connected with described port two Port2, second end of described 6th electric capacity Ctsv23 is connected with second end of described inner foundation electric capacity Csub.
Described first external substrate electric capacity Csub11 and the first external substrate resistance Rsub11 is connected in parallel, and the first end ground connection of described first external substrate electric capacity Csub11, described second external substrate electric capacity Csub12 and the second external substrate resistance Rsub12 is connected in parallel, and the first end ground connection of described second external substrate electric capacity Csub12, described 3rd external substrate electric capacity Csub21 and the 3rd external substrate resistance Rsub21 is connected in parallel, and the first end ground connection of described 3rd external substrate electric capacity Csub21, described 4th external substrate electric capacity Csub22 and the 4th external substrate resistance Rsub22 is connected in parallel, and the first end ground connection of described 4th external substrate electric capacity Csub22.
nullFirst end of described 7th electric capacity Ctsv12 is connected with described port one Port1、Second end of described 7th electric capacity Ctsv12 is connected with second end of described first external substrate electric capacity Csub11，First end of described 8th electric capacity Ctsv14 is connected with described port two Port2、Second end of described 8th electric capacity Ctsv14 is connected with second end of described second external substrate electric capacity Csub12，First end of described 9th electric capacity Ctsv22 is connected with described port one Port1、Second end of described 9th electric capacity Ctsv22 is connected with second end of described 3rd external substrate electric capacity Csub21，First end of described tenth electric capacity Ctsv24 is connected with described port two Port2、Second end of described tenth electric capacity Ctsv24 is connected with second end of described second external substrate electric capacity Csub12.
The radiofrequency model method of embodiment of the present invention silicon via-hole array structure take into account stray inductance, dead resistance and the Kelvin effect of bar shaped silicon through hole in silicon via-hole array structure, and the mutual inductance that the coupling between bar shaped silicon through hole is between electric capacity, bar shaped silicon through hole, and silicon through hole and the parasitic capacitance of substrate, and body effect etc., can well characterize the high-frequency characteristic of silicon via-hole array structure, simulate the relation of the stray inductance of silicon via-hole array structure, parasitic capacitance and frequency accurately.As shown in Figure 6A, it is the inductance that obtains of embodiment of the present invention method and the relation curve of frequency；Wherein solid line is stray inductance and the relation curve of frequency of the silicon via-hole array obtained by the radiofrequency model of embodiment of the present invention method, square frame dotted line is stray inductance and the relation curve of frequency of the silicon via-hole array obtained by reality measurement, can be seen that both meet fine, and the relation curve of the inductance that in Fig. 3 A, existing method obtains and frequency is different.As shown in Figure 6B, it is the inductance that obtains of embodiment of the present invention method and the relation curve of frequency, wherein solid line is dead resistance and the relation curve of frequency of the silicon via-hole array obtained by the radiofrequency model of embodiment of the present invention method, square frame dotted line is dead resistance and the relation curve of frequency of the silicon via-hole array obtained by reality measurement, it can be seen that it is fine that both meet.
Above by specific embodiment, the present invention is described in detail, but these have not been construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, and these also should be regarded as protection scope of the present invention.
Claims (10)
1. a radiofrequency model method for silicon via-hole array structure, for setting up the radiofrequency model of silicon via-hole array structure,
Multiple bar shaped silicon through holes composition that described silicon via-hole array structure is formed from silicon substrate, described bar shaped silicon through hole is bar
Shape silicon through hole one, each described bar shaped silicon through hole one is equally spaced arranged in parallel, the length phase of each described bar shaped silicon through hole one
Equal Deng, width, each described bar shaped silicon through hole one is mutually aligned with；Or, described silicon via-hole array structure is by being formed
Multiple bar shaped silicon through holes composition in silicon substrate, described bar shaped silicon through hole includes one, two bars of multiple bar shaped silicon through holes
Shape silicon through hole two and two bar shaped silicon through holes three, each described bar shaped silicon through hole one is equally spaced arranged in parallel, each described bar
The length of shape silicon through hole one is equal, width is equal, and each described bar shaped silicon through hole one is mutually aligned with, and described bar shaped silicon leads to
Bar shaped silicon through hole three described in Kong Erhe is surrounded on the outside of the homogeneous texture being made up of described bar shaped silicon through hole one, and
Described bar shaped silicon through hole two is more than described bar with the length of described bar shaped silicon through hole one parallel and described bar shaped silicon through hole two
The length of shape silicon through hole one, described bar shaped silicon through hole three and described bar shaped silicon through hole one be vertical and described bar shaped silicon through hole three
Length more than the length of homogeneous texture being made up of described bar shaped silicon through hole one, described bar shaped silicon through hole two and institute
The width stating bar shaped silicon through hole three is identical with the width of described bar shaped silicon through hole one；
It is characterized in that, described radiofrequency model includes:
Two ports, port one represents that the upper end of each described bar shaped silicon through hole, port two represent each described bar shaped silicon through hole
Lower end；The upper end of all described bar shaped silicon through holes all links together, the lower end of all described bar shaped silicon through holes all connects
It is connected together；
First inductance element and the second inductance element, post for characterizing formed two of described silicon via-hole array structure
Raw inductance；There is mutual inductance between described first inductance element and described second inductance element, mutual inductance is K；
First coupling capacitance element and the second coupling capacitance element, described first coupling capacitance element is used for characterizing described silicon
The coupling electric capacity of the position of the close described port one of via-hole array structure, described second coupling capacitance element is used for table
Levy the coupling electric capacity of the position of the close described port two of described silicon via-hole array structure；
Two ladder resistances and inductance network, for characterizing the parasitic electricity of the bar shaped silicon through hole of described silicon via-hole array structure
Resistance and Kelvin effect；First ladder resistance and inductance network are to be formed in parallel by N level electronic circuit, described first ladder electricity
Hinder the every one-level electronic circuit with inductance network to be in series by a sub-resistance and sub-inductance, the second ladder resistance and inductance
Network is to be formed in parallel by N level electronic circuit, and every one-level electronic circuit of described second ladder resistance and inductance network is by one
Sub-resistance and sub-inductance are in series, and N is more than or equal to 2；
Described first inductance element and described first ladder resistance are series at described port one and described end with inductance network
Between mouth two, described second inductance element and described second ladder resistance are series at described port one and institute with inductance network
State between port two；The two ends of described first coupling capacitance element are all connected with described port one, described second coupling electricity
The two ends holding element are all connected with described port two.
2. the radiofrequency model method of silicon via-hole array structure as claimed in claim 1, it is characterised in that: described the
The inductance value of one inductance element and described second inductance element is equal, described first inductance element or described second inductance unit
The inductance value of part is the sample of the described silicon via-hole array structure obtained under the test condition of 100MHz or frequencies below
Port one and port two between 1.6 times to 2 times of inductance value between；K is between 0 to 1.
3. the radiofrequency model method of silicon via-hole array structure as claimed in claim 1, it is characterised in that: described the
The capacitance of one coupling capacitance element and described second coupling capacitance element is equal, described first coupling capacitance element or institute
The formula of the capacitance stating the second coupling capacitance element is: Ccoupling1=Ccoupling2=n × w × w × ε/t, wherein
Ccoupling1For the capacitance of described first coupling capacitance element, Ccoupling2For the capacitance of described second coupling capacitance element,
N is the number of bar shaped silicon through hole in array, and w is the width of single bar shaped silicon through hole, and t is single bar shaped silicon through hole
The degree of depth, ε is the dielectric coefficient of the silicon medium between bar shaped silicon through hole.
4. the radiofrequency model method of silicon via-hole array structure as claimed in claim 1, it is characterised in that: from described
The first order electronic circuit of the first ladder resistance and inductance network is to N level electronic circuit, and the value of sub-resistance at different levels increases successively
And the value of sub-inductance at different levels reduces successively；From the first order electronic circuit of described second ladder resistance and inductance network to N
Level electronic circuit, the value of sub-resistance at different levels increases successively and the value of sub-inductance at different levels reduces successively.
5. the radiofrequency model method of silicon via-hole array structure as claimed in claim 4, it is characterised in that: N is equal to 4,
Described first ladder resistance is identical with inductance network with the at different levels sub-resistance of inductance network and described second ladder resistance
The value of the sub-resistance of level is identical, described first ladder resistance and the at different levels sub-inductance of inductance network and described second ladder electricity
Hinder identical with the value of the sub-inductance of the same stages of inductance network；Described first ladder resistance and inductance network or described second
Ladder resistance is obtained by equation below with the at different levels sub-resistance of inductance network:
Wherein, αR=2.1246, x are between 1 to 2；RDCFor the test condition at 100MHz or frequencies below
Under dead resistance between port one and the port two of the sample of described silicon via-hole array structure that obtain, or RDCIt is logical
Cross the resistivity of each bar shaped silicon through hole of described silicon via-hole array structure and sectional area and resistance value that depth calculation obtains；
R1For the sub-resistance value of the first order, R2For the sub-resistance value in the second level, R3For the sub-resistance value of the third level, R4For fourth stage electricity
Resistance；L1For the sub-inductance value of the first order, L2For the sub-inductance value in the second level, L3For the sub-inductance value of the third level, L4It is the 4th
The sub-inductance value of level；
Described first ladder resistance is logical with the at different levels sub-inductance of inductance network with inductance network or described second ladder resistance
Cross equation below to obtain:Wherein LmainFor described first inductance
Element or the inductance value of described second inductance element.
6. the radiofrequency model method of silicon via-hole array structure as claimed in claim 1, it is characterised in that: from described
The first order electronic circuit of the first ladder resistance and inductance network is to N level electronic circuit, and the value of sub-resistance at different levels reduces successively
And the value of sub-inductance at different levels increases successively；From the first order electronic circuit of described second ladder resistance and inductance network to N
Level electronic circuit, the value of sub-resistance at different levels reduces successively and the value of sub-inductance at different levels increases successively.
7. the radiofrequency model method of silicon via-hole array structure as claimed in claim 1, it is characterised in that penetrate described in:
Frequently model also includes:
The described bar shaped silicon through hole of described silicon via-hole array structure and the silicon substrate of described silicon via-hole array inside configuration it
Between parasitic capacitance, including the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity and the 6th electric capacity；
The described bar shaped silicon through hole of described silicon via-hole array structure and the silicon substrate of described silicon via-hole array structural outer it
Between parasitic capacitance, including the 7th electric capacity, the 8th electric capacity, the 9th electric capacity and the tenth electric capacity；
The inner foundation network element of described silicon via-hole array structure, including inner foundation electric capacity and inner foundation resistance；
The external substrate network element of described silicon via-hole array structure, including the outside lining of the first external substrate electric capacity and first
End resistance, the second external substrate electric capacity and the second external substrate resistance, the 3rd external substrate electric capacity and the 3rd external substrate
Resistance, the 4th external substrate electric capacity and the 4th external substrate resistance；
Described inner foundation electric capacity and described inner foundation resistor coupled in parallel connect, the first end of described 3rd electric capacity and described
Port one is connected, and the second end of described 3rd electric capacity is connected with the first end of described inner foundation electric capacity, described 4th electricity
The first end held is connected with described port two, the second end of described 4th electric capacity and the first end of described inner foundation electric capacity
It is connected；First end of described 5th electric capacity is connected with described port one, the second end of described 5th electric capacity and described inside
Second end of capacitance to substrate is connected, and the first end of described 6th electric capacity is connected with described port two, described 6th electric capacity
Second end is connected with the second end of described inner foundation electric capacity；
Described first external substrate electric capacity and the first external substrate resistor coupled in parallel connect and described first external substrate electric capacity
The first end ground connection, described second external substrate electric capacity and the second external substrate resistor coupled in parallel connect and described second outside
First end ground connection of capacitance to substrate, described 3rd external substrate electric capacity and the 3rd external substrate resistor coupled in parallel connect and described
First end ground connection of the 3rd external substrate electric capacity, described 4th external substrate electric capacity and the 4th external substrate resistor coupled in parallel are even
Connect and the first end ground connection of described 4th external substrate electric capacity；
First end of described 7th electric capacity is connected with described port one, outside second end and described first of described 7th electric capacity
Second end of portion's capacitance to substrate is connected, and the first end of described 8th electric capacity is connected with described port two, described 8th electric capacity
The second end be connected with the second end of described second external substrate electric capacity, the first end of described 9th electric capacity and described port
One is connected, and the second end of described 9th electric capacity is connected with the second end of described 3rd external substrate electric capacity, described tenth electricity
The first end held is connected with described port two, the of the second end of described tenth electric capacity and described second external substrate electric capacity
Two ends are connected.
8. the radiofrequency model method of silicon via-hole array structure as claimed in claim 7, it is characterised in that: described the
The capacitance of three electric capacity, described 4th electric capacity, described 5th electric capacity and described 6th electric capacity is equal and this capacitance is by such as
Lower formula determines:
Wherein, t is the degree of depth of single bar shaped silicon through hole, l1For the inside length sum of all bar shaped silicon through holes, w1For
The inboard width sum of all bar shaped silicon through holes, CsubFor the unit-area capacitance of silicon substrate, kcBetween 2-5, kc
For fitting coefficient.
9. the radiofrequency model method of silicon via-hole array structure as claimed in claim 7, it is characterised in that: described the
The capacitance of seven electric capacity, described 8th electric capacity, described 9th electric capacity and described tenth electric capacity is equal and this capacitance is by such as
Lower formula determines:Determine；
T is the degree of depth of single bar shaped silicon through hole, l2For the length of outer side sum of all bar shaped silicon through holes, w2For all bars
The outside width sum of shape silicon through hole, CsubFor the unit-area capacitance of silicon substrate, kcBetween 2-5, kcFor matching
Coefficient.
10. the radiofrequency model method of silicon via-hole array structure as claimed in claim 7, it is characterised in that:
The capacitance of described inner foundation electric capacity is determined by equation below:
Described inner foundation resistance equation below determines:
Described first external substrate electric capacity, described second external substrate electric capacity, described 3rd external substrate electric capacity and described
The capacitance of the 4th external substrate electric capacity is equal and this capacitance is determined by equation below:
Described first external substrate resistance, described second external substrate resistance, described 3rd external substrate resistance and described
The resistance value of the 4th external substrate resistance is equal and this resistance value is determined by equation below:
In above-mentioned formula, t is the degree of depth of single bar shaped silicon through hole, l1For the inside length sum of all bar shaped silicon through holes,
l2For the length of outer side sum of all bar shaped silicon through holes, w1For the inboard width sum of all bar shaped silicon through holes, w2For
The outside width sum of all bar shaped silicon through holes, GsubFor the electrical conductivity of silicon substrate, CsubUnit are for silicon substrate
Electric capacity.
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