CN105095533B - A method of establishing metal-insulator-metal capacitor model - Google Patents
A method of establishing metal-insulator-metal capacitor model Download PDFInfo
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Abstract
The present invention relates to a kind of methods for establishing metal-insulator-metal capacitor model, and the method includes the steps (a) to design metal-insulator-metal Test Constructure of model；Step (b) is according to the test structure model foundation model equation and format in the step (a)；Step (c) is according to model equation described in step (b) and format extraction model, to obtain metal-insulator-metal capacitor model.A kind of new method for establishing metal-insulator-metal capacitor model is provided in the present invention, the single model that preferred dimension can become in the method, include multiple metal layers in the model, each metal layer includes the first pectinate texture and the second pectinate texture, wherein broach is mutually parallel staggeredly, the model expends the less modeling time and occupies less test chip area, the cost of product can be further decreased, the model can obtain more freely using, and improve efficiency.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to which a kind of establishing metal-insulator-metal capacitor mould
The method of type.
Background technology
Increasingly increase for the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages
It is concerned by people, in order to increase the integration density of semiconductor storage, uses many different sides in the prior art
Method, such as multiple storage units are formed on single wafer by reducing wafer size and/or changing interior structural unit.
As the continuous development integrated circuit of semiconductor technology and the integrated circuit of large size are widely used, form
It can be passive either active in the component of integrated circuit, become integrated nothing when the component is passive device
Source device (integrated passive device, IPD), IPD provide the passive devices such as high-accuracy capacitor and high-performance inductance
It is integrated, the application on radio frequency at present becomes new hot spot.
The passive device includes metal-insulating layer-metal capacitor, and metal-insulating layer-metal capacitor is due to its performance
Superior, with IC, metal-insulating layer-metal capacitor model described in the prior art consists of metal for more and more applications,
But the model is only applicable to specific domain structure.
Although there is a small number of metal-insulating layer-metal capacitor models in the prior art, the model is used only one
The metal layer of type is combined to form a model to describe the performance of metal-insulating layer-metal capacitor, such as by the first gold medal
When category layer M1 to the 6th metal layer M6 is combined to form capacitance, it is desirable to provide a model, by second metal layer M2 to the 6th gold medal
When category layer M6 is combined to form another metal capacitance, it is desirable to provide another model, the model that client is provided cannot
The model for freely adequately utilizing, and client can only being used to provide is accessed, but with the reduction of wafer size, it is impossible to
Enough detection structures are set on wafer to extract all metal-insulating layer-metal capacitor models.
Therefore, it is necessary to the method for building up to metal-insulating layer-metal capacitor model described in the prior art to make further
It improves, so as to eliminate the above problem.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of side establishing metal-insulator-metal capacitor model
Method, including：
Step (a) designs metal-insulator-metal capacitor test structure model；
Step (b) is according to the test structure model foundation model equation and format in the step (a)；
Step (c) is according to model equation described in step (b) and format extraction model, to obtain metal-insulator-gold
Belong to capacitor model.
Preferably, the step (a) includes following sub-step：
It includes first kind gold that step (a-1), which selects the metal layer used in the test structure model, the metal layer,
Belong to layer and Second Type metal layer；
Step (a-2) sets the parameter of the metal layer；
The number of the test structure model is calculated according to the metal layer and the parameter for step (a-3).
Preferably, if the metal layer includes dried layer, it is oppositely arranged wherein including at least in every layer of metal layer
The broach of first pectinate texture and the second pectinate texture, the broach of first pectinate texture and second pectinate texture is mutual
Staggeredly and it is isolated.
Preferably, the parameter of the metal layer includes broach in first pectinate texture and second pectinate texture
The distance between width, length, number and the broach.
Preferably, the number of the test structure model is equal to the number of the metal channel type, the metal layer
Parameter and the product for determining number of parameters needed for test structure moulded dimension.
Preferably, the step (b) includes following sub-step：
Step (b-1) chooses the parameter of different metal layer and/or metal layer in the step (a), obtains different surveys
Structural model is tried, and calculates the corresponding capacitance of test structure model, determines the parameter of the test structure model；
Step (b-2) establishes the model side between the capacitance and the test structure model according to the parameter
Formula and format.
Preferably, the capacitance of the test structure model includes tetra- part cf1, ca1, cf2 and ca2；
Wherein, the cf1 is the capacitance between broach in the first kind metal layer of same layer；
Electricity of the ca1 between broach in broach in neighbouring first kind metal layer and Second Type metal layer
Hold；
The cf2 is the capacitance between broach in the Second Type metal layer of same layer；
The ca2 is the capacitance between broach in neighbouring Second Type metal layer.
Preferably, the model equation includes following variable：Bottom gold in metal-insulator-metal capacitor model
Belong to layer, metal layer at top, the length and number of broach in metal-insulator-metal capacitor model.
Preferably, by changing the variable, different test structure models is obtained, and corresponding electricity is calculated
Hold, to establish the model equation and format between the capacitance and the test structure model.
Preferably, the bottom metal layers select the metal other than the two metal layers of test structure model the top
Layer；
The metal layer at top selects the test structure model to remove bottom metal layer and the topmost metal layer
Any intermediate metal layer in addition.
Preferably, the length of the broach is 3um~100um；
The number of the broach is 3~500.
Preferably, when the metal layer that the bottom metal layers are selected is metal layer M1, with the relevant public affairs of metal layer M1
Formula effectively (that is, using and the relevant formula of metal layer M1 at this time),
When the metal layer non-metallic layer M1 that the bottom metal layers are selected, but -2 gold from metal layer M2 to metal layer at top
Belong to layer in any metal layer when, it is invalid with the relevant formula of metal layer M1, with the incoherent formula of metal layer M1 effectively (that is,
It uses and the incoherent formula of metal layer M1 at this time)
Preferably, the step (c) includes following sub-step：
Step (c-1) extracts suitable curve according to the model equation, determines the variable in the model equation,
Establish metal-insulator-metal capacitor model.
Preferably, the method is further comprising the steps of：
Influence of the step (c-2) by voltage and temperature to capacitance is added to the metal-insulator-metal capacitor model
In, to obtain more accurate model.
It is in order to solve the problems in the existing technology provided in the present invention and a kind of new establishes metal-insulator-gold
The method for belonging to capacitor model, the single model that preferred dimension can become in the method, includes multiple metals in the model
Layer, each metal layer includes the first pectinate texture and the second pectinate texture, and wherein broach is mutually parallel staggeredly, the model consumption
Take the less modeling time and occupy less test chip area, the cost of product, the model can be further decreased
It can obtain more freely using, improve efficiency.
The selection of all metal layers is contained in the modeling method of metal-insulator-metal type capacitance structure of the present invention,
The parameter of spacing and device size in metal layer between broach number, broach width, broach length and broach.It is described
Model is used to describe MOM capacitor in a model, passes through the selection of metal layer, broach number, broach width, broach length
And the selection of the spacing between broach describes the capacitance of different metal layer and different metal layer sizes.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 a-1c are the structural schematic diagram of the metal-insulator-metal capacitor model；
Fig. 2 is the process flow chart for establishing the metal-insulator-metal capacitor model.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
In order to solve the problems in the existing technology the present invention provides a kind of establishing metal-insulator-metal capacitor
The method of model, including：
The design of step (a) metal-insulator-metal capacitor test structure model；
Step (b) is according to the test structure model foundation model equation and format in the step (a)；
Step (c) carries out the extraction of model according to model equation described in step (b) and format, exhausted to obtain metal-
Edge body-metal capacitance model.
Wherein, the step (a) includes following sub-step：
It includes first kind gold that step (a-1), which selects the metal layer used in the test structure model, the metal layer,
Belong to layer and Second Type metal layer；
Step (a-2) sets the parameter of the metal layer；
The number of the test structure model is calculated according to the metal layer and the parameter for step (a-3).
Specifically, wherein there are two types of the selections of metal layer described in the step (a-1), i.e. first kind metal layer and
Two types of metals layers, wherein the first kind metal layer and Second Type metal layer Bu Tong can specifically be presented as the gold
Belong to layer thickness and otherwise difference, the thickness of the metal layer is different, then causes the difference of capacitance.
Such as the present invention one specifically bottom metal layers described in embodiment select first kind metal layer, it is described
Second metal layer to metal layer at top selects Second Type metal layer, what certain example was merely exemplary, not office
It is limited to the example, such as first kind metal layer or second can also be only selected in the other embodiment of the present invention
Types of metals layer or the bottom metal layers select Second Type metal layer, the second metal layer equal to metal layer at top
First kind metal layer etc. is selected, details are not described herein, and the metal layer can select the metal layer of any type.
Wherein, the test structure model includes several metal layers, as seen in figure la and lb, several metal layers
Each metal layer includes mutually isolated part.
In step (a-2), the parameter of the metal layer includes at least the first pectinate texture and the second pectination that are oppositely arranged
101 ˊ of broach of structure, the broach 101 of first pectinate texture and second pectinate texture is interlaced, such as Fig. 1 c institutes
Show.
Wherein, broach connecting pin is still further comprised in first pectinate texture and second pectinate texture, it is described
Broach connecting pin is in the same plane with the broach and is mutually perpendicular to, wherein the broach of first pectinate texture and described
The broach of second pectinate texture is interlaced, but mutually isolated setting between the broach.
Further, it is connected with each other by through-hole 102 between the metal layer of different layers, specifically between different metal layer
Broach connecting pin connected by metal throuth hole.
The present invention one specifically metal layer described in embodiment include 6 layers, as shown in Figure 1 b, as metal layer M1,
M2, M3, M4, M5 and M6, all metal layers, wherein the M1 is bottom metal layer, the M6 is top layer metallic layer, but simultaneously
It is not limited to the example, can also include more layers metal layer, such as metal layer M7, M8 etc., wherein the bottom metal layer
M1 selects a kind of metal material, the metal layer M2 to M6 to select another metal material, the metal material that can select
Metal commonly used in the art, it is not limited to a certain.
Wherein, two metal layers are needed when forming capacitance, can select the metal layer of same metal material, such as gold
Belong to layer M2 to any two metal layer between M6；Or the metal layer of above two different metal material is selected, such as select
Bottom metal layer M1 and metal layer M2 between M6 any one metal layer form capacitance.Similarly, in modeling process, packet
Model containing above two, first, the double layer of metal of composition capacitance, does not include metal layer M1, at this time with a formula；Another kind is
The double layer of metal for forming capacitance includes M1, at this point, with another formula.
Preferably, wherein including the first pectinate texture and second pectinate texture, the pectination in each layer
Broach in structure is mutually isolated and interlaced, forms the model structure.
Wherein, the parameter of metal layer described in the step (a-2) includes the first pectinate texture and the second pectination knot
The distance between the width W of broach, length L, number N and described broach S in structure, as shown in figs. lb and lc, such as following table
Shown in lattice：
The number of the test structure model is calculated according to the metal layer and the parameter for step (a-3), wherein
The number of the test structure model is equal to the number, the number of the parameter and determining test structure of the metal channel type
The number product of main points needed for moulded dimension.
In this embodiment, such as the number of the wherein described metal layer type is 2, first kind metal layer and Second Type
Metal layer, wherein the parameter is 4, respectively the distance between the width W of broach, length L, number N and described broach
S determines that number of parameters needed for the test structure moulded dimension is at least 3, therefore the number of the test structure model is 2
× 4 × 3=24.
The area for the wafer that the test structure occupies can be further decreased by the method.
In the step (b), including following sub-step：
Step (b-1) chooses the parameter of different metal layer and/or metal layer in the step (a), obtains different surveys
Structural model is tried, and calculates the corresponding capacitance of test structure model, determines the parameter of the test structure model；
Step (b-2) establishes the model side between the capacitance and the test structure model according to the parameter
Formula and format.
Wherein, the capacitance of the test structure model includes cf1, ca1, cf2 and ca2 in this step；Wherein, described
Cf1 is the capacitance between broach in the first kind metal layer of same layer；The ca1 is neighbouring first kind metal
Capacitance in layer in broach and Second Type metal layer between broach；The cf2 is in the Second Type metal layer of same layer
Capacitance between broach；The ca2 is the capacitance between broach in neighbouring Second Type metal layer.
In of the invention one specifically embodiment, as shown, for example described metal layer M1 selects first kind gold
Belong to layer, metal layer M2- metal layers M6 selects Second Type metal layer；Wherein, the cf1 is between the broach in metal layer M1
Capacitance, the ca1 are the capacitance between the broach in broach and metal layer M2 in metal layer M1, and cf2 is metal layer M2- metals
It is the capacitance between same layer broach in layer M6；On in metal layer adjacent between metal layer M2- metal layers M6 the ca2
Capacitance between lower broach.
The total capacitance of the model structure=((((ca1* (tm-bm+1) -0.0098) * L*1e6+
(cf1* (tm-bm+1) -0.0008)) * N) * (bm==1)+(((ca2* (tm-bm+1) -0.0024) * lf*1e6+
(cf2*(tm-bm+1)-0.0362))*N)*(bm>1))*1e-15；
Wherein, the bm is bottom metal layers, and the tm is metal layer at top, and the L is the length of the broach, described
N is the number of the broach.
The variable of the model equation is bottom metal layers, top metal in metal-insulator-metal capacitor model
Layer, the length and number of broach in metal-insulator-metal capacitor model.
By changing the variable, different test structure models is obtained, and corresponding capacitance is calculated, to establish
The model equation between the capacitance and the test structure model and format.Such as select different metal layers and/
Or the length and number of broach obtain different models, and the capacitance data of different models is obtained by calculation, association is established,
To obtain the model equation and format.
Wherein, the bottom metal layers select the metal layer other than the two metal layers of test structure model the top；
In the specific implementation mode of the present invention, the bottom metal layers are selected below metal layer at top Mtop and metal layer at top
Contain 6 layers of metal layer in metal layer below Mtop-1, such as the model, then selects the 5th layer of metal layer below.
The metal layer at top selects any gold between bottom metal layer and topmost metal layer lower section
Belong to layer, specifically, the metal layer at top selects the arbitrary metal layer in metal layer M2 to metal layer Mtop-1.
Preferably, the length of the broach is 3um~100um；
The number of the broach is 3~500.
Wherein, when the metal layer that the bottom metal layers are selected is metal layer M1, have with the relevant formula of metal layer M1
Effect (that is, using and the relevant formula of metal layer M1 at this time),
When the metal layer non-metallic layer M1 that the bottom metal layers are selected, but -2 gold from metal layer M2 to metal layer at top
Belong to layer in any metal layer when, it is invalid with the relevant formula of metal layer M1, with the incoherent formula of metal layer M1 effectively (that is,
It uses and the incoherent formula of metal layer M1 at this time)
The step (c) includes following sub-step：
Step (c-1) extracts suitable curve according to the model equation, determines the variable in model equation, is used for
Establish metal-insulator-metal capacitor model；Specifically, different metal layers is chosen according to the model structure in step
Type and various variables, are added in the equation and extract, to obtain required model.
Influence of the step (c-2) by voltage and temperature to capacitance is added to the metal-insulator-metal capacitor model
In, to obtain more accurate model.
Fig. 2 be establish the process flow chart of the metal-insulator-metal capacitor model, including：
Step (a) designs metal-insulator-metal capacitor test structure model；
Step (b) is according to the test structure model foundation model equation and format in the step (a)；
Step (c) is according to model equation described in step (b) and format extraction model, to obtain metal-insulator-gold
Belong to capacitor model.
It is in order to solve the problems in the existing technology provided in the present invention and a kind of new establishes metal-insulator-gold
The method for belonging to capacitor model, the single model that preferred dimension can become in the method, includes multiple metals in the model
Layer, each metal layer includes the first pectinate texture and the second pectinate texture, and wherein broach is mutually parallel staggeredly, the model consumption
Take the less modeling time and occupy less test chip area, the cost of product, the model can be further decreased
It can obtain more freely using, improve efficiency.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of method for establishing metal-insulator-metal capacitor model, including：
Step (a) designs metal-insulator-metal capacitor test structure model；
Step (b) is according to the test structure model foundation model equation and format in the step (a)；
Step (c) is according to model equation described in step (b) and format extraction model, to obtain metal-insulator-metal type electricity
Molar type,
The step (a) includes following sub-step：
Step (a-1) selects the metal layer used in the test structure model, and the metal layer includes first kind metal layer
With Second Type metal layer.
2. according to the method described in claim 1, it is characterized in that, the step (a) further includes following sub-step：
Step (a-2) sets the parameter of the metal layer；
The number of the test structure model is calculated according to the metal layer and the parameter for step (a-3).
3. according to the method described in claim 2, it is characterized in that, if the metal layer includes dried layer, wherein every layer of gold
Belong to the first pectinate texture and the second pectinate texture for including at least and being oppositely arranged in layer, the broach of first pectinate texture and institute
The broach for stating the second pectinate texture is interlaced and be isolated.
4. according to the method described in claim 3, it is characterized in that, wherein, the parameter of the metal layer includes first comb
The distance between width, length, number and the broach of broach in shape structure and second pectinate texture.
5. according to the method described in claim 3, it is characterized in that, the number of the test structure model is equal to the metal layer
The number of type, the number of the parameter of the metal layer and the product for determining number of parameters needed for test structure moulded dimension.
6. method according to claim 1 to 5, which is characterized in that the step (b) includes following sub-step：
Step (b-1) chooses the parameter of different metal layer and/or metal layer in the step (a), obtains different test knots
Structure model, and the corresponding capacitance of test structure model is calculated, determine the parameter of the test structure model；
Step (b-2) establishes the model equation between the capacitance and the test structure model according to the parameter
And format.
7. according to the method described in claim 6, it is characterized in that, the capacitance of the test structure model include cf1, ca1,
Tetra- part cf2 and ca2；
Wherein, the cf1 is the capacitance between broach in the first kind metal layer of same layer；
Capacitances of the ca1 between broach in broach in neighbouring first kind metal layer and Second Type metal layer；
The cf2 is the capacitance between broach in the Second Type metal layer of same layer；
The ca2 is the capacitance between broach in neighbouring Second Type metal layer.
8. according to the method described in claim 6, it is characterized in that, the model equation includes following variable：Metal-insulator
Bottom metal layers, metal layer at top in body-metal capacitance model, in metal-insulator-metal capacitor model the length of broach and
Number.
9. according to the method described in claim 8, it is characterized in that, by changing the variable, different test structures is obtained
Model, and corresponding capacitance is calculated, to establish the model side between the capacitance and the test structure model
Formula and format.
10. according to the method described in claim 8, it is characterized in that, the bottom metal layers select the test structure model
Metal layer other than the two metal layers of the top；
The metal layer at top selects the test structure model in addition to bottom metal layer and the topmost metal layer
Any intermediate metal layer.
11. according to the method described in claim 8, it is characterized in that, the length of the broach is 3um~100um；
The number of the broach is 3~500.
12. according to the method described in claim 8, it is characterized in that, when the metal layer that the bottom metal layers are selected is metal
It is effective with the relevant formula of metal layer M1 when layer M1, it uses and 1 relevant formula of metal layer at this time；
As the metal layer non-metallic layer M1 that the bottom metal layers are selected, and select from metal layer M2 to the test structure model
It is invalid with the relevant formula of metal layer M1 when any metal layer of the metal layer other than the two metal layers of the top, with metal layer
The incoherent formula of M1 are effective.
13. according to the method described in claim 1, it is characterized in that, the step (c) includes following sub-step：
Step (c-1) extracts suitable curve according to the model equation, determines the variable in the model equation, establishes
Metal-insulator-metal capacitor model.
14. according to the method for claim 13, which is characterized in that the method is further comprising the steps of：
Influence of the step (c-2) by voltage and temperature to capacitance is added in the metal-insulator-metal capacitor model, with
Obtain more accurate model.
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| CN1734763A (en) * | 2004-08-13 | 2006-02-15 | 上海华虹Nec电子有限公司 | MIM capacitor on CMOS device and manufacturing method thereof |
| CN102012950A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | MIM (Metal-Insulator-Metal) capacitance modeling method and capacitance value acquiring method |
| CN102184281A (en) * | 2011-04-28 | 2011-09-14 | 上海宏力半导体制造有限公司 | Metal-insulator-metal (MIM) capacitor mismatch model and establishing method thereof |
| CN102487055A (en) * | 2010-12-01 | 2012-06-06 | 上海华虹Nec电子有限公司 | Metal-oxide-metal capacitor structure |
| CN102800646A (en) * | 2012-08-17 | 2012-11-28 | 中国科学院微电子研究所 | Capacitor structure |
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| US8207569B2 (en) * | 2007-06-06 | 2012-06-26 | Qualcomm, Incorporated | Intertwined finger capacitors |
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Patent Citations (5)
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|---|---|---|---|---|
| CN1734763A (en) * | 2004-08-13 | 2006-02-15 | 上海华虹Nec电子有限公司 | MIM capacitor on CMOS device and manufacturing method thereof |
| CN102012950A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | MIM (Metal-Insulator-Metal) capacitance modeling method and capacitance value acquiring method |
| CN102487055A (en) * | 2010-12-01 | 2012-06-06 | 上海华虹Nec电子有限公司 | Metal-oxide-metal capacitor structure |
| CN102184281A (en) * | 2011-04-28 | 2011-09-14 | 上海宏力半导体制造有限公司 | Metal-insulator-metal (MIM) capacitor mismatch model and establishing method thereof |
| CN102800646A (en) * | 2012-08-17 | 2012-11-28 | 中国科学院微电子研究所 | Capacitor structure |
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