CN110196984B - High-speed broadband modeling method, system, device and storage medium - Google Patents

High-speed broadband modeling method, system, device and storage medium Download PDF

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CN110196984B
CN110196984B CN201811488761.0A CN201811488761A CN110196984B CN 110196984 B CN110196984 B CN 110196984B CN 201811488761 A CN201811488761 A CN 201811488761A CN 110196984 B CN110196984 B CN 110196984B
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李跃进
高成楠
王松松
史阳楠
卢启军
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Xidian University
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Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed broadband modeling method, a high-speed broadband modeling system, a high-speed broadband modeling device and a storage medium. Acquiring parameter information of the TSV; performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model; and obtaining an equivalent circuit model according to the three-dimensional structure model. According to the invention, through the mode of establishing the three-dimensional structure model by simulating the TSV and analyzing the three-dimensional structure model to establish the equivalent model, the equivalent circuit model is established by calculating MOS parasitic capacitance formed by the TSV and the oxide layer and the silicon substrate and capacitance, resistance, inductance and conductance naturally formed by bonding salient points of the multilayer interconnection structure, and the influence of eddy current loss, parasitic effect and proximity effect on the high-frequency transmission of the TSV is reduced.

Description

High-speed broadband modeling method, system, device and storage medium
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed broadband modeling method, a high-speed broadband modeling system, a high-speed broadband modeling device and a storage medium.
Background
In a Three-Dimensional Integrated Circuit (3D-IC), Through Silicon Vias (TSVs) are a key part for realizing vertical interconnection between a plurality of chips. The three-dimensional integrated circuit (3-D IC) can interconnect modules of different processes, thereby improving the integration level, shortening the interconnection line, reducing the interconnection delay, reducing the power consumption of the circuit and reducing the cost of the integrated circuit. Although three-dimensional integrated circuits have been developed, there is still a need to fully analyze the transmission characteristics of signals. The method for full-wave numerical simulation is accurate, but low in speed, needs to consume extremely large memory resources, and is not suitable for analyzing and optimizing design in large-scale integrated circuit analysis.
At present, many circuit models of practical structures and methods have been proposed, however, eddy current loss, proximity effect, and metal-oxide-semiconductor (MOS) parasitic capacitance formed by TSV and silicon substrate, parasitic effect of bonding bump in vertical interconnection have a great influence on high frequency transmission in gigahertz high frequency transmission.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high-speed wide-screen modeling method for three-dimensional integrated interconnection. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a high-speed wide-screen band modeling method for three-dimensional integrated interconnection, which comprises the following steps:
acquiring parameter information of the TSV;
performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
and obtaining an equivalent circuit model according to the three-dimensional structure model.
In one embodiment of the present invention, the equivalent circuit model is obtained from a three-dimensional structure model, including,
obtaining impedance and admittance according to the three-dimensional structure model;
a circuit model is established based on the impedance and the admittance.
In one embodiment of the invention, the impedance Z is Z ═ Zbump+ZTSV，ZbumpFor bonding bump impedance, ZTSVIs the series impedance of the TSV.
In one embodiment of the present invention, the parameter information includes one or more of a radius of the TSV, a TSV pitch, a height of the TSV, a thickness of the oxide layer, a height of the bonding bump, and a radius of the bonding bump.
In one embodiment of the invention, the external inductance L of the TSVouter，
Figure GDA0002124201200000021
Figure GDA0002124201200000022
WdepIs the maximum width of the depletion layer, phifpIs the fermi potential of the holes,siis a relative dielectric of a silicon substrateThe constant number is a constant number,
Figure GDA0002124201200000023
is the second type of zeroth order function of the Hankel function,siis the damping factor, t, of the silicon substrateoxIs the thickness of the insulating layer, muTSVAnd Na is the doping concentration of the substrate, which is the relative permeability of the TSV.
The invention also provides a high-speed broadband modeling system for the three-dimensional integrated circuit, which comprises a data acquisition module, a simulation module and a model construction module;
the data acquisition module is used for acquiring parameter information of the TSV;
the simulation module is used for carrying out first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
and the model construction module is used for obtaining an equivalent circuit model according to the three-dimensional structure model.
The invention also provides high-speed broadband modeling equipment for the three-dimensional integrated circuit, which comprises an information acquisition device, a processor and a memory, wherein the memory is stored with a computer program, and the processor executes the computer program by the following steps:
acquiring parameter information of the TSV;
performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
and obtaining an equivalent circuit model according to the three-dimensional structure model.
The invention also provides a storage device having stored thereon a computer program which, when executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, through the mode of establishing the three-dimensional structure model by simulating the TSV and analyzing the three-dimensional structure model to establish the equivalent model, the equivalent circuit model is established by calculating MOS parasitic capacitance formed by the TSV and the oxide layer and the silicon substrate and capacitance, resistance, inductance and conductance naturally formed by bonding salient points of the multilayer interconnection structure, and the influence of eddy current loss, parasitic effect and proximity effect on the high-frequency transmission of the TSV is reduced.
Drawings
Fig. 1 is a flow chart of a high-speed broadband modeling method according to an embodiment of the present invention;
fig. 2 is a TSV cross-sectional view of a high-speed broadband modeling method according to an embodiment of the present invention;
FIG. 3 is a top view of FIG. 2;
fig. 4 is a three-dimensional structure model diagram of a high-speed broadband modeling method according to an embodiment of the present invention;
fig. 5 is a schematic side interface diagram of a high-speed broadband modeling method according to an embodiment of the present invention;
fig. 6 is an equivalent circuit model of a high-speed broadband modeling method according to an embodiment of the present invention;
fig. 7 is a pi-type equivalent circuit model of a high-speed broadband modeling method according to an embodiment of the present invention;
fig. 8 is a return loss curve diagram of an equivalent circuit model of a high-speed broadband modeling method according to an embodiment of the present invention;
fig. 9 is an insertion loss curve diagram of an equivalent circuit model of a high-speed broadband modeling method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
As shown in fig. 1, an embodiment of the present invention provides a high-speed wide-screen band modeling method for three-dimensional integrated interconnection, which includes the following steps:
acquiring parameter information of the TSV;
performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
and obtaining an equivalent circuit model according to the three-dimensional structure model.
In one embodiment of the invention, the equivalent circuit model is derived from a three-dimensional structure model, including,
obtaining impedance and admittance according to the three-dimensional structure model;
a circuit model is established based on the impedance and the admittance.
In one embodiment of the invention, the impedance Z is Z ═ Zbump+ZTSV，ZbumpFor bonding bump impedance, ZTSVIs the series impedance of the TSV.
In one embodiment of the present invention, the parameter information includes one or more of a radius of the TSV, a TSV pitch, a height of the TSV, a thickness of the oxide layer, a height of the bonding bump, and a radius of the bonding bump.
In one embodiment of the present invention, the TSV pitch pTSVSatisfy the requirement of
Figure GDA0002124201200000051
rTSVIs the TSV radius.
In one embodiment of the invention, the external inductance L of the TSVouter，
Figure GDA0002124201200000052
Figure GDA0002124201200000053
WdepIs the maximum width of the depletion layer, phifpIs the fermi potential of the holes,siis the relative dielectric constant of the silicon substrate,
Figure GDA0002124201200000054
is the second type of zeroth order function of the Hankel function,siis the damping factor, t, of the silicon substrateoxIs the thickness of the insulating layer, muTSVAnd Na is the doping concentration of the substrate, which is the relative permeability of the TSV.
Specifically, the equivalent resistance, the equivalent capacitance, the equivalent inductance and the equivalent conductance of the three-dimensional structure model are obtained according to the TSV three-dimensional structure model, and the specific process is as follows:
(1) calculating the internal impedance Zmetal；
Figure GDA0002124201200000055
J0And J1Respectively the zeroth order and the first order of the first type of Bessel function;cuis the damping factor of the TSV; k is a radical ofpIs a proximity factor; sigmatsvIs the conductivity of the TSV; r isTSVIs the TSV radius; omega is the angular frequency of the transmission signal; mu.stsvPermeability of TSV.
(2) Equivalent resistance R for calculating substrate eddy current losssub；
Figure GDA0002124201200000056
Figure GDA0002124201200000057
A zeroth order function of a second type of Hankel function;siis the damping factor of the silicon substrate,siis the damping factor of the silicon substrate; t is toxIs the thickness of the insulating layer; wdepIs the maximum width of the depletion layer.
(3) Calculating the external inductance Louter；
Figure GDA0002124201200000061
WdepIs the maximum width of the depletion layer, phifpIs the fermi potential of the holes,siis the relative dielectric constant of the silicon substrate,
Figure GDA0002124201200000062
is the second type of zeroth order function of the Hankel function,siis the damping factor, t, of the silicon substrateoxIs the thickness of the insulating layer, muTSVAnd Na is the doping concentration of the substrate, which is the relative permeability of the TSV.
(4) Calculating series impedance Z of TSV Unit heightTSV；
ZTSV＝2Zmetal+jwLouter+Rsub。
(5) Calculating loop impedance Z in the equivalent circuit model;
Figure GDA0002124201200000063
Zbump＝4Zmetal_bump，
will calculate ZbumpAnd ZTSVSubstituting formula, Z ═ Zbump+ZTSVThe loop impedance Z is obtained.
(6) Calculating the capacitance of each part in the equivalent circuit;
a. calculating the capacitance C of the oxide layerOX
Figure GDA0002124201200000064
Wherein h isTSVIs the TSV height; h isIMDIs the dielectric layer height; t is tOXIs the thickness of the insulating layer.
b. Bonding bump capacitor Cbump1And Cbump2
Bonding bumps and a silicon substrate are used as upper and lower capacitor plates of a capacitor, an IMD (in-mold decoration) layer of a metal piece dielectric serves as an insulating layer, and the bonding bump capacitors of two adjacent TSVs are respectively Cbump1And Cbump2；
Figure GDA0002124201200000065
Figure GDA0002124201200000071
Wherein r isbump1And rbump2The radius of the bonding salient point is the same as that of the bonding salient point;r,IMDis the dielectric constant of the metal dielectric layer;
c. calculating the capacitance C of the unfilled layerUnderfill
A parallel wire capacitor C is formed between the signal bonding salient point and the ground bonding salient point as well as the Underfill layerUnderfill，
Figure GDA0002124201200000072
Whereinr,UnderfillIs the relative dielectric constant of the unfilled layer, wherein hbumpIs the height of the bonding bump.
d. Calculating the capacitance C of the metal dielectric layerIMD
Parallel conductor capacitor C is formed between two adjacent TSVs and formed by IMD layerIMD，
Figure GDA0002124201200000073
hIMDIs the height of the metal dielectric layer;
e. calculating bottom oxide layer capacitance Cbottom
A parallel lead capacitor C is formed between two adjacent TSVs and the bottom oxide layerbottom，
Figure GDA0002124201200000074
oxIs the dielectric constant of silicon dioxide; t is tox，botIs the thickness of the bottom oxide layer.
f. Calculating the capacitance C of the silicon substrateSi
Figure GDA0002124201200000075
Effective TSV height is (h)TSV-2hIMD)。
g. Calculating depletion layer capacitance Cdep
Figure GDA0002124201200000076
(7) Calculating the conductance G of a silicon substrateTSV
si＝si'-jsi”，1/ρ＝2πf”，tan|d|＝1/(2πρfsi)＝si'/si”：
Figure GDA0002124201200000081
WhereinρsiIs the silicon substrate resistivity.
Specifically, as shown in fig. 6, a primary equivalent circuit model is drawn based on the calculated resistance, capacitance, inductance, and conductance of each portion, and the primary equivalent circuit model is simplified to a pi-type equivalent circuit model (equivalent circuit model).
Specifically, as shown in fig. 8 and 9, a second simulation is performed on the three-dimensional structure model of the TSV using HFSS, and curves of return loss and insertion loss of the TSV transmission characteristic are plotted.
Specifically, the values of return loss and insertion loss of the TSV equivalent circuit model are calculated according to the equivalent circuit model,
1) the ABCD matrix is calculated as follows:
Figure GDA0002124201200000082
wherein C iseq1And Ceq2As follows:
Figure GDA0002124201200000083
since TSV is a symmetric structure model, Cbump1And Cbump2Same, therefore Ceq1And Ceq2The same is true.
In summary, the equivalent circuit model derived is shown in fig. 7. From the equivalent circuit model, the [ ABCD ] matrix can be derived as follows:
Figure GDA0002124201200000084
2) the [ S ] parameter matrix of the equivalent circuit model:
Figure GDA0002124201200000085
Dscomprises the following steps:
Figure GDA0002124201200000086
wherein S11As return loss value, S12Is the insertion loss value.
Specifically, the height h of the TSV is changedtsvTesting the return loss and insertion loss of the TSV model and the S of the equivalent model within the range of 100MHz-100GH]Degree of parametric curve fitting. As can be seen from FIGS. 8 and 9, the frequency is in the range of 100MHz-100GHz, and S of the equivalent circuit model11Parametric curve and S21Parameter curve and HFSS model derived [ S ]]The parameter results are very similar at different TSV heights, when frequency<At 10GHz, S11Maximum error less than 3%, when frequency>When 10GHz is adopted, the maximum error is less than 2%; s21In the range of 100MHz-100GHz, the maximum error is less than 5%, so that the model structure of the high-frequency equivalent circuit model and the TSV in the HFSS has extremely high goodness of fit. The traditional equivalent model has larger errors in high-frequency signal transmission because the traditional model does not consider the MOS capacitance effect and the silicon substrate eddy current loss and the like caused by silicon substrate doping. The correctness and accuracy of the equivalent circuit model proposed herein are derived therefrom.
The invention also provides a high-speed broadband modeling system for the three-dimensional integrated circuit, which comprises a data acquisition module, a simulation module and a model construction module;
the data acquisition module is used for acquiring parameter information of the TSV;
the simulation module is used for carrying out first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
and the model construction module is used for obtaining an equivalent circuit model according to the three-dimensional structure model.
The invention also provides high-speed broadband modeling equipment for the three-dimensional integrated circuit, which comprises an information acquisition device, a processor and a memory, wherein the memory is stored with a computer program, and the processor executes the computer program by the following steps:
acquiring parameter information of the TSV;
performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
and obtaining an equivalent circuit model according to the three-dimensional structure model.
The invention also provides a storage device having stored thereon a computer program which, when executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. A high-speed broadband modeling method is characterized in that: the method comprises the following steps:
acquiring parameter information of the TSV;
performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
obtaining an equivalent circuit model according to the three-dimensional structure model;
the obtaining of the equivalent circuit model according to the three-dimensional structure model includes: obtaining impedance and admittance according to the three-dimensional structure model; establishing a circuit model according to the impedance and the admittance;
wherein, the external inductance L of the TSVouterComprises the following steps:
Figure FDA0002692354900000011
Figure FDA0002692354900000012
Wdepis the maximum width of the depletion layer, phifpIs the fermi potential of the holes,siis the relative dielectric constant of the silicon substrate,
Figure FDA0002692354900000013
is the second type of zeroth order function of the Hankel function,siis the damping factor, t, of the silicon substrateoxIs the thickness of the insulating layer, muTSVRelative permeability of TSV, Na as substrate doping concentration, rTSVIs the TSV radius.
2. The high-speed wide-band modeling method of claim 1, wherein: the impedance Z is Z ═ Zbump+ZTSV，ZbumpFor bonding bump impedance, ZTSVIs the series impedance of the TSV.
3. The high-speed wide-band modeling method of claim 1, wherein: the parameter information comprises one or more of the radius of the TSV, the TSV interval, the height of the TSV, the thickness of the oxide layer, the height of the bonding salient point and the radius of the bonding salient point.
4. A high-speed broadband modeling system, characterized in that: the simulation system comprises a data acquisition module, a simulation module and a model construction module;
the data acquisition module is used for acquiring parameter information of the TSV;
the simulation module is used for carrying out first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
the model building module is used for obtaining a built equivalent circuit model according to the three-dimensional structure model;
the model building module obtains an equivalent circuit model according to the three-dimensional structure model, and comprises:
obtaining impedance and admittance according to the three-dimensional structure model; establishing a circuit model according to the impedance and the admittance;
wherein, the external inductance L of the TSVouterComprises the following steps:
Figure FDA0002692354900000021
Figure FDA0002692354900000022
Wdepis the maximum width of the depletion layer, phifpIs the fermi potential of the holes,siis the relative dielectric constant of the silicon substrate,
Figure FDA0002692354900000023
is the second type of zeroth order function of the Hankel function,siis the damping factor, t, of the silicon substrateoxIs the thickness of the insulating layer, muTSVRelative permeability of TSV, Na as substrate doping concentration, rTSVIs the TSV radius.
5. A high-speed broadband modeling device is characterized in that: the system comprises an information acquisition device, a processor and a memory, wherein a computer program is stored in the memory, and the processor executes the computer program by the steps of:
acquiring parameter information of the TSV;
performing first simulation on the TSV according to the parameter information to obtain a TSV three-dimensional structure model;
obtaining an equivalent circuit model according to the three-dimensional structure model;
the obtaining of the equivalent circuit model according to the three-dimensional structure model includes:
obtaining impedance and admittance according to the three-dimensional structure model; establishing a circuit model according to the impedance and the admittance;
wherein, the external inductance L of the TSVouterComprises the following steps:
Figure FDA0002692354900000024
Figure FDA0002692354900000025
Wdepis the maximum width of the depletion layer, phifpIs the fermi potential of the holes,siis the relative dielectric constant of the silicon substrate,
Figure FDA0002692354900000026
is the second type of zeroth order function of the Hankel function,siis the damping factor, t, of the silicon substrateoxIs the thickness of the insulating layer, muTSVRelative permeability of TSV, Na as substrate doping concentration, rTSVIs the TSV radius.
6. A storage medium having a computer program stored thereon, characterized in that: the computer program, when executed by a processor, implementing the steps of the method of any one of claims 1 to 3.
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