CN103676335A - Display panel, manufacturing method and display device - Google Patents
Display panel, manufacturing method and display device Download PDFInfo
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- CN103676335A CN103676335A CN201310664326.XA CN201310664326A CN103676335A CN 103676335 A CN103676335 A CN 103676335A CN 201310664326 A CN201310664326 A CN 201310664326A CN 103676335 A CN103676335 A CN 103676335A
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Abstract
The invention provides a display panel, a manufacturing method and a display device. The display panel comprises an array substrate, a color film substrate and spacers arranged between the array substrate and the color film substrate, the spacers comprise a plurality of setting combinations, each setting combination comprises at least one spacer, spacers in the setting combinations comprise first parts arranged on the array substrate and second parts arranged on the color film substrate, and relative displacement between the array substrate and the color film substrate is limited through the counterpoint combination of the first parts and the second parts. By the adoption of the manufacturing method, the relative displacement between the array substrate and the color film substrate when external force is exerted on the display panel be effectively avoided, and therefore the phenomenon of color mixture is avoided.
Description
Technical field
The present invention relates to display technique field, refer in particular to a kind of display panel and manufacture method, display device.
Background technology
Along with social progress and development in science and technology, Thin Film Transistor-LCD (TFT-LCD) has become the main product that current era shows field, has played vital effect in commercial production, daily life, is more and more subject to people's favor.
Display panels can show good display effect in normal use; but when being subject to external force; there will be certain display defect and bad; as when press...withing one's finger pressure panel surface; what there will be " water ripples " sample bounces displacement Touch mura; and when display panels is placed in module internal; often can have the dimensions difference due to the spatial domain panel that module internal card is put panel; thereby likely cause stressed generation relative displacement between the array base palte of display panels and color membrane substrates, thereby occur " colour mixture " phenomenon.
Summary of the invention
The object of technical solution of the present invention is to provide a kind of display panel and manufacture method, display device, the relative displacement in the time of can effectively avoiding display panel to be subject to external force between array base palte and color membrane substrates, thus avoid the generation of " colour mixture " phenomenon.
The invention provides a kind of display panel, comprise array base palte, color membrane substrates, be arranged at the chock insulator matter between described array base palte and described color membrane substrates, wherein, described chock insulator matter comprises a plurality of combinations that arrange, described in each, arrange and in combination, comprise at least one chock insulator matter, and the described described chock insulator matter arranging in combination comprises the first being arranged on array base palte and is arranged at the second portion on color membrane substrates, by described first and described second portion to bit pattern, the relative displacement between restriction array base palte and color membrane substrates.
Preferably, display panel described above, described setting comprises at least two chock insulator matters in combination, wherein the first chock insulator matter is arranged on array base palte, forms described first, and the second chock insulator matter is arranged on color membrane substrates, form described second portion, described the first chock insulator matter is positioned at described the second chock insulator matter along a side of first direction, and described the first chock insulator matter and described the second chock insulator matter adjacent, restriction color membrane substrates with respect to array base palte, along first direction, move.
Preferably, display panel described above, described setting also comprises the 3rd chock insulator matter being arranged on array base palte and is arranged at the 4th chock insulator matter on color membrane substrates in combination, wherein said the 3rd chock insulator matter is positioned at described the 4th chock insulator matter along a side of second direction, and described the 3rd chock insulator matter and described the 4th chock insulator matter are adjacent, restriction color membrane substrates moves along second direction with respect to array base palte, and wherein said second direction is contrary with described first direction.
Preferably, display panel described above, described setting also comprises the 5th chock insulator matter being arranged on array base palte and is arranged at the 6th chock insulator matter on color membrane substrates in combination, wherein said the 5th chock insulator matter is positioned at described the 6th chock insulator matter along a side of third direction, and described the 5th chock insulator matter and described the 6th chock insulator matter are adjacent, restriction color membrane substrates moves along third direction with respect to array base palte, and wherein said third direction is vertical with described first direction.
Preferably, display panel described above, described setting also comprises the 7th chock insulator matter being arranged on array base palte and is arranged at the 8th chock insulator matter on color membrane substrates in combination, wherein said the 7th chock insulator matter is positioned at described the 8th chock insulator matter along a side of fourth direction, and described the 7th chock insulator matter and described the 8th chock insulator matter are adjacent, restriction color membrane substrates moves along fourth direction with respect to array base palte, and wherein said fourth direction is contrary with described third direction.
Preferably, display panel described above, on described color membrane substrates, four edges of a sub-pixel unit are respectively arranged with a chock insulator matter; On described array base palte, four edges of a pixel electrode are respectively arranged with a chock insulator matter.
Preferably, display panel described above, described setting comprises a chock insulator matter in combination, wherein first's structure is arranged on array base palte, forms described first, and second portion structure is arranged on color membrane substrates, form described second portion, between described first structure and described second portion structure, with inserting mode contraposition, engage, be combined as a chock insulator matter, and can limit the relative displacement between array base palte and color membrane substrates.
Preferably, display panel described above, described first direction parallels with one of them edge of described color membrane substrates or described array base palte.
The present invention also provides a kind of display device, comprises the display panel described in as above any one.
The present invention also provides a kind of manufacture method of display panel, comprising:
Make the step of color membrane substrates, the wherein said step of making color membrane substrates is included in the step that forms the first of chock insulator matter on color membrane substrates;
Make the step of array base palte, the wherein said step of making array base palte is included in the step that forms the second portion of chock insulator matter on array base palte;
Color membrane substrates box relative to array base palte, makes described first and described second portion to bit pattern.
At least one in specific embodiment of the invention technique scheme has following beneficial effect:
By improving the structure of chock insulator matter, chock insulator matter is constituted by a plurality of settings, the chock insulator matter part arranging in combination is arranged on array base palte, another part is arranged on color membrane substrates, by two-part to bit pattern, limit the relative displacement between array base palte and color membrane substrates, thereby effectively alleviate display panel, because being subject to external force, cause producing relative displacement between color membrane substrates and array base palte, cause the problem of " colour mixture " phenomenon.
Accompanying drawing explanation
Fig. 1 represents described in first embodiment of the invention that, in display panel, chock insulator matter arranges the schematic diagram of structure;
Fig. 2 represents described in second embodiment of the invention that, in display panel, chock insulator matter arranges the first stress schematic diagram of structure;
Fig. 3 represents described in second embodiment of the invention that, in display panel, chock insulator matter arranges the second stress schematic diagram of structure;
Fig. 4 represents in second embodiment of the invention, the arrangement architecture schematic diagram of chock insulator matter on display panel;
Fig. 5 represents described in third embodiment of the invention that, in display panel, chock insulator matter arranges the schematic diagram of structure.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
Display panel of the present invention, comprise array base palte, color membrane substrates, be arranged at the chock insulator matter between described array base palte and described color membrane substrates, described chock insulator matter comprises a plurality of combinations that arrange, described in each, arrange and in combination, comprise at least one chock insulator matter, and the described described chock insulator matter arranging in combination comprises the first being arranged on array base palte and is arranged at the second portion on color membrane substrates, by described first and described second portion to bit pattern, the relative displacement between restriction array base palte and color membrane substrates.
Display panel described in the specific embodiment of the invention, by improving the structure of chock insulator matter, chock insulator matter is constituted by a plurality of settings, the chock insulator matter part arranging in combination is arranged on array base palte, another part is arranged on color membrane substrates, by two-part, to bit pattern, limits the relative displacement between array base palte and color membrane substrates, thereby effectively alleviate display panel, because being subject to external force, cause producing relative displacement between color membrane substrates and array base palte, cause the problem of " colour mixture " phenomenon.
If Fig. 1 is the structural representation of display panel in first embodiment of the invention.Consult shown in Fig. 1, identical with the structure of the display panel of prior art, display panel of the present invention comprises color membrane substrates 100 and array base palte 200, wherein between color membrane substrates 100 and array base palte 200, be provided with liquid crystal layer, in liquid crystal layer, be provided with for playing the chock insulator matter 300 of the thick effect of supporting case.Conventionally chock insulator matter 300 comprises cylindrical spacer (Post Spacer, be called for short PS) and spherical chock insulator matter (Ball Spacer, be called for short BS), the present invention is by the architecture advances to chock insulator matter 300, reach effective alleviation display panel and because being subject to external force, cause producing between color membrane substrates and array base palte the problem of relative displacement, following submitted to the architecture advances that relates to chock insulator matter both can be applied to cylindrical spacer, also can be applied to spherical chock insulator matter.
Those skilled in the art should be able to manage the concrete structure of array base palte and color membrane substrates in display panel, and this part is not improvement emphasis of the present invention, at this, are not described in detail.
In first embodiment of the invention, set chock insulator matter between color membrane substrates 100 and array base palte 200, comprise a plurality of combinations that arrange, in this arranges combination, wherein a part of chock insulator matter is arranged on color membrane substrates 100, another part chock insulator matter is arranged on array base palte 200, by two parts, to bit pattern, reaches the effect of restriction color membrane substrates 100 and array base palte 200 relative displacements.
In conjunction with Fig. 1, in first embodiment of the invention, chock insulator matter comprises a plurality of combination I that arrange, this arranges in combination I and comprises the first chock insulator matter 310 and the second chock insulator matter 320, wherein the first chock insulator matter 310 is arranged on array base palte 200, the second chock insulator matter 320 is arranged on color membrane substrates 100, the first chock insulator matter 310 is positioned at the right side (first direction) of the second chock insulator matter 320 along continuous straight runs, and the first chock insulator matter 310 and the second chock insulator matter 320 are adjacent, by this kind of set-up mode, when color membrane substrates 100 is subject to mobile external force to the right of level, barrier effect due to the first chock insulator matter 310, reach the effect that restriction color membrane substrates 100 levels move to right.
The present invention also provides the display panel of the second embodiment, as shown in Figure 2, chock insulator matter comprises a plurality of combination II that arrange, this arrange combination comprise in II arrange in combination I shown in the first chock insulator matter 310 and second chock insulator matter 320 of structure, the first chock insulator matter 310 is arranged on array base palte 200, the second chock insulator matter 320 is arranged on color membrane substrates 100, the first chock insulator matter 310 is positioned at the right side (first direction) of the second chock insulator matter 320 along continuous straight runs, and the first chock insulator matter 310 and the second chock insulator matter 320 are adjacent, by this kind of set-up mode, when color membrane substrates 100 is subject to mobile external force to the right of level, barrier effect due to the first chock insulator matter 310, reach the effect that restriction color membrane substrates 100 levels move to right, this arranges in combination II and also comprises the 3rd chock insulator matter 330 and the 4th chock insulator matter 340 in addition, wherein the 3rd chock insulator matter 330 is arranged on array base palte 200, the 4th chock insulator matter 340 is arranged on color membrane substrates 100, the 3rd chock insulator matter 330 is positioned at the left side (second direction) of the 4th chock insulator matter 340 along continuous straight runs, and the 3rd chock insulator matter 330 and the 4th chock insulator matter 340 are adjacent, by this kind of set-up mode, when color membrane substrates 100 is subject to mobile external force left of level, due to the barrier effect of the 3rd chock insulator matter 330, reach the effect of restriction color membrane substrates 100 horizontal left.
Fig. 4, for representing the arrangement architecture schematic diagram of chock insulator matter on display panel, is coated with bullet and represents the chock insulator matter on color membrane substrates 100, and white round dot represents the chock insulator matter on array base palte 200.Wherein, on color membrane substrates 100, four edges of a sub-pixel unit 110 are respectively arranged with a chock insulator matter; On array base palte 200, four edges of a pixel electrode 210 are respectively arranged with a chock insulator matter.On display panel, be configured to the horizontal chock insulator matter of multirow.In conjunction with Fig. 2, in the horizontal direction of display panel, chock insulator matter is arranged in order and is formed by a plurality of combination II that arrange, by this kind of set-up mode, when thering is relative displacement trend to the right of level between color membrane substrates 100 and array base palte 200, utilize the barrier effect that the first chock insulator matter 310 in combination II is respectively set, restriction relatively moving between the two.When thering is relative displacement trend left of level between color membrane substrates 100 and array base palte 200, utilize the barrier effect that the 3rd chock insulator matter 330 in combination II is respectively set, restriction relatively moving between the two, as shown in Figure 3.
Preferably, in conjunction with Fig. 4, for the vertically relative displacement of (along the short side direction of display panel) between restriction color membrane substrates 100 and array base palte 200, the chock insulator matter on display panel also comprises the chock insulator matter that multiple row is arranged at vertical direction, and the combination that arranges that therefore forms this chock insulator matter also comprises:
Be arranged at the 5th chock insulator matter 350 on array base palte 200 and be arranged at the 6th chock insulator matter 360 on color membrane substrates 100, wherein said the 5th chock insulator matter 350 is positioned at described the 6th chock insulator matter 360 along a side (Figure 4 shows that a side straight down) of third direction, and described the 5th chock insulator matter 350 is adjacent with described the 6th chock insulator matter 360, restriction color membrane substrates 100 moves along third direction with respect to array base palte 200, wherein said third direction is vertical with described first direction, in the present embodiment, mobile trend straight down between restriction color membrane substrates 100 and array base palte 200,
And comprise and be arranged at the 7th chock insulator matter 370 on array base palte 200 and be arranged at the 8th chock insulator matter 380 on color membrane substrates 100, wherein said the 7th chock insulator matter 370 is positioned at described the 8th chock insulator matter 380 along a side (Fig. 4 is a side straight up) of fourth direction, and described the 7th chock insulator matter 370 is adjacent with described the 8th chock insulator matter 380, restriction color membrane substrates 100 moves along fourth direction with respect to array base palte 200, and wherein said fourth direction is contrary with described third direction.In the present embodiment, mobile trend straight up between restriction color membrane substrates 100 and array base palte 200.
By above-mentioned setting, utilize improved chock insulator matter structure, avoid on display panel between color membrane substrates 100 and array base palte 200 movement along the long limit of display panel, and along the movement of display panel minor face, thereby avoid the generation of mixed color phenomenon.
In addition, the present invention also provides the display panel of the 3rd embodiment, and in the 3rd embodiment, chock insulator matter also can reach the effect of the relative displacement between restriction array base palte and color membrane substrates with another kind of version combination.
As shown in Figure 5, in the 3rd embodiment, the chock insulator matter being arranged between array base palte 200 and color membrane substrates 100 is also to be constituted by a plurality of settings, wherein each arranges to combine and comprises a chock insulator matter 300, first's structure 301 of this chock insulator matter 300 is arranged on array base palte 200, second portion structure 302 is arranged on color membrane substrates 100, wherein between first's structure 301 and second portion structure 302 structures, with inserting mode contraposition, engage, be combined as a chock insulator matter, and can reach the effect of the relative displacement between restriction array base palte 200 and color membrane substrates 100.
In conjunction with Fig. 5, in the 3rd embodiment, first's structure 301 of chock insulator matter 300 and second portion structure 302 form respectively stepped, and when involutory between array base palte 200 and color membrane substrates 100, two-part structure is combined as a chock insulator matter.Utilize this kind of structure setting, when color membrane substrates 100 has mobile trend to the right of level with respect to array base palte 200, the barrier effect restriction that can utilize first's structure 301 relatively moving between the two; When color membrane substrates 100 has mobile trend left of level with respect to array base palte 200, the barrier effect restriction that can utilize second portion structure 302 relatively moving between the two.
Therefore, the 3rd example structure shown in Fig. 5 also can reach the relative displacement of avoiding between color membrane substrates and array base palte, thereby avoids the problem of " colour mixture " phenomenon generation of display panel.
The present invention also provides a kind of display device with above-mentioned display panel structure, and the concrete structure of described display panel can be consulted above description, does not repeat them here.
Further aspect of the present invention also provides a kind of manufacture method of above-mentioned display panel, comprising:
Make the step of color membrane substrates, the wherein said step of making color membrane substrates is included in the step that forms the first of chock insulator matter on color membrane substrates;
Make the step of array base palte, the wherein said step of making array base palte is included in the step that forms the second portion of chock insulator matter on array base palte;
Color membrane substrates box relative to array base palte, makes described first and described second portion to bit pattern.
Those skilled in the art should be able to understand in the manufacture process of display device, make the specific embodiment of color membrane substrates and array base palte, and by color membrane substrates box relative to array base palte, make the specific embodiment of display device, at this, are not described in detail.
In the specific embodiment of the invention, above-mentioned mentioned " level ", " vertically ", " left ", " to the right ", " make progress " and " downwards " about the description in orientation, all to take the state that arranges of beholder's display panel while conventionally watching display device to describe as example, also be the arrange state of display panel vertical plane during to beholder, when display panel is rectangle, horizontal direction is the direction parallel with the long side direction of display panel, vertical direction is the direction parallel with the short side direction of display panel, it is only the structure that clearly demonstrates chock insulator matter in display panel of the present invention that above-mentioned orientation limits, but chock insulator matter structure is not limited with the setting orientation in above-mentioned.For example, color membrane substrates is not limited to parallel with respect to the edge of display panel with the orientation that arranges of two chock insulator matters on array base palte, can be also for example the edge offset certain angle of relative level direction or vertical direction, in order to limit the movement of oblique direction between color membrane substrates and array base palte.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a display panel, comprise array base palte, color membrane substrates, be arranged at the chock insulator matter between described array base palte and described color membrane substrates, it is characterized in that, described chock insulator matter comprises a plurality of combinations that arrange, described in each, arrange and in combination, comprise at least one chock insulator matter, and the described described chock insulator matter arranging in combination comprises the first being arranged on array base palte and is arranged at the second portion on color membrane substrates, by described first and described second portion to bit pattern, the relative displacement between restriction array base palte and color membrane substrates.
2. display panel as claimed in claim 1, it is characterized in that, described setting comprises at least two chock insulator matters in combination, wherein the first chock insulator matter is arranged on array base palte, forms described first, and the second chock insulator matter is arranged on color membrane substrates, form described second portion, described the first chock insulator matter is positioned at described the second chock insulator matter along a side of first direction, and described the first chock insulator matter and described the second chock insulator matter adjacent, restriction color membrane substrates with respect to array base palte, along first direction, move.
3. display panel as claimed in claim 2, it is characterized in that, described setting also comprises the 3rd chock insulator matter being arranged on array base palte and is arranged at the 4th chock insulator matter on color membrane substrates in combination, wherein said the 3rd chock insulator matter is positioned at described the 4th chock insulator matter along a side of second direction, and described the 3rd chock insulator matter and described the 4th chock insulator matter are adjacent, restriction color membrane substrates moves along second direction with respect to array base palte, and wherein said second direction is contrary with described first direction.
4. display panel as claimed in claim 2, it is characterized in that, described setting also comprises the 5th chock insulator matter being arranged on array base palte and is arranged at the 6th chock insulator matter on color membrane substrates in combination, wherein said the 5th chock insulator matter is positioned at described the 6th chock insulator matter along a side of third direction, and described the 5th chock insulator matter and described the 6th chock insulator matter are adjacent, restriction color membrane substrates moves along third direction with respect to array base palte, and wherein said third direction is vertical with described first direction.
5. display panel as claimed in claim 2, it is characterized in that, described setting also comprises the 7th chock insulator matter being arranged on array base palte and is arranged at the 8th chock insulator matter on color membrane substrates in combination, wherein said the 7th chock insulator matter is positioned at described the 8th chock insulator matter along a side of fourth direction, and described the 7th chock insulator matter and described the 8th chock insulator matter are adjacent, restriction color membrane substrates moves along fourth direction with respect to array base palte, and wherein said fourth direction is contrary with described third direction.
6. display panel as claimed in claim 1, is characterized in that, on described color membrane substrates, four edges of a sub-pixel unit are respectively arranged with a chock insulator matter; On described array base palte, four edges of a pixel electrode are respectively arranged with a chock insulator matter.
7. display panel as claimed in claim 1, it is characterized in that, described setting comprises a chock insulator matter in combination, wherein first's structure is arranged on array base palte, forms described first, and second portion structure is arranged on color membrane substrates, form described second portion, between described first structure and described second portion structure, with inserting mode contraposition, engage, be combined as a chock insulator matter, and can limit the relative displacement between array base palte and color membrane substrates.
8. display panel as claimed in claim 2, is characterized in that, described first direction parallels with one of them edge of described color membrane substrates or described array base palte.
9. a display device, is characterized in that, comprises the display panel as described in claim 1 to 8 any one.
10. a manufacture method for display panel, is characterized in that, comprising:
Make the step of color membrane substrates, the wherein said step of making color membrane substrates is included in the step that forms the first of chock insulator matter on color membrane substrates;
Make the step of array base palte, the wherein said step of making array base palte is included in the step that forms the second portion of chock insulator matter on array base palte;
Color membrane substrates box relative to array base palte, makes described first and described second portion to bit pattern.
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| CN201310664326.XA CN103676335B (en) | 2013-12-09 | 2013-12-09 | Display floater and manufacture method, display device |
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| CN201310664326.XA CN103676335B (en) | 2013-12-09 | 2013-12-09 | Display floater and manufacture method, display device |
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| CN103676335A true CN103676335A (en) | 2014-03-26 |
| CN103676335B CN103676335B (en) | 2016-06-15 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104635384A (en) * | 2015-03-03 | 2015-05-20 | 合肥京东方光电科技有限公司 | Liquid crystal panel and display device |
| CN104914607A (en) * | 2015-06-16 | 2015-09-16 | 武汉华星光电技术有限公司 | Liquid crystal display and liquid crystal panel thereof |
| CN106802517A (en) * | 2017-04-12 | 2017-06-06 | 京东方科技集团股份有限公司 | A kind of liquid crystal display panel and display device |
| CN107632440A (en) * | 2017-10-09 | 2018-01-26 | 天马微电子股份有限公司 | Display panel and preparation method thereof and display device |
| CN107656403A (en) * | 2017-09-29 | 2018-02-02 | 京东方科技集团股份有限公司 | A kind of curved face display panel and curved-surface display device |
| CN108897175A (en) * | 2018-08-31 | 2018-11-27 | 合肥鑫晟光电科技有限公司 | A kind of display panel and preparation method thereof, display device |
| WO2018223768A1 (en) * | 2017-06-05 | 2018-12-13 | 京东方科技集团股份有限公司 | Liquid crystal panel and manufacturing method thereof |
| CN111458939A (en) * | 2020-06-05 | 2020-07-28 | 业成科技（成都）有限公司 | Liquid crystal display panel, preparation method thereof and electronic equipment |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08114809A (en) * | 1994-10-14 | 1996-05-07 | Sony Corp | Liquid crystal panel and its production |
| CN1223384A (en) * | 1997-12-25 | 1999-07-21 | 夏普公司 | Liquid crystal display device |
| US6118510A (en) * | 1996-07-26 | 2000-09-12 | Sharp Kabushiki Kaisha | Liquid crystal device |
| US20060066801A1 (en) * | 2004-09-29 | 2006-03-30 | Meng-Chi Liu | Liquid crystal display panel and manufacturing method thereof |
| CN101251689A (en) * | 2008-03-31 | 2008-08-27 | 昆山龙腾光电有限公司 | Liquid crystal display panel and apparatus including the same |
| CN101373298A (en) * | 2007-08-20 | 2009-02-25 | 中华映管股份有限公司 | LCD device and manufacture method thereof |
| CN101762916A (en) * | 2008-12-25 | 2010-06-30 | 北京京东方光电科技有限公司 | Array substrate, liquid crystal display panel and manufacturing methods thereof |
-
2013
- 2013-12-09 CN CN201310664326.XA patent/CN103676335B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08114809A (en) * | 1994-10-14 | 1996-05-07 | Sony Corp | Liquid crystal panel and its production |
| US6118510A (en) * | 1996-07-26 | 2000-09-12 | Sharp Kabushiki Kaisha | Liquid crystal device |
| CN1223384A (en) * | 1997-12-25 | 1999-07-21 | 夏普公司 | Liquid crystal display device |
| US20060066801A1 (en) * | 2004-09-29 | 2006-03-30 | Meng-Chi Liu | Liquid crystal display panel and manufacturing method thereof |
| CN101373298A (en) * | 2007-08-20 | 2009-02-25 | 中华映管股份有限公司 | LCD device and manufacture method thereof |
| CN101251689A (en) * | 2008-03-31 | 2008-08-27 | 昆山龙腾光电有限公司 | Liquid crystal display panel and apparatus including the same |
| CN101762916A (en) * | 2008-12-25 | 2010-06-30 | 北京京东方光电科技有限公司 | Array substrate, liquid crystal display panel and manufacturing methods thereof |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9885923B2 (en) | 2015-03-03 | 2018-02-06 | Boe Technology Group Co., Ltd. | Liquid crystal panel and display device |
| CN104635384B (en) * | 2015-03-03 | 2018-03-13 | 合肥京东方光电科技有限公司 | Liquid crystal panel and display device |
| CN104635384A (en) * | 2015-03-03 | 2015-05-20 | 合肥京东方光电科技有限公司 | Liquid crystal panel and display device |
| CN104914607A (en) * | 2015-06-16 | 2015-09-16 | 武汉华星光电技术有限公司 | Liquid crystal display and liquid crystal panel thereof |
| CN104914607B (en) * | 2015-06-16 | 2018-05-11 | 武汉华星光电技术有限公司 | Liquid crystal display and its liquid crystal panel |
| US10656472B2 (en) | 2017-04-12 | 2020-05-19 | Boe Technology Group Co., Ltd. | Liquid crystal display panel and display device |
| CN106802517A (en) * | 2017-04-12 | 2017-06-06 | 京东方科技集团股份有限公司 | A kind of liquid crystal display panel and display device |
| WO2018223768A1 (en) * | 2017-06-05 | 2018-12-13 | 京东方科技集团股份有限公司 | Liquid crystal panel and manufacturing method thereof |
| CN107656403A (en) * | 2017-09-29 | 2018-02-02 | 京东方科技集团股份有限公司 | A kind of curved face display panel and curved-surface display device |
| US10656473B2 (en) | 2017-09-29 | 2020-05-19 | Boe Technology Group Co., Ltd. | Curved display panel and curved display device |
| CN107632440A (en) * | 2017-10-09 | 2018-01-26 | 天马微电子股份有限公司 | Display panel and preparation method thereof and display device |
| CN108897175A (en) * | 2018-08-31 | 2018-11-27 | 合肥鑫晟光电科技有限公司 | A kind of display panel and preparation method thereof, display device |
| US10976616B2 (en) | 2018-08-31 | 2021-04-13 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Display panel, manufacturing method thereof and display device |
| CN111458939A (en) * | 2020-06-05 | 2020-07-28 | 业成科技（成都）有限公司 | Liquid crystal display panel, preparation method thereof and electronic equipment |
| CN118131523A (en) * | 2024-05-10 | 2024-06-04 | 惠科股份有限公司 | Display Panel |
| CN118131523B (en) * | 2024-05-10 | 2024-07-16 | 惠科股份有限公司 | Display panel |
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