CN103647925B - A kind of embedded parallel duplex digital image capturing system based on GigE interface - Google Patents

A kind of embedded parallel duplex digital image capturing system based on GigE interface Download PDF

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Publication number
CN103647925B
CN103647925B CN201310328995.XA CN201310328995A CN103647925B CN 103647925 B CN103647925 B CN 103647925B CN 201310328995 A CN201310328995 A CN 201310328995A CN 103647925 B CN103647925 B CN 103647925B
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image
data
gige
digital image
module
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CN103647925A (en
Inventor
李勇刚
王为
徐德刚
胡俊
朱军
阳春华
桂卫华
谢永芳
朱红求
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Central South University
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Central South University
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Abstract

The invention discloses a kind of embedded parallel duplex digital image capturing system based on GigE interface, including industry local gigabit Ethernet network, based on the video camera of GigE interface, industrial computer, digital image acquisition embedded device based on GigE interface, wherein based on the nucleus equipment that digital image acquisition embedded device is system of GigE interface.Present invention achieves the multichannel based on GigE interface embedded image to gather simultaneously, there is transfer rate height, image transmitting distortion rate is low, networking convenient, the advantage such as convenient for installation and maintenance.Devise a kind of digital image acquisition embedded device based on GigE interface, GigE camera review data in special collection LAN.Embedded system based on present invention exploitation can be widely applied to monitor based on the industrial site of machine vision.

Description

A kind of embedded parallel duplex digital image capturing system based on GigE interface
Technical field
The present invention relates to a kind of railway digital image capturing system, particularly to a kind of embedded parallel duplex digital image capturing system based on GigE interface, belong to digital image processing system.
Background technology
Machine vision, as a kind of general means of finding a view, is widely used in a lot of fields.Image capture device is data source in whole image processing system, is an indispensable ingredient.
At present great majority are all based on PC and what image pick-up card was constituted for the image acquisition monitored and control and process equipment.In this mode, image pick-up card gathers image from industrial camera, PC process image and obtain a result.PC can, according to result, realize relevant device etc. is controlled operation by other interface equipments.If carrying out multiway images detection, it is necessary to expanded images capture card on the motherboard of PC.
Owing to instruction and data is operated by PC in a serial fashion, so, can only carrying out image processing by road, cause the reduction of image processing speed, thus becoming the bottleneck that whole system gathers, and then having influence on the real-time of follow-up data operation.It addition, along with image acquisition with process the increasing of way, what the bottleneck of the disposal ability of PC should highlight more displays.
Furthermore, the copyright fee etc. of the hardware device acquisition expenses of PC and corresponding operating system and high-level language exploitation software can improve user cost greatly.Especially PC and capture card structure are when equipment is installed, and a plurality of data lines can be used to connect computer simultaneously, can cause the series of problems such as field wiring is difficult, cost is high, circuit is mixed and disorderly.
Summary of the invention
The present invention be in order to solve current PC use capture card to existing for multiway images signal processing technical problem, the present invention provides the one can from multiple digital image sensor serial acquisition image sequences;High speed digital signal processor processes every frame through the decoded view data of large-scale programmable logic array, thus obtaining required supplemental characteristic, and can by original image with process the data that obtain and be uploaded to the embedded parallel duplex digital image capturing system based on GigE interface of host computer by ethernet network.
In order to realize above-mentioned technical purpose, the technical scheme is that a kind of embedded parallel duplex digital image capturing system based on GigE interface, including:
Industry local gigabit Ethernet network, at least one stylobate in the video camera of GigE interface, at least one computer and at least one stylobate in the digital image acquisition embedded device of GigE interface;Wherein video camera, computer and image capture device are connected in same LAN, realize intercoming mutually by Ethernet;Video camera in LAN, computer, embedded collecting device sum is maximum up to 255;
View data is transferred to image acquisition embedded device by network twisted-pair cable by GigE interface by video camera in the way of packet;
Each collection embedded device includes gigabit Ethernet physical layer circuit, fpga core circuit, DSP core circuit, SDRAM, Flash, FIFO;Wherein gigabit Ethernet physical layer circuit includes general RJ45 interface and the gigabit physical chip of interconnection;Fpga core circuit is made up of a piece of FPGA and the clock of periphery thereof, filter circuit, program is developed by VerilogHDL hardware program language, and hardware logic module includes system arbitrament module, pre-processing image data module, GigE interface hardware parsing module, network data transceiver module, SDRAM controls module, Flash controls module and FIFO controls module;Network data transceiver module is connected with ethernet physical layer circuit by FPGA, image RGB data after being respectively completed reception GigE interface data bag and sending pretreatment;GigE interface hardware parsing module receives the packet that photographic head sends, and obtains the RGB data of image according to interface standard resolution data bag;The process such as the raw image data that parsing is obtained by pre-processing image data module is filtered, denoising, toning;SDRAM is controlled module and is connected with off-chip SDRAM by FPGA interface, and SDRAM realizes configuration, read-write data, and SDRAM is view data frame buffer;Flash is controlled module and is connected with off-chip Flash by FPGA interface, and Flash realizes configuration, the read-write operation such as data and erasing, and Flash is data backup storage;FIFO is controlled module and is connected with off-chip FIFO by FPGA interface, and FIFO realizes configuration, read-write data, and FIFO is data swap bridge between FPGA and DSP;Above-mentioned module is all connected with system arbitrament module, the data between system arbitrament module coordination modules exchange;DSP core circuit includes a piece of dsp processor and the clock of periphery, filter circuit composition, and operation image Processing Algorithm processes from the FPGA view data obtained;
Installation system host computer, is used for showing and store image and image parameter and configuration systematic parameter;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, the work process of system is:
1) photographic head, image acquisition embedded device and industrial computer are connected in same LAN, and system electrification initializes, and System self-test, host computer read system mode, configure systematic parameter, send operating instruction, now system work;
2) photographic head obtains view data, sends to LAN, and correspondence image gathers embedded device according to obtaining packet, through resolving and of short duration storage after pretreatment, sends until host computer, after access instruction, data and parameter is uploaded to host computer;
3) host computer shows selected camera image and image parameter in real time;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, host computer can configure systematic parameter:
1) host computer can configure the parameters such as photographic head IP address, frame per second, operational mode;
2) host computer can configure image acquisition embedded equipment I P address, sample frequency, operational mode and the parameter such as photographic head is corresponding;
3) host computer can be transferred any photographic head real time imaging and image parameter and be shown on main interface;
4) image in LAN and supplemental characteristic can be stored by host computer, and can consult historical data;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, photographic head all selects GigE interface industry photographic head;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, the industrial computer of the equal selection and deployment PCI-Express of computer;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, FPGA all selects XilinxV5 serial model No. to be XC5VSX50T chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, DSP all selects TIDavinci serial model No. to be TMS320DM642 chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, FPGA all selects XilinxV5 serial model No. to be XC5VSX50T chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, SDRAM all selects model to be MT47H64M16BT chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, Flash all selects model to be K9L8G08U1M chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, FIFO all selects model to be 72T1895 chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, ethernet PHY all selects model to be 88E1340S chip.
Said system can gather multiple imageing sensor view data simultaneously, and is placed in same LAN by imageing sensor, collecting device, host computer, it is easy to installs and safeguards;View data is transmitted based on GigE interface standard, possesses the transmission bandwidth of gigabit, can be applicable to high-definition video monitoring field.
Below in conjunction with accompanying drawing, the invention will be further described.
Accompanying drawing explanation
Fig. 1 is the system application connection figure topological diagram of the present invention;
Fig. 2 is image acquisition embedded device hardware structure figure in the present invention;
Fig. 3 be the present invention image acquisition embedded device in fpga logic structure chart;
Fig. 4 is present system workflow;
Fig. 5 is the data flow diagram of present system;
Detailed description of the invention
The present invention includes industry local gigabit Ethernet network, at least one stylobate in the video camera of GigE interface, at least one computer and at least one stylobate in the digital image acquisition embedded device of GigE interface;Wherein video camera, computer and image capture device are connected in same LAN, realize intercoming mutually by Ethernet;Video camera in LAN, computer, embedded collecting device sum is maximum up to 255;
View data is transferred to image acquisition embedded device by network twisted-pair cable by GigE interface by video camera in the way of packet;
Each collection embedded device includes gigabit Ethernet physical layer circuit, fpga core circuit, DSP core circuit, SDRAM, Flash, FIFO;Wherein gigabit Ethernet physical layer circuit includes general RJ45 interface and the gigabit physical chip of interconnection;Fpga core circuit is made up of a piece of FPGA and the clock of periphery thereof, filter circuit, program is developed by VerilogHDL hardware program language, and hardware logic module includes system arbitrament module, pre-processing image data module, GigE interface hardware parsing module, network data transceiver module, SDRAM controls module, Flash controls module and FIFO controls module;Network data transceiver module is connected with ethernet physical layer circuit by FPGA, image RGB data after being respectively completed reception GigE interface data bag and sending pretreatment;GigE interface hardware parsing module receives the packet that photographic head sends, and obtains the RGB data of image according to interface standard resolution data bag;The process such as the raw image data that parsing is obtained by pre-processing image data module is filtered, denoising, toning;SDRAM is controlled module and is connected with off-chip SDRAM by FPGA interface, and SDRAM realizes configuration, read-write data, and SDRAM is view data frame buffer;Flash is controlled module and is connected with off-chip Flash by FPGA interface, and Flash realizes configuration, the read-write operation such as data and erasing, and Flash is data backup storage;FIFO is controlled module and is connected with off-chip FIFO by FPGA interface, and FIFO realizes configuration, read-write data, and FIFO is data swap bridge between FPGA and DSP;Above-mentioned module is all connected with system arbitrament module, the data between system arbitrament module coordination modules exchange;DSP core circuit includes a piece of dsp processor and the clock of periphery, filter circuit composition, and operation image Processing Algorithm processes from the FPGA view data obtained;
System host computer is used for showing and store image and image parameter and configuration systematic parameter;
Referring to Fig. 4, the work process of the system of the present invention is:
1) photographic head, image acquisition embedded device and industrial computer are connected in same LAN, and system electrification initializes, and System self-test, host computer read system mode, configure systematic parameter, send operating instruction, now system work;
2) photographic head obtains view data, sends to LAN, and correspondence image gathers embedded device according to obtaining packet, through resolving and of short duration storage after pretreatment, sends until host computer, after access instruction, data and parameter is uploaded to host computer;
3) host computer shows selected camera image and image parameter in real time;
The host computer of the present invention can configure systematic parameter:
1) host computer can configure the parameters such as photographic head IP address, frame per second, operational mode;
2) host computer can configure image acquisition embedded equipment I P address, sample frequency, operational mode and the parameter such as photographic head is corresponding;
3) host computer can be transferred any photographic head real time imaging and image parameter and be shown on main interface;
4) image in LAN and supplemental characteristic can be stored by host computer, and can consult historical data;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, photographic head all selects GigE interface industry photographic head;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, the industrial computer of the equal selection and deployment PCI-Express of computer;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, FPGA all selects XilinxV5 serial model No. to be XC5VSX50T chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, DSP all selects TIDavinci serial model No. to be TMS320DM642 chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, FPGA all selects XilinxV5 serial model No. to be XC5VSX50T chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, SDRAM all selects model to be MT47H64M16BT chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, Flash all selects model to be K9L8G08U1M chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, FIFO all selects model to be 72T1895 chip;
A kind of embedded parallel duplex digital image capturing system based on GigE interface of the present invention, in built-in image collection equipment, ethernet PHY all selects model to be 88E1340S chip.
Accompanying drawing 1 is the topological structure that system is installed when applying at the scene.In FIG, system all devices is connected on the gigabit Ethernet of locality, including multiple PC host computers for monitoring, multiple imageing sensor, multiple embedded acquisition system.In this LAN, each equipment has unique ip address, and the exchange of data is all based on Ethernet.The view data bag collected is transmitted to embedded acquisition system by GigE photographic head, after treatment artwork data and result is uploaded to PC host computer, and artwork and result are shown on screen by PC host computer.Simultaneously PC host computer has and arranges interface, and embedded acquisition system receives host computer instruction and the input signal in conjunction with self result to image and signal acquisition circuit sends control instruction, and GigE photographic head receives control instruction and corresponding adjustment is made in response.
Accompanying drawing 2 is based on the embedded parallel duplex digital image capturing system hardware Organization Chart of GigEVISION coffret, system connects LAN by RJ45 interface, acquisition GigE network packet then passes through gigabit Ethernet PHY and carries out the signal conversion of hardware view, then packet transmits to FPGA, packet is resolved with reference to GigE agreement and obtains transparent pixel RGB data by FPGA, transmits to FPGA after carrying out simple process in FPGA.Then DSP fetches data from FPGA, in DSP, run relevant image processing algorithm obtain corresponding result, same puts in FPGA, and FPGA takes out the result data in FPGA, artwork data corresponding for the combination of this processing result image was packed into network interface and sends to PC host computer.Simultaneity factor has from backup functionality, and the information such as each processing result image and corresponding camera numbers, time can be stored in NANDFlash by FPGA, and can regularly clear up renewal.When system detects that PC host computer is not connected with, the information such as processing result image and corresponding camera numbers, time can be stored in NANDFlash by system.
Power-supply system is powered, D.C. regulated power supply is system power supply.

Claims (10)

1. the embedded parallel duplex digital image capturing system based on GigE interface, it is characterised in that including:
Industry local gigabit Ethernet network, at least one stylobate in the video camera of GigE interface, at least one computer and at least one stylobate in the digital image acquisition embedded device of GigE interface;Wherein video camera, computer and image capture device are connected in industry local gigabit Ethernet network, realize intercoming mutually by Ethernet;In LAN, video camera, computer, embedded collecting device sum are 255 to the maximum;
View data is transferred to image acquisition embedded device by network twisted-pair cable by GigE interface by video camera in the way of packet;
Each collection embedded device includes gigabit Ethernet physical layer circuit, fpga core circuit, DSP core circuit, SDRAM, Flash, FIFO;Wherein gigabit Ethernet physical layer circuit includes general RJ45 interface and the gigabit physical chip of interconnection;Fpga core circuit is made up of a piece of FPGA and the peripheral clock circuit being connected with FPGA and filter circuit, program is developed by VerilogHDL hardware program language, and hardware logic module includes system arbitrament module and controls module, Flash control module and FIFO control module respectively with the pre-processing image data module of system arbitrament module communication connection, GigE interface hardware parsing module, network data transceiver module, SDRAM;Network data transceiver module is connected with ethernet physical layer circuit by FPGA, image RGB data after being respectively completed reception GigE interface data bag and sending pretreatment;GigE interface hardware parsing module receives the packet that photographic head sends, and obtains the RGB data of image according to interface standard resolution data bag;Pre-processing image data module carries out pretreatment to resolving the raw image data obtained;SDRAM is controlled module and is connected with off-chip SDRAM by FPGA interface, and SDRAM realizes configuration, read-write data, and SDRAM is view data frame buffer;Flash is controlled module and is connected with off-chip Flash by FPGA interface, and Flash realizes configuration, read-write data and erasing operation, and Flash is data backup storage;FIFO is controlled module and is connected with off-chip FIFO by FPGA interface, and FIFO realizes configuration, read-write data, and FIFO is data swap bridge between FPGA and DSP;Data exchange between each hardware logic module of system arbitrament module coordination;DSP core circuit include a piece of dsp processor and peripheral is connected with dsp processor clock, filter circuit, the process of operation image Processing Algorithm is from the view data of FPGA acquisition;
Computer, as system host computer, is used for showing and store image and image parameter and configuration systematic parameter.
2. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that the work process of system is:
1) photographic head, image acquisition embedded device and industrial computer are connected in same LAN, and system electrification initializes, and System self-test, host computer read system mode, configure systematic parameter, send operating instruction, system starts;
2) photographic head obtains view data, sends to LAN, and correspondence image gathers embedded device according to obtaining packet, through resolving and of short duration storage after pretreatment, sends until host computer, after access instruction, data and parameter is uploaded to host computer;
3) host computer shows selected camera image and image parameter in real time.
3. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that the industrial computer of the equal selection and deployment PCI-Express of computer.
4. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, FPGA all selects XilinxV5 serial model No. to be XC5VSX50T chip.
5. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, DSP all selects TIDavinci serial model No. to be TMS320DM642 chip.
6. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, FPGA all selects XilinxV5 serial model No. to be XC5VSX50T chip.
7. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, SDRAM all selects model to be MT47H64M16BT chip.
8. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, Flash all selects model to be K9L8G08U1M chip.
9. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, FIFO all selects model to be 72T1895 chip.
10. a kind of embedded parallel duplex digital image capturing system based on GigE interface according to claim 1, it is characterised in that in built-in image collection equipment, ethernet PHY all selects model to be 88E1340S chip.
CN201310328995.XA 2013-07-31 2013-07-31 A kind of embedded parallel duplex digital image capturing system based on GigE interface Expired - Fee Related CN103647925B (en)

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