CN103647028B - Array base palte and preparation method thereof, display device - Google Patents
Array base palte and preparation method thereof, display device Download PDFInfo
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- CN103647028B CN103647028B CN201310706776.0A CN201310706776A CN103647028B CN 103647028 B CN103647028 B CN 103647028B CN 201310706776 A CN201310706776 A CN 201310706776A CN 103647028 B CN103647028 B CN 103647028B
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- 238000002360 preparation method Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000009413 insulation Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000011368 organic material Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 27
- 239000010408 film Substances 0.000 claims description 23
- 239000010409 thin film Substances 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 229910000765 intermetallic Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 239000007772 electrode material Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims 3
- 230000005611 electricity Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
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- 238000001704 evaporation Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a kind of array substrate manufacturing method, comprising: on substrate, form the figure including data wire, source electrode and drain electrode；Form the figure including active layer；Form the figure including gate insulation layer, and expose the region that described drain electrode is connected with anode to be formed；Form the figure including grid line, grid and anode；Form the figure including pixel defining layer, organic material layer and transparent cathode.Also disclose a kind of array base palte and display device.The method of the present invention decreases the number of times of mask, thus saves fabrication processing and cost of manufacture.
Description
Technical field
The present invention relates to Display Technique field, particularly to a kind of array base palte and preparation method thereof, display device.
Background technology
The AMOLED display device of traditional top emitting is as shown in Figure 1, comprising: form first grid on substrate 1 the 2nd,
Second grid 2 ＇ and grid line (not shown), be formed at the gate insulation layer 3 on first grid the 2nd, second grid 2 ＇ and grid line,
The first active layer 4 and the second active layer 4 ＇ being formed on gate insulation layer 3, is formed at the first active layer 4 and the second active layer 4 ＇
On etching barrier layer 5, the first source-drain layer 6(being formed on etching barrier layer 5 include the first source electrode and first drain electrode) and
Second source-drain layer 6 ＇ (include the second source electrode and second drain electrode), be formed on the first source-drain layer 6 and the second source-drain layer 6 ＇ is blunt
Change layer 7.Wherein, first grid the 2nd, gate insulation layer the 3rd, the first active layer the 4th, etching barrier layer 5 and the first source-drain layer 6 formation switch are thin
Film transistor (switch TFT), second grid 2 ＇, gate insulation layer the 3rd, the second active layer 4 ＇, etching barrier layer 5 and the second source-drain layer 6 ＇
Formed and drive thin film transistor (TFT) (driving TFT).
Passivation layer 7 is formed on the first source-drain layer 6 and the second source-drain layer 6 ＇, it is also formed with for anode 8(impermeable
Bright) connect the via of the second source-drain layer 6 ＇, anode 8 is formed on passivation layer 7.It is also formed with pixel defining layer 11 on anode 8
And organic luminous layer 9, form transparent cathode 10 on organic luminous layer 9.
Wherein, active layer is typically oxide semiconductor material, and the TFT i.e. being formed is OxideTFT, therefore also needs to volume
One layer of outer etching barrier layer 5 in case when etching source-drain layer oxide semiconductor material be damaged, affect the performance of TFT.
Therefore, make above-mentioned AMOLED display device and typically require 7 masking process (mask) formation (mistakes on grid, gate insulation layer
Hole, active layer, the via on etching barrier layer, source-drain layer, the via on passivation layer, each mask of pixel defining layer), technique
Complexity, cost is high.
Content of the invention
(1) to solve the technical problem that
The technical problem to be solved in the present invention is: how to reduce manufacture craft and the cost of display device.
(2) technical scheme
For solving above-mentioned technical problem, the invention provides a kind of array substrate manufacturing method, comprising:
Substrate forms the figure including data wire, source electrode and drain electrode；
Form the figure including active layer；
Form the figure including gate insulation layer, and expose the region that described drain electrode is connected with anode to be formed；
Form the figure including grid line, grid and anode；
Form the figure including pixel defining layer, organic material layer and transparent cathode.
Wherein, the step of the figure that described formation includes active layer specifically includes:
The substrate being formed with data wire, source electrode and drain electrode forms photoresist；
It is exposed development to described photoresist, remove the photoresist of the graphics field of corresponding described active layer；
Sequentially forming active layer material film, in the graphics field of corresponding described active layer, active layer material film connects
Described source electrode and drain electrode；
Peel off remaining photoresist and the active layer material film being formed on described residue photoresist, have described in being formed
The figure of active layer.
Wherein, described active layer material film is oxide semiconductor thin-film.
Wherein, described formation includes that the step of the figure of grid line, grid and anode specifically includes:
The substrate be formed with gate insulation layer forms gate electrode material film；
Formed the figure including grid line, grid and anode by patterning processes, described anode connects described drain electrode.
Wherein, the thickness of described gate electrode material film is:
Wherein, grid material is the metallic compound of metal or the conduction with light-reflecting property.
Wherein, the described metal with light-reflecting property includes: Ag, Au, Al, Ti or Cr；The metallic compound of described conduction
Including: AlX, MoX or CuX.
Present invention also offers a kind of array base palte, including the grid line being formed on substrate and data wire, and by described
Multiple pixel cells that grid line and data wire limit, each described pixel cell is divided into TFT regions and luminous zone
Territory；
Described TFT regions is formed with at least one thin film transistor (TFT), and described thin film transistor (TFT) includes sequentially forming
Source-drain electrode layer on described substrate, active layer, gate insulation layer and grid；
Surface at described light-emitting zone is formed with anode, and described anode connects the drain electrode of described source-drain electrode layer,
Described anode and grid are identical material and are formed in one-time process, are sequentially formed with organic luminous layer and the moon above anode
Pole, and organic luminous layer and the negative electrode of described anode and anode corresponding region be collectively forming Organic Light Emitting Diode；
It is also formed with pixel defining layer on described thin film transistor (TFT).
Wherein, described organic luminous layer and negative electrode cover whole substrate regions, and it is brilliant that described pixel defining layer is formed at film
Between body pipe and described organic luminous layer.
Wherein, described pixel defining layer also covers described grid line and data wire corresponding region.
Wherein, the material of described grid and anode is the metallic compound of metal or the conduction with light-reflecting property.
Wherein, the described metal with light-reflecting property includes: Ag, Au, Al, Ti or Cr；The metallic compound of described conduction
Including: AlX, MoX or CuX.
Wherein, the thickness of described grid and anode is:
Present invention also offers a kind of display device, including the array base palte described in any of the above-described item.
(3) beneficial effect
The preparation method using the array base palte of the present invention decreases the number of times of mask, thus saves fabrication processing
And cost of manufacture.
Brief description
The array base-plate structure schematic diagram of the OLED display of the existing top emitting of Fig. 1；
Fig. 2 be the present invention array substrate manufacturing method on substrate formed source-drain electrode layer structural representation；
Fig. 3 is the structural representation forming photoetching offset plate figure on the basis of Fig. 2；
Fig. 4 is the structural representation being formed with active layer and etching barrier layer materials film on the basis of Fig. 3；
Fig. 5 is the structural representation being formed with active layer and etch stopper layer pattern on the basis of Fig. 4；
Fig. 6 is the structural representation forming gate insulation layer on the basis of Fig. 5；
Fig. 7 is the structural representation forming via on the basis of Fig. 6 on gate insulation layer；
Fig. 8 is the structural representation forming gate electrode material film on the basis of Fig. 7；
Fig. 9 is the structural representation forming grid and anode on the basis of Fig. 8；
Figure 10 is the structural representation forming pixel defining layer on the basis of Fig. 9；
Figure 11 is the structural representation of the array base palte that the method for the present invention ultimately forms.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, the detailed description of the invention of the present invention is described in further detail.Hereinafter implement
Example is used for illustrating the present invention, but is not limited to the scope of the present invention.
The array substrate manufacturing method of the embodiment of the present invention comprises the steps:
Step one, at substrate 101(transparency carrier, such as glass substrate or quartz base plate) above form data wire, source-drain electrode
The figure of layer.This step can be specifically on the substrate 101 formed (can be sputtering, evaporation or chemical gaseous phase deposition CVD side
Formula is formed) source and drain metallic film, then (generally include photoresist coating, exposure, development, etching, photoresist by patterning processes
The techniques such as stripping) form source electrode 102a and the figure of drain electrode 102b, as shown in Figure 2.
Step 2, is formed with the figure of active layer on the substrate of Fig. 1.Specifically include:
The substrate 101 of Fig. 1 applies photoresist, as it is shown on figure 3, be exposed development to photoresist, removes active layer
With the photoresist of etch stopper layer region A, remain photoresist 103.
As shown in Figure 4, active layer material film 104 ＇ is sequentially formed, except the active layer material film of active layer region A
Outside 104 ＇ cover on the substrate 101, active layer material film 104 ＇ in other regions all covers on photoresist 103.Fig. 4
In, one layer of etching barrier layer materials film 105 ＇ can also be defined at active layer material film 104 ＇.
It as it is shown in figure 5, peel off residue photoresist 103, is formed with the figure of active layer 104.In the present embodiment, active layer material
For oxide semiconductor, such as IGZO.(etching barrier layer 105 can have can also to form the figure of etching barrier layer 105 in Fig. 5
Nothing).
Step 3, forms the figure including gate insulation layer, and exposes the region that drain electrode is connected with anode to be formed.This step
Suddenly specifically include:
As shown in Figure 6, the substrate after step 2 forms gate insulation layer 106.
As it is shown in fig. 7, in the present embodiment, the region shape that is connected with anode to be formed at drain electrode 102b by patterning processes
Become the via 107 through gate insulation layer 106.Certainly can also by patterning processes direct etching fall anode region and drain electrode with
The gate insulation layer film in the region that anode to be formed connects, to ultimately form gate insulation layer 106.
Step 4, forms the figure including grid line, grid and anode.This step specifically includes:
As shown in Figure 8, the substrate after step 3 forms gate electrode material film 108.
As it is shown in figure 9, become the figure of grid 109 in area of grid C-shaped by patterning processes, anode region D-shaped becomes anode
The figure of 110.Grid 109 i.e. defines top gate structure thin film transistor (TFT) after being formed (includes source electrode 102a, drain electrode 102b, has
Active layer the 104th, etching barrier layer the 105th, gate insulation layer 106 and grid 109).
In the present embodiment, the light that sends due to anode 110 luminous organic material to be reflected, therefore, grid 109 and anode 110
Material be the metallic compound of metal or the conduction with light-reflecting property, can be Ag, Au, AlX, MoX, CuX, Al, Ti or Cr,
Wherein AlX, MoX or CuX are the metallic compounds of conduction.The thickness of grid 109 and anode 110 is:
Step 5, forms the figure including pixel defining layer, organic material layer and transparent cathode.Specifically include:
As shown in Figure 10, the region E(i.e. TFT regions on the substrate after step 4) pass through patterning processes
Forming pixel defining layer 111, the region F not forming pixel defining layer 111 is then pixel region, the i.e. luminous zone of organic luminous layer
Territory, usual pixel defining layer 111 is mainly used in blocking the corresponding region of TFT, grid line and data wire, to avoid in thin film transistor (TFT)
The active layer 104 of oxide semiconductor by illumination, thus ensure the performance of thin film transistor (TFT).
In the drawings 10 on the basis of sequentially form organic luminescent layer 112 and negative electrode 113, as shown in figure 11, region F is corresponding
Anode the 110th, organic luminous layer 112 and negative electrode 113 are collectively forming Organic Light Emitting Diode, thus form the battle array of OLED display
Row substrate.
The array substrate manufacturing method of the present embodiment has respectively used an i.e. composition work of mask(in step one to step 5
Skill), totally 5 mask.Relative to 7 mask techniques of existing array base palte, decrease mask number, save technological process
And cost.
The embodiment of the present invention additionally provide said method make array base palte, including the grid line being formed on substrate and
Data wire, and the multiple pixel cells being limited by described grid line and data wire.Each described pixel cell as shown in figure 11, is drawn
It is divided into TFT regions E and light-emitting zone F；
TFT regions E is formed with at least one thin film transistor (TFT), and described thin film transistor (TFT) includes being sequentially formed at
Source-drain electrode layer (including source electrode 102a and drain electrode 102b) on described substrate 101, active layer the 104th, etching barrier layer 105
(also can there is no etching barrier layer 105), gate insulation layer 106 and grid 109.
Substrate 101 at light-emitting zone F is formed above anode 110, and anode 110 connects the drain electrode of described source-drain electrode layer
102b.Anode 110 and grid 109 are identical material and are formed in one-time process.It is sequentially formed with organic light emission above anode
Layer 112 and negative electrode 113, and organic luminous layer 112 and the negative electrode 113 of anode 110 and anode 110 corresponding region (i.e. region F) are common
With formation Organic Light Emitting Diode.This thin film transistor (TFT) is used for driving Organic Light Emitting Diode.
It is also formed with pixel defining layer 111 on described thin film transistor (TFT).Due to organic luminous layer 112 and the moon when making
Pole 113 covers the region of whole substrate 101, in order to avoid the organic luminous layer 112 of thin film transistor (TFT) corresponding region E is luminous and sends out
Light that light region F sends and the performance that has influence on thin film transistor (TFT), pixel defining layer 111 is formed at thin film transistor (TFT) and organic
Between photosphere 112.Pixel defining layer 111 also covers grid line and data wire corresponding region.
The array base palte of the present embodiment is the array base palte of top emitting OLED display, therefore grid 109 and anode 110
Material is the metallic compound of metal or the conduction with light-reflecting property, such as: Ag, Au, AlX, MoX, CuX, Al, Ti or Cr etc.,
Wherein AlX, MoX or CuX are the metallic compounds of conduction.The thickness of grid 109 and anode 110 is:
Present invention also offers a kind of display device, including above-mentioned array base palte.This display device can be: OLED face
Plate, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator etc. are any has display function
Product or parts.
Embodiment of above is merely to illustrate the present invention, and not limitation of the present invention, common about technical field
Technical staff, without departing from the spirit and scope of the present invention, can also make a variety of changes and modification, therefore own
Equivalent technical scheme falls within scope of the invention, and the scope of patent protection of the present invention should be defined by the claims.
Claims (13)
1. an array substrate manufacturing method, it is characterised in that include:
Substrate forms the figure including data wire, source electrode and drain electrode；
Form the figure including active layer；
Form the figure including gate insulation layer, and expose the region that described drain electrode is connected with anode to be formed；
Form the figure including grid line, grid and anode；Described anode and grid are identical material and are formed in one-time process；
Form the figure including pixel defining layer, organic material layer and transparent cathode；
Described formation includes that the step of the figure of grid line, grid and anode specifically includes:
The substrate be formed with gate insulation layer forms gate electrode material film；
Formed the figure including grid line, grid and anode by patterning processes, described anode connects described drain electrode.
2. array substrate manufacturing method as claimed in claim 1, it is characterised in that described formation includes the figure of active layer
Step specifically includes:
The substrate being formed with data wire, source electrode and drain electrode forms photoresist；
It is exposed development to described photoresist, remove the photoresist of the graphics field of corresponding described active layer；
Sequentially forming active layer material film, in the graphics field of corresponding described active layer, active layer material film connects described
Source electrode and drain electrode；
Peel off remaining photoresist and the active layer material film being formed on described residue photoresist, to form described active layer
Figure.
3. array substrate manufacturing method as claimed in claim 2, it is characterised in that described active layer material film is oxide
Semiconductive thin film.
4. array substrate manufacturing method as claimed in claim 1, it is characterised in that the thickness of described gate electrode material film is:
5. array substrate manufacturing method as claimed in claim 1, it is characterised in that grid material is the gold with light-reflecting property
The metallic compound belonging to or conducting electricity.
6. array substrate manufacturing method as claimed in claim 5, it is characterised in that the described metal bag with light-reflecting property
Include: Ag, Au, Al, Ti or Cr；The metallic compound of described conduction includes: AlX, MoX or CuX.
7. an array base palte, including the grid line being formed on substrate and data wire, and limited by described grid line and data wire
Multiple pixel cells, it is characterised in that each described pixel cell is divided into TFT regions and light-emitting zone；
Described TFT regions is formed with at least one thin film transistor (TFT), and described thin film transistor (TFT) includes being sequentially formed at institute
State the source-drain electrode layer on substrate, active layer, gate insulation layer and grid；
Surface at described light-emitting zone is formed with anode, and described anode connects the drain electrode of described source-drain electrode layer, described
Anode and grid are identical material and are formed in one-time process, are sequentially formed with organic luminous layer and negative electrode above anode, and
The organic luminous layer of described anode and anode corresponding region and negative electrode are collectively forming Organic Light Emitting Diode；
It is also formed with pixel defining layer on described thin film transistor (TFT)；
Wherein, described anode is by being connected through the via of described gate insulation layer with described drain electrode.
8. array base palte as claimed in claim 7, it is characterised in that described organic luminous layer and negative electrode cover whole substrate zone
Territory, described pixel defining layer is formed between thin film transistor (TFT) and described organic luminous layer.
9. array base palte as claimed in claim 8, it is characterised in that described pixel defining layer also covers described grid line and data
Line corresponding region.
10. the array base palte as according to any one of claim 7～9, it is characterised in that the material of described grid and anode is
There is the metal of light-reflecting property or the metallic compound of conduction.
11. array base paltes as claimed in claim 10, it is characterised in that the described metal with light-reflecting property includes: Ag,
Au, Al, Ti or Cr；The metallic compound of described conduction includes: AlX, MoX or CuX.
12. array base paltes as according to any one of claim 7～9, it is characterised in that the thickness of described grid and anode
For:
13. 1 kinds of display devices, it is characterised in that include the array base palte as according to any one of claim 7～12.
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| CN106410030A (en) * | 2016-11-08 | 2017-02-15 | 深圳市华星光电技术有限公司 | Manufacturing method of organic thin-film transistor |
| CN108231824B (en) * | 2016-12-16 | 2024-04-23 | 京东方科技集团股份有限公司 | OLED display panel and preparation method thereof |
| CN109407893B (en) * | 2018-12-17 | 2021-01-01 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and manufacturing method thereof |
| US11188178B2 (en) | 2018-12-17 | 2021-11-30 | Wuhan China Star Optofi Fctronics Semiconductor Display Technology Co., Ltd. | Touch display panel, manufacturing method thereof, and touch display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937272A (en) * | 1997-06-06 | 1999-08-10 | Eastman Kodak Company | Patterned organic layers in a full-color organic electroluminescent display array on a thin film transistor array substrate |
| CN101075634A (en) * | 2006-05-17 | 2007-11-21 | Lg.菲利浦Lcd株式会社 | Light emitting device and method of manufacturing the same |
| CN101958339A (en) * | 2009-07-15 | 2011-01-26 | 三星移动显示器株式会社 | Organic light-emitting display device and manufacture method thereof |
| CN102201451A (en) * | 2011-06-02 | 2011-09-28 | 上海大学 | Oxide thin film transistor (TFT) with buffer layer top grid structure |
| CN102651403A (en) * | 2012-04-16 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method of array substrate and display panel |
| EP1405356B1 (en) * | 2001-07-09 | 2013-07-31 | Plastic Logic Limited | Solution influenced alignment |
| CN203674211U (en) * | 2013-12-19 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4337171B2 (en) * | 1999-06-14 | 2009-09-30 | ソニー株式会社 | Display device |
| CN100533746C (en) * | 2004-08-03 | 2009-08-26 | 株式会社半导体能源研究所 | Display device, manufacturing method thereof, and television set |
-
2013
- 2013-12-19 CN CN201310706776.0A patent/CN103647028B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937272A (en) * | 1997-06-06 | 1999-08-10 | Eastman Kodak Company | Patterned organic layers in a full-color organic electroluminescent display array on a thin film transistor array substrate |
| EP1405356B1 (en) * | 2001-07-09 | 2013-07-31 | Plastic Logic Limited | Solution influenced alignment |
| CN101075634A (en) * | 2006-05-17 | 2007-11-21 | Lg.菲利浦Lcd株式会社 | Light emitting device and method of manufacturing the same |
| CN101958339A (en) * | 2009-07-15 | 2011-01-26 | 三星移动显示器株式会社 | Organic light-emitting display device and manufacture method thereof |
| CN102201451A (en) * | 2011-06-02 | 2011-09-28 | 上海大学 | Oxide thin film transistor (TFT) with buffer layer top grid structure |
| CN102651403A (en) * | 2012-04-16 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method of array substrate and display panel |
| CN203674211U (en) * | 2013-12-19 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate and display device |
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