CN203674211U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203674211U CN203674211U CN201320844965.XU CN201320844965U CN203674211U CN 203674211 U CN203674211 U CN 203674211U CN 201320844965 U CN201320844965 U CN 201320844965U CN 203674211 U CN203674211 U CN 203674211U
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- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000000873 masking effect Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 19
- 230000004888 barrier function Effects 0.000 description 16
- 239000010408 film Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000000203 mixture Substances 0.000 description 6
- 229910000765 intermetallic Inorganic materials 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- -1 as shown in Figure 4 Polymers 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Images
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- Thin Film Transistor (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The utility model discloses an array substrate, which comprises grid lines, data lines and a plurality of pixel units, wherein the grid lines and the data lines are formed on the substrate, the plurality of pixel units are defined by the grid lines and the data lines, and each of the pixel units is divided into a thin-film transistor region and a light emitting region; the thin-film transistor region is provided with at least one thin-film transistor, the thin-film transistor comprises a source and drain electrode layer, an active layer, a gate insulation layer and a gate electrode layer which are formed on the substrate sequentially; an anode is formed on the substrate of the light emitting region, the anode is connected with a drain electrode of the source and drain electrode layer, the anode and the gate electrode are of the same material and formed in one time processing, an organic light emitting layer and a cathode are sequentially formed above the anode, and the anode, the organic light emitting layer of the region corresponding to the anode and the cathode form an organic light emitting diode together; and the thin-film transistor is further provided with a pixel defining layer. The method disclosed by the utility model reduces the number of masking times, thereby saving the manufacturing technological process and the manufacturing cost.
Description
Technical field
The utility model relates to Display Technique field, particularly a kind of array base palte and preparation method thereof, display unit.
Background technology
The AMOLED display unit of traditional top transmitting as shown in Figure 1, comprise: be formed on the first grid 2 on substrate 1, second grid 2 ＇ and grid line (not shown), be formed on first grid 2, gate insulation layer 3 on second grid 2 ＇ and grid line, be formed on the first active layer 4 and the second active layer 4 ＇ on gate insulation layer 3, be formed on the etching barrier layer 5 on the first active layer 4 and the second active layer 4 ＇, the the first source-drain layer 6(being formed on etching barrier layer 5 comprises the first source electrode and the first drain electrode) and the second source-drain layer 6 ＇ (comprising the second source electrode and the second drain electrode), be formed on the passivation layer 7 on the first source-drain layer 6 and the second source-drain layer 6 ＇.Wherein, first grid 2, gate insulation layer 3, the first active layer 4, etching barrier layer 5 and the first source-drain layer 6 form switching thin-film transistor (switching TFT), and second grid 2 ＇, gate insulation layer 3, the second active layer 4 ＇, etching barrier layer 5 and the second source-drain layer 6 ＇ form and drive thin-film transistor (drive TFT).
Wherein, active layer is oxide semiconductor material normally, form TFT be Oxide TFT, therefore also need extra one deck etching barrier layer 5 in case in the time of etching source-drain layer oxide semiconductor material be damaged, affect the performance of TFT.Therefore, making above-mentioned AMOLED display unit conventionally needs 7 masking process (mask) to form (the each mask of via hole, pixel defining layer on via hole on via hole on grid, gate insulation layer, active layer, etching barrier layer, source-drain layer, passivation layer), complex process, cost is high.
Utility model content
(1) technical problem that will solve
The technical problems to be solved in the utility model is: the manufacture craft and the cost that how to reduce display unit.
(2) technical scheme
For solving the problems of the technologies described above, the utility model provides a kind of array base palte, comprises the grid line and the data wire that are formed on substrate, and the multiple pixel cells that limited by described grid line and data wire, it is characterized in that, each described pixel cell is divided into TFT regions and light-emitting zone;
Described TFT regions is formed with at least one thin-film transistor, and described thin-film transistor comprises the source-drain electrode layer, active layer, gate insulation layer and the grid that are formed on successively on described substrate;
Above the substrate of described light-emitting zone, be formed with anode, the drain electrode of source-drain electrode layer described in described anodic bonding, described anode and grid are same material and form in one-time process, anode top is formed with organic luminous layer and negative electrode successively, and the organic luminous layer of described anode and anode corresponding region and negative electrode are formed with OLED jointly;
On described thin-film transistor, be also formed with pixel defining layer.
Wherein, described organic luminous layer and negative electrode cover whole substrate regions, and described pixel defining layer is formed between thin-film transistor and described organic luminous layer.
Wherein, described pixel defining layer also covers described grid line and data wire corresponding region.
Wherein, the material of described active layer is oxide semiconductor.
Wherein, the material of described grid and anode is to have the metal of reflective characteristic or the metallic compound of conduction.
The metal wherein, with reflective characteristic comprises: Ag, Au, Al, Ti or Cr; The metallic compound of described conduction comprises: AlX, MoX or CuX.
Wherein, the thickness of described grid and anode is:
The utility model also provides a kind of display unit, comprises the array base palte described in above-mentioned any one.
(3) beneficial effect
Array base palte of the present utility model adopts top gate structure, and source-drain electrode is positioned at active layer and grid below (can not need etching barrier layer), makes to have reduced while making this array base palte the number of times of mask, thereby has saved fabrication processing and cost of manufacture.
Accompanying drawing explanation
The array base-plate structure schematic diagram of the OLED display unit of Fig. 1 existing top transmitting;
Fig. 2 is the structural representation of the final array base palte forming of method of the present utility model;
Fig. 3 is the structural representation that forms source-drain electrode layer in array substrate manufacturing method of the present utility model on substrate;
Fig. 4 is the structural representation that forms photoetching offset plate figure on the basis of Fig. 3;
Fig. 5 is the structural representation that forms active layer and etching barrier layer material film on the basis of Fig. 4;
Fig. 6 is the structural representation that forms active layer and etching barrier layer figure on the basis of Fig. 5;
Fig. 7 is the structural representation that forms gate insulation layer on the basis of Fig. 6;
Fig. 8 is the structural representation that forms via hole on the basis of Fig. 7 on gate insulation layer;
Fig. 9 is the structural representation that forms gate electrode material film on the basis of Fig. 8;
Figure 10 is the structural representation that forms grid and anode on the basis of Fig. 9;
Figure 11 is the structural representation that forms pixel defining layer on the basis of Figure 10.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for illustrating the utility model, but are not used for limiting scope of the present utility model.
The array base palte that the utility model provides, comprises the grid line and the data wire that are formed on substrate, and the multiple pixel cells that limited by described grid line and data wire.Each described pixel cell as shown in Figure 2, is divided into TFT regions E and light-emitting zone F;
TFT regions E is formed with at least one thin-film transistor, and described thin-film transistor comprises that the source-drain electrode layer that is formed on successively on substrate 101 (comprising source electrode 102a and drain electrode 102b), active layer 104, etching barrier layer 105(can not have etching barrier layer 105 yet), gate insulation layer 106 and grid 109.The material of active layer 104 is oxide semiconductor, as IGZO.
Above the substrate 101 of light-emitting zone F, be formed with anode 110, anode 110 connects the drain electrode 102b of described source-drain electrode layer.Anode 110 is same material with grid 109 and forms in one-time process.Anode top is formed with organic luminous layer 112 and negative electrode 113 successively, and organic luminous layer 112 and the negative electrode 113 of anode 110 and anode 110 corresponding regions (being region F) are formed with OLED jointly.This thin-film transistor is used for driving Organic Light Emitting Diode.
On described thin-film transistor, be also formed with pixel defining layer 111.Because organic luminous layer 112 and negative electrode 113 in the time making cover the region of whole substrate 101, for fear of the light that organic luminous layer 112 is luminous and light-emitting zone F sends of thin-film transistor corresponding region E and have influence on the performance of thin-film transistor, pixel defining layer 111 is formed between thin-film transistor and organic luminous layer 112.Pixel defining layer 111 also covers grid line and data wire corresponding region.
The array base palte of the present embodiment is the array base palte of top transmitting OLED display unit, therefore the material of grid 109 and anode 110 is to have the metal of reflective characteristic or the metallic compound of conduction, as: Ag, Au, AlX, MoX, CuX, Al, Ti or Cr etc., wherein AlX, MoX or CuX are the metallic compounds of conduction.The thickness of grid 109 and anode 110 is:
Also provide a kind of making above-mentioned array substrate manufacturing method, comprised the steps:
Step 1, at substrate 101(transparency carrier, as glass substrate or quartz base plate) the upper figure that forms data wire, source-drain electrode layer.This step can be specifically on substrate 101, to form (mode that can be sputter, evaporation or chemical vapour deposition (CVD) CVD forms) source to leak metallic film, then form the figure of source electrode 102a and drain electrode 102b by composition technique (generally including the techniques such as photoresist coating, exposure, development, etching, photoresist lift off), as shown in Figure 3.
On the substrate 101 of Fig. 3, apply photoresist, as shown in Figure 4, photoresist is carried out to exposure imaging, remove the photoresist of active layer and etching barrier layer region A, residue photoresist 103.
As shown in Figure 5, form successively active layer material film 104 ＇, except active layer material film 104 ＇ of active layer region A cover on substrate 101, active layer material film 104 ＇ in other region all cover on photoresist 103.In Fig. 5, one deck etching barrier layer material film 105 ＇ can also be formed at source layer material film 104 ＇.
As shown in Figure 6, peel off residue photoresist 103, form the figure of active layer 104.In the present embodiment, active layer material is oxide semiconductor, as IGZO.In Fig. 6, can also form the figure (etching barrier layer 105 is not essential) of etching barrier layer 105.
Step 3, forms and comprises the figure of gate insulation layer, and exposes the region of drain electrode and anodic bonding to be formed.This step specifically comprises:
As shown in Figure 7, on the substrate after step 2, form gate insulation layer 106.
As shown in Figure 8, in the present embodiment, by composition technique in the region formation of drain electrode 102b and anodic bonding to be formed the via hole 107 through gate insulation layer 106.Certainly can also fall by composition technique direct etching the gate insulation layer film in the region of anode region and drain electrode and anodic bonding to be formed, finally to form gate insulation layer 106.
As shown in Figure 9, on the substrate after step 3, form gate electrode material film 108.
As shown in figure 10, form the figure of grid 109 by composition technique at area of grid C, anode region D forms the figure of anode 110.After forming, grid 109 forms the thin-film transistor (comprising source electrode 102a, drain electrode 102b, active layer 104, etching barrier layer 105, gate insulation layer 106 and grid 109) of top gate structure.
In the present embodiment, because anode 110 will reflect the light that luminous organic material sends, therefore, the material of grid 109 and anode 110 is to have the metal of reflective characteristic or the metallic compound of conduction, can be Ag, Au, AlX, MoX, CuX, Al, Ti or Cr, wherein AlX, MoX or CuX be the metallic compounds of conduction.The thickness of grid 109 and anode 110 is:
Step 5, forms the figure that comprises pixel defining layer, organic material layer and transparent cathode.Specifically comprise:
As shown in figure 11, region E(on substrate after step 4 is TFT regions) form pixel defining layer 111 by composition technique, the region F that does not form pixel defining layer 111 is pixel region, it is the light-emitting zone of organic luminous layer, conventionally pixel defining layer 111 is mainly used in blocking the region that TFT, grid line and data wire are corresponding, to avoid the active layer 104 of the oxide semiconductor in thin-film transistor by illumination, thus the performance of assurance thin-film transistor.
On 11 basis, form successively in the drawings organic luminous layer 112 and negative electrode 113, as shown in Figure 2, anode 110, organic luminous layer 112 and negative electrode 113 that region F is corresponding are formed with OLED jointly, thereby form the array base palte of OLED display unit.
The array substrate manufacturing method of the present embodiment is composition technique in step 1 to respectively having used a mask(in step 5), totally 5 mask.With respect to 7 mask techniques of existing array base palte, reduce number mask time, save technological process and cost.
The utility model also provides a kind of display unit, comprises above-mentioned array base palte.This display unit can be: any product or parts with Presentation Function such as oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Above execution mode is only for illustrating the utility model; and be not limitation of the utility model; the those of ordinary skill in relevant technologies field; in the situation that not departing from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (8)
1. an array base palte, comprises the grid line and the data wire that are formed on substrate, and the multiple pixel cells that limited by described grid line and data wire, it is characterized in that, each described pixel cell is divided into TFT regions and light-emitting zone;
Described TFT regions is formed with at least one thin-film transistor, and described thin-film transistor comprises the source-drain electrode layer, active layer, gate insulation layer and the grid that are formed on successively on described substrate;
Above the substrate of described light-emitting zone, be formed with anode, the drain electrode of source-drain electrode layer described in described anodic bonding, described anode and grid are same material and form in one-time process, anode top is formed with organic luminous layer and negative electrode successively, and the organic luminous layer of described anode and anode corresponding region and negative electrode are formed with OLED jointly;
On described thin-film transistor, be also formed with pixel defining layer.
2. array base palte as claimed in claim 1, is characterized in that, described organic luminous layer and negative electrode cover whole substrate regions, and described pixel defining layer is formed between thin-film transistor and described organic luminous layer.
3. array base palte as claimed in claim 2, is characterized in that, described pixel defining layer also covers described grid line and data wire corresponding region.
4. the array base palte as described in any one in claim 1～3, is characterized in that, the material of described active layer is oxide semiconductor.
5. the array base palte as described in any one in claim 1～3, is characterized in that, the material of described grid and anode is the metal with reflective characteristic.
6. array base palte as claimed in claim 5, is characterized in that, described in there is reflective characteristic metal comprise: Ag, Au, Al, Ti or Cr.
7. the array base palte as described in any one in claim 1～3, is characterized in that, the thickness of described grid and anode is:
8. a display unit, is characterized in that, comprises the array base palte as described in any one in claim 1～7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320844965.XU CN203674211U (en) | 2013-12-19 | 2013-12-19 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320844965.XU CN203674211U (en) | 2013-12-19 | 2013-12-19 | Array substrate and display device |
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| CN203674211U true CN203674211U (en) | 2014-06-25 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103647028A (en) * | 2013-12-19 | 2014-03-19 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106206427A (en) * | 2016-08-15 | 2016-12-07 | 京东方科技集团股份有限公司 | The manufacture method of display base plate, the manufacture method of display device and display base plate |
| CN106501998A (en) * | 2016-10-26 | 2017-03-15 | 京东方科技集团股份有限公司 | Backlight, display device and its driving method |
| WO2020140767A1 (en) * | 2019-01-02 | 2020-07-09 | 京东方科技集团股份有限公司 | Transparent display substrate and manufacturing method therefor, and transparent display panel |
| JP7422209B1 (en) | 2022-10-25 | 2024-01-25 | ティーシーエル チャイナスター オプトエレクトロニクス テクノロジー カンパニー リミテッド | Display panel, its manufacturing method, and display device |
-
2013
- 2013-12-19 CN CN201320844965.XU patent/CN203674211U/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103647028A (en) * | 2013-12-19 | 2014-03-19 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103647028B (en) * | 2013-12-19 | 2016-11-09 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN106206427A (en) * | 2016-08-15 | 2016-12-07 | 京东方科技集团股份有限公司 | The manufacture method of display base plate, the manufacture method of display device and display base plate |
| WO2018032753A1 (en) * | 2016-08-15 | 2018-02-22 | 京东方科技集团股份有限公司 | Manufacturing method for display substrate, manufacturing method for display device, and display substrate |
| US10580806B2 (en) | 2016-08-15 | 2020-03-03 | Boe Technology Group Co., Ltd. | Method of manufacturing a display substrate, method of manufacturing a display device and display substrate |
| CN106501998A (en) * | 2016-10-26 | 2017-03-15 | 京东方科技集团股份有限公司 | Backlight, display device and its driving method |
| CN106501998B (en) * | 2016-10-26 | 2020-01-17 | 京东方科技集团股份有限公司 | Backlight source, display device and driving method thereof |
| US10573230B2 (en) | 2016-10-26 | 2020-02-25 | Boe Technology Group Co., Ltd. | Backlight source, display device and driving method thereof |
| WO2020140767A1 (en) * | 2019-01-02 | 2020-07-09 | 京东方科技集团股份有限公司 | Transparent display substrate and manufacturing method therefor, and transparent display panel |
| US11489029B2 (en) | 2019-01-02 | 2022-11-01 | Boe Technology Group Co., Ltd. | Transparent display substrate including capacitor overlapping driving and switching TFTs, and manufacturing method therefor |
| JP7422209B1 (en) | 2022-10-25 | 2024-01-25 | ティーシーエル チャイナスター オプトエレクトロニクス テクノロジー カンパニー リミテッド | Display panel, its manufacturing method, and display device |
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Granted publication date: 20140625 |
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| CX01 | Expiry of patent term |