CN103646938A - Primary plating-prior-to-etching metal frame subtraction imbedded chip flip bump structure and process method - Google Patents
Primary plating-prior-to-etching metal frame subtraction imbedded chip flip bump structure and process method Download PDFInfo
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- CN103646938A CN103646938A CN201310645450.1A CN201310645450A CN103646938A CN 103646938 A CN103646938 A CN 103646938A CN 201310645450 A CN201310645450 A CN 201310645450A CN 103646938 A CN103646938 A CN 103646938A
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- photoresistance film
- metal substrate
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 100
- 239000002184 metal Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000003963 antioxidant agent Substances 0.000 claims abstract description 32
- 230000003078 antioxidant effect Effects 0.000 claims abstract description 31
- 239000004033 plastic Substances 0.000 claims abstract description 24
- 239000005022 packaging material Substances 0.000 claims abstract description 20
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims abstract 2
- 235000006708 antioxidants Nutrition 0.000 claims description 30
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- 238000003384 imaging method Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 11
- 238000003486 chemical etching Methods 0.000 claims description 10
- 238000004806 packaging method and process Methods 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- -1 NiPdAu Chemical compound 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 2
- 239000003292 glue Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 14
- 238000001465 metallisation Methods 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000011112 process operation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a primary plating-prior-to-etching metal frame subtraction imbedded chip flip bump structure and a process method. The structure is characterized in that the structure comprises a metal base frame; the metal base frame is internally provided with base islands and pins; the back surface of each base island and the step surface of each pin are invertedly provided with a chip through bottom filling glue; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas under the base islands and the pins and the outer sides of the chips are wrapped with plastic packaging materials; the surface of the metal substrate fame is plated with an anti-oxidation layer or a coated antioxidant (OSP), wherein the plastic packaging materials are flush with the anti-oxidation layers or coated antioxidants (OSP) on the upper and lower surfaces of the metal substrate fame; and the back surface of each pin is provided with a metal ball. With the structure and by utilizing the method, the problem that the function and the application performance of a conventional metal lead frame are limited since an object cannot be imbedded in the metal lead frame of such plate thickness can be solved.
Description
Technical field
The present invention relates to a kind of once first plating loses afterwards metal frame subtraction and buries flip-chip bump structure and process thereof.Belong to semiconductor packaging field.
Background technology
Traditional flat-four-side mainly contains two kinds without pin metal leadframe structure:
Be flat-four-side without pin package (QFN) lead frame, the lead frame of this structure forms (as shown in figure 14) by copper material metal framework and high temperature resistant glued membrane.
Be to seal in advance flat-four-side without pin package (pQFN) lead frame, the lead frame structure of this structure comprises pin Yu Ji island, and the etching area between pin Yu Ji island is filled with plastic packaging material (as shown in figure 15).
There is following shortcoming in above-mentioned traditional metal lead frame:
1, traditional metal lead frame is as the package carrier that loads chip, and itself does not possess systemic-function, thereby has limited integrated functionality and application performance after traditional metal leadframe package;
2,, because traditional metal lead frame itself does not possess systemic-function, can only carry out in lead frame front tiling or the stacked package of chip and assembly.And power device and control chip are encapsulated in same packaging body, the heat radiation of power device can affect the transmission of control chip signal;
3, because traditional metal lead frame itself does not possess systemic-function, so multifunction system integration module can only be in traditional metal lead frame front by tiling or stacking realization of multi-chip and assembly, correspondingly also just increase component module shared space on PCB.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, provide a kind of once first plating to lose afterwards metal frame subtraction and bury flip-chip bump structure and method thereof, it can solve the problem that traditional metal lead frame lacks systemic-function.
The object of the present invention is achieved like this: a kind of once first plating lost the manufacture method that metal frame subtraction buries flip-chip bump structure afterwards, and described method comprises the steps:
Step 2, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at metal substrate;
Step 3, metallic substrate surfaces are removed part photoresistance film
The metallic substrate surfaces of utilizing exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film;
Step 4, plating anti-oxidant metal layer or coating antioxidant (OSP)
In step 3, metallic substrate surfaces is removed in the region of part photoresistance film and is electroplated anti-oxidant metal layer, prevents burning, as golden in gold, nickel, NiPdAu, tin or coating antioxidant (OSP).
Step 5, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 6, the operation of subsides photoresistance film
On the surface label of metal substrate, can carry out the photoresistance film of exposure imaging;
Step 7, metallic substrate surfaces are removed part photoresistance film
The metallic substrate surfaces of utilizing exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film, specifically remove and electroplate anti-oxidant metal layer photoresistance film in addition, to expose, the metal substrate back side is follow-up need to carry out etched regional graphics;
Step 8, chemical etching
In step 7, in the region of metallic substrate surfaces removal part photoresistance film, carry out the chemical etching of different depth, after chemical etching completes, form corresponding Ji island and step-like pin;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, load
At the back side, step 9 Ji island and pin step surface, the chip that completes surface and have salient point is carried out to upside-down mounting, after completing and carry out bottom by underfill and fill protection;
Step 11, seal
The inner plastic packaging material that adopts of the metal substrate of step 10 is carried out to plastic packaging, and plastic packaging material all flushes with the front and back of metal substrate.
Step 12, plant ball
At the pin back side of step 11 implanted metal ball.
When the anti-oxidant metal layer in step 4 is nickel gold or NiPdAu, described step 6 and step 7 can be omitted.
A kind of once first plating lost afterwards metal frame subtraction and buried flip-chip bump structure, it comprises Metal Substrate sheet frame, in described Metal Substrate sheet frame inside, be provided with Ji Dao and pin, described pin is step-like, the front of described Ji Dao and pin flushes with Metal Substrate sheet frame front, the back side of described pin flushes with the back side of Metal Substrate sheet frame, the described Ji Dao back side flushes with the step surface of pin, there is chip at the back side of described Ji Dao by underfill upside-down mounting, the region of periphery, described base island, region between Ji Dao and pin, region between pin and pin, the region on Ji Dao and pin top, the region of Ji Dao and pin bottom and chip are all encapsulated with plastic packaging material outward, described plastic packaging material flushes with the upper and lower surface of Metal Substrate sheet frame, positive on described base island, the surface of the front and back of pin and Metal Substrate sheet frame is coated with anti oxidation layer or coating antioxidant (OSP), described plastic packaging material flushes with anti oxidation layer or the coating antioxidant (OSP) of Metal Substrate sheet frame upper and lower surface, front at described pin is provided with Metal Ball.
On the step surface of the described Ji Dao back side and pin, be provided with metal level.
Compared with prior art, the present invention has following beneficial effect:
1, the interlayer of subtractive metallization technology lead frame can be because of the needs of system and function be imbedded active member or assembly or passive assembly in the position of needs or region, becomes a system-level metal lead wire frame of individual layer circuit;
2, from the outward appearance of subtractive metallization technology lead frame finished product, can't see inner interlayer has completely imbedded because of system or the object of function needs, especially the imbedding X-ray and all cannot inspect of the chip of silicon material, fully reaches confidentiality and the protectiveness of system and function;
3, the interlayer of subtractive metallization technology lead frame can be imbedded high-power component in manufacturing process, secondary encapsulation carries out the load of control chip again, thereby high-power component and control chip are contained in respectively subtractive metallization technology lead frame both sides, can avoid high-power component to disturb the signal of control chip because of thermal radiation and transmit.
4, subtractive metallization technology lead frame itself includes the function of imbedding object, after secondary encapsulation, can fully realize the integrated of systemic-function and integrate, it is little that thereby the volume size of the component module of said function comes than the module of conventional lead frame encapsulation, corresponding space shared on PCB is also just fewer, thereby has also just reduced cost.
5, the interlayer of subtractive metallization technology lead frame can be because heat conduction or heat radiation need in manufacturing process be imbedded heat conduction or heat radiation object in the position of needs or region, thereby improves the radiating effect of whole encapsulating structure;
6, subtractive metallization technology lead frame finished product itself has just been rich in various assemblies, if no longer carried out in the situation of follow-up encapsulation for the second time, subtractive metallization technology lead frame is cut according to each lattice unit, itself just can become a ultra-thin packaging body or compact system level encapsulation body;
7, subtractive metallization technology lead frame, except itself including imbedding of object can also superpose in packaging body periphery function different unit package or system in package, fully reaches the dual system of individual layer circuit metal lead wire frame or the encapsulation technology ability of polyphyly irrespective of size again.
8, object or the object in subtractive metallization technology lead frame, imbedded all flush with metal thickness, embody fully among the ultra-thin and highdensity thickness space being filled in subtractive metallization technology lead frame.
Accompanying drawing explanation
Fig. 1 ~ Figure 12 is that the present invention once first plates and loses afterwards each operation schematic diagram that metal frame subtraction buries the process of flip-chip bump structure.
Figure 13 is that the present invention once first plates and loses afterwards the schematic diagram that metal frame subtraction buries flip-chip bump structure.
Figure 14 is that traditional flat-four-side is without the schematic diagram of pin package (QFN) lead frame structure.
Figure 15 is for to seal flat-four-side without the schematic diagram of pin package (pQFN) lead frame structure in advance.
Wherein:
Metal Substrate sheet frame 1
Base island 2
Pin 3
Underfill 4
Chip 5
Plastic packaging material 6
Anti-oxidant metal layer or coating antioxidant 7
Metal Ball 8.
Embodiment
The present invention is a kind of once first to plate and loses afterwards metal frame subtraction to bury the process of flip-chip bump structure as follows:
Referring to Fig. 1, get the metal substrate that a slice thickness is suitable, the material of this sheet material is mainly to take metal material as main, and the metallics of the material of metal material can be the zinc-plated Cai ﹑ of Tong Cai ﹑ Tie Cai ﹑ Bu rust Gang Cai ﹑ aluminium maybe can reach conducting function or non-all-metal material etc., the selection of thickness can be selected according to product performance.
Step 2, the operation of subsides photoresistance film
Referring to Fig. 2, at front and the back side of metal substrate, stick respectively the photoresistance film that can carry out exposure imaging, to protect follow-up etch process operation, photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Step 3, metallic substrate surfaces are removed part photoresistance film
Referring to Fig. 3, the metallic substrate surfaces (front and back) of utilizing exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs of metallic substrate surfaces.
Step 4, plating anti-oxidant metal layer or coating antioxidant (OSP)
Referring to Fig. 4, in step 3, metallic substrate surfaces is removed in the region of part photoresistance film and is electroplated anti-oxidant metal layer, prevents burning, as golden in gold, nickel, NiPdAu, tin or coating antioxidant (OSP).
Step 5, removal photoresistance film
Referring to Fig. 5, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove photoresistance film.
Step 6, the operation of subsides photoresistance film
Referring to Fig. 6, on the surface label of metal substrate, can carry out the photoresistance film of exposure imaging, to protect follow-up etch process operation, photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Step 7, metallic substrate surfaces are removed part photoresistance film
Referring to Fig. 7, the metallic substrate surfaces of utilizing exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film, specifically remove and electroplate anti-oxidant metal layer photoresistance film in addition, to expose, the metal substrate back side is follow-up need to carry out etched regional graphics.
Step 8, chemical etching
Referring to Fig. 8, in step 7, in the region of metallic substrate surfaces removal part photoresistance film, carry out the chemical etching of different depth, after chemical etching completes, can form corresponding Ji Dao and step-like pin, etching solution can adopt copper chloride or iron chloride or liquid medicine or the technology that can carry out metal material chemical etching.
Step 9, removal photoresistance film
Referring to Fig. 9, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove photoresistance film.
Step 10, load
Referring to Figure 10, at the back side, step 9 Ji island and pin step surface, the chip that completes surface and have salient point is carried out to upside-down mounting, after completing and carry out bottom by underfill and fill protection.
Tin diffusion when preventing the electrical interconnected and upside-down mounting between metal substrate oxidation affects chip and substrate therefore can first be carried out anti-oxidant metal layer plating or antioxidant coating in the exposed metal surface of metallic substrate surfaces before step 10 load.
Step 11, seal
Referring to Figure 11, the inner plastic packaging material that adopts of the metal substrate of step 10 is carried out to plastic packaging, plastic packaging material flushes with anti oxidation layer or the coating antioxidant (OSP) of metal substrate upper and lower surface, plastic packaging mode can adopt mould encapsulating mode, spraying method, brush coating mode or pad pasting mode, and described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Step 12, plant ball
Referring to Figure 12, at the pin front of step 15 implanted metal ball, the mode of planting ball can be that direct implanted metal ball can be also to adopt mask plate (MASK) to brush into metal paste, then goes into Metal Ball through high temperature reflux.
Referring to Figure 13, for the present invention is a kind of, once first plates and lose afterwards the structural representation that metal frame subtraction buries flip-chip bump structure, it comprises Metal Substrate sheet frame 1, in described Metal Substrate sheet frame 1 inside, be provided with base island 2 and pin 3, described pin 3 is step-like, the front of described base island 2 and pin 3 flushes with Metal Substrate sheet frame 1 front, the back side of described pin 3 flushes with the back side of Metal Substrate sheet frame 1, 2 back sides, described base island flush with the step surface of pin 3, there is chip 5 at the back side on described base island 2 by underfill 4 upside-down mountings, the region of 2 peripheries, described base island, region between base island 2 and pin 3, region between pin 3 and pin 3, the region on base island 2 and pin 3 tops, the region of base island 2 and pin 3 bottoms and chip are all encapsulated with plastic packaging material 6 outward, described plastic packaging material 6 flushes with the upper and lower surface of Metal Substrate sheet frame 1, in 2 fronts, described base island, the surface of the front and back of pin 3 and Metal Substrate sheet frame 1 is coated with anti oxidation layer or coating antioxidant (OSP) 7, described plastic packaging material 6 flushes with anti oxidation layer or the coating antioxidant (OSP) 7 of Metal Substrate sheet frame 1 upper and lower surface, in the front of described pin 3, be provided with Metal Ball 8.
Claims (5)
1. once first plate and lose afterwards the process that metal frame subtraction buries flip-chip bump structure, described method comprises the steps:
Step 1, get metal substrate
Step 2, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at metal substrate;
Step 3, metallic substrate surfaces are removed part photoresistance film
The metallic substrate surfaces of utilizing exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film;
Step 4, plating anti-oxidant metal layer or coating antioxidant (OSP)
In step 3, metallic substrate surfaces is removed in the region of part photoresistance film and is electroplated anti-oxidant metal layer, prevents burning, as golden in gold, nickel, NiPdAu, tin or coating antioxidant (OSP);
Step 5, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 6, the operation of subsides photoresistance film
On the surface label of metal substrate, can carry out the photoresistance film of exposure imaging;
Step 7, metallic substrate surfaces are removed part photoresistance film
The metallic substrate surfaces of utilizing exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film, specifically remove and electroplate anti-oxidant metal layer photoresistance film in addition, to expose, the metal substrate back side is follow-up need to carry out etched regional graphics;
Step 8, chemical etching
In step 7, in the region of metallic substrate surfaces removal part photoresistance film, carry out the chemical etching of different depth, after chemical etching completes, form corresponding Ji island and step-like pin;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, load
At the back side, step 9 Ji island and pin step surface, the chip that completes surface and have salient point is carried out to upside-down mounting, after completing and carry out bottom by underfill and fill protection;
Step 11, seal
The inner plastic packaging material that adopts of the metal substrate of step 10 is carried out to plastic packaging, and plastic packaging material all flushes with the front and back of metal substrate;
Step 12, plant ball
At the pin back side of step 11 implanted metal ball.
2. according to claim 1ly once first plate and lose afterwards the process that metal frame subtraction buries the flat leg structure of chip formal dress, while it is characterized in that anti-oxidant metal layer in step 4 is nickel gold or NiPdAu, described step 6 and step 7 can be omitted.
3. by prepared a kind of once first plating of claim 1 or 2, lose afterwards metal frame subtraction and bury flip-chip bump structure, it is characterized in that it comprises Metal Substrate sheet frame (1), in described Metal Substrate sheet frame (1) inside, be provided with Ji Dao (2) and pin (3), described pin (3) is step-like, the front of described Ji Dao (2) and pin (3) flushes with Metal Substrate sheet frame (1) front, the back side of described pin 3 flushes with the back side of Metal Substrate sheet frame (1), described Ji Dao (2) back side flushes with the step surface of pin (3), there is the peripheral region of the described Ji Dao of chip (5) (2) at the back side of the described Ji Dao of described pin (3) (2) by underfill (4) upside-down mounting, region between Ji Dao (2) and pin (3), region between pin (3) and pin (3), the region on Ji Dao (2) and pin (3) top, the outer plastic packaging material (6) that is all encapsulated with of the region of Ji Dao (2) and pin (3) bottom and chip (5), described plastic packaging material (6) flushes with the upper and lower surface of Metal Substrate sheet frame (1), in described Ji Dao (2) front, the surface of the front and back of pin (3) and Metal Substrate sheet frame (1) is coated with anti oxidation layer or coating antioxidant (OSP) (7), described plastic packaging material (6) flushes with anti oxidation layer or the coating antioxidant (OSP) (7) of Metal Substrate sheet frame (1) upper and lower surface, at described pin (3) back side, be provided with Metal Ball (8).
4. according to claim 3 once first plating lost afterwards metal frame subtraction and buried flip-chip bump structure, it is characterized in that: on the step surface of described Ji Dao (2) back side and pin (3), be provided with metal level.
5. according to claim 3ly a kind ofly once first plate and lose afterwards the process that metal frame subtraction buries the flat leg structure of flip-chip, it is characterized in that: in step 9, remove between photoresistance film and step 10 load and carry out anti-oxidant metal layer plating or antioxidant coating (OSP) in the exposed metal surface of metallic substrate surfaces.
Priority Applications (1)
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| CN201310645450.1A CN103646938B (en) | 2013-12-05 | 2013-12-05 | Once first plate and lose metal frame subtraction afterwards and bury flip-chip bump structure and process |
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| CN103646938B CN103646938B (en) | 2016-02-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9806043B2 (en) | 2016-03-03 | 2017-10-31 | Infineon Technologies Ag | Method of manufacturing molded semiconductor packages having an optical inspection feature |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030064547A1 (en) * | 1999-02-01 | 2003-04-03 | Salman Akram | High density modularity for IC's |
| CN1453858A (en) * | 2002-04-22 | 2003-11-05 | Nec化合物半导体器件株式会社 | Semiconductor device and producing method thereof |
| US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
| CN101814446A (en) * | 2010-04-28 | 2010-08-25 | 江苏长电科技股份有限公司 | Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof |
| CN101814482A (en) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | Base island lead frame structure and production method thereof |
| CN102714201A (en) * | 2010-01-19 | 2012-10-03 | 维西埃-硅化物公司 | Semiconductor package and method |
| US20130056861A1 (en) * | 2011-03-17 | 2013-03-07 | Freescale Semiconductor, Inc | Semiconductor devices and methods of assembling same |
| CN103400771A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching chip-flipped type three-dimensional system-level metal circuit board structure and process method thereof |
-
2013
- 2013-12-05 CN CN201310645450.1A patent/CN103646938B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030064547A1 (en) * | 1999-02-01 | 2003-04-03 | Salman Akram | High density modularity for IC's |
| CN1453858A (en) * | 2002-04-22 | 2003-11-05 | Nec化合物半导体器件株式会社 | Semiconductor device and producing method thereof |
| US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
| CN102714201A (en) * | 2010-01-19 | 2012-10-03 | 维西埃-硅化物公司 | Semiconductor package and method |
| CN101814446A (en) * | 2010-04-28 | 2010-08-25 | 江苏长电科技股份有限公司 | Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof |
| CN101814482A (en) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | Base island lead frame structure and production method thereof |
| US20130056861A1 (en) * | 2011-03-17 | 2013-03-07 | Freescale Semiconductor, Inc | Semiconductor devices and methods of assembling same |
| CN103400771A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching chip-flipped type three-dimensional system-level metal circuit board structure and process method thereof |
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| US9806043B2 (en) | 2016-03-03 | 2017-10-31 | Infineon Technologies Ag | Method of manufacturing molded semiconductor packages having an optical inspection feature |
| US10431560B2 (en) | 2016-03-03 | 2019-10-01 | Infineon Technologies Ag | Molded semiconductor package having an optical inspection feature |
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