CN103646856A - Method for improving strain-layer boundary defects - Google Patents
Method for improving strain-layer boundary defects Download PDFInfo
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- CN103646856A CN103646856A CN201310554641.7A CN201310554641A CN103646856A CN 103646856 A CN103646856 A CN 103646856A CN 201310554641 A CN201310554641 A CN 201310554641A CN 103646856 A CN103646856 A CN 103646856A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- H01L21/02532—Silicon, silicon germanium, germanium
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Abstract
The invention provides a method for improving strain-layer boundary defects, which is applied to a preparation process of a semiconductor device. The semiconductor device includes a substrate and a source region and a drain region are formed on the substrate. A grid is formed on the substrate between the source region and the drain region. Side walls and a side wall structure are also formed on the grid. Parts of the source region and the drain region, in the substrate, are etched and removed through adoption of a plasma-etching process; wet process cleaning is carried out and cavity corrosion, film laminating and baking processes are carried out; and a dry etching process is continued to be carried out to remove impurities at the etching source/drain region boundary and finally a silicon-germanium layer is developed on the source region and the drain region. In the method for improving the strain-layer boundary defects, the dry etching process is added so that impurities which exist on the etching surface of the boundaries between the substrate and the source and drain regions can be better cleared and at the same time, the flatness of the etching surface can also be improved; and crystal-lattice damages are not generated at the boundaries during follow-up preparation of silicon germanide so that device yield and product performance are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of method of improving strained layer boundary defect.
Background technology
In recent years, a kind of development of following Moore's Law of semicon industry, that is: when price is constant, open ended transistor size on integrated circuit, approximately just can double every 18 months, and performance also will promote one times.From beginning so far, people endeavour research always and produce high performance semiconductor device to realize arithmetic speed faster.
As everyone knows, the performance of cmos circuit is subject to the restriction of PMOS to a great extent, therefore, if the level that any technology can be brought up to NMOS the performance of PMOS is all considered to favourable.In the PMOS of 90nm technique, Intel(Intel) engineer removes the source of device, water clock etching off, deposit silicon germanium layer again then, and source electrode and drain electrode will produce a compression stress to raceway groove like this, thereby improve the transmission characteristic of PMOS, and then boost device performance.
Silicon Germanium source/leakage is implanted and caused strain gauge technique is that SiGe is mounted to source-drain area, thereby produces compressive deformation at raceway groove place, improve the transistorized carrier mobility of PMOS, and the raising of carrier mobility can cause high drive current, improves transistor performance.
Grown silicon germanium film on silicon substrate, the technique of developing strain layer is epitaxy technique process, if interface is not processed with regard to grown silicon germanium layer, SiGe can not form good mono-crystalline structures, in growth course, relaxation phenomena will occur, and the strain meeting accumulating in film causes crystal-plane slip, interface atomic arrangement is staggered, strain sharply discharges, and produces a large amount of defects in film, causes deformation relaxation.
In prior art, generally adopt following technical scheme to prepare SiGe strain layer:
Semiconductor structure is provided, and this semiconductor structure comprises a substrate 1, and preferred, this substrate is silicon substrate; This substrate 1 is formed with source region and drain region, is positioned on substrate and is formed with grid 2 between source region and drain region, and described grid also forms sidewall 3 and sidewall structure 4; Etching is removed the silicon of substrate 1 interior source-drain area, forms structure shown in Fig. 2;
Because the etching interface through over etching opisthogenesis drain region easily has the existence of lattice damage, if directly carry out the growth meeting of SiGe outer, at SiGe-silicon interface, form defect, affect device performance, therefore also need etching interface to process, so that etching interface is more smooth: carry out pretreating process, adopt wet-cleaned to remove the impurity of source-drain area etching interface, and after being dried, finally at the source-drain area germanium-silicon layer 5 of growing.
Because traditional wet-cleaned can not accomplish crystal column surface to carry out trickle processing, cause at crystal column surface and have local residual impurity, or be uneven, as shown in Figure 3, after simple preliminary treatment, be difficult to obtain a comparatively ideal pattern, cause after germanium-silicon layer 5 epitaxial growths, in generation of interfaces defect source, as shown in Figure 4; And serious defect may be extended to the growing surface of SiGe and easily form lattice damage, cause SiGe can not form good mono-crystalline structures, in growth course, will there is relaxation, the strain meeting accumulating in film causes crystal-plane slip, and interface atomic arrangement is staggered, and strain sharply discharges, in film, produce a large amount of defects, cause deformation relaxation, and then affect device performance, this is that those skilled in the art do not want to see.
Chinese patent (CN 102104067A) discloses the transistor in a kind of epitaxial growth source/drain region, comprising: substrate; Be positioned at the grid structure on described substrate; Be formed in substrate, be positioned at source region and the drain region of described grid structure both sides, described source region and drain region comprise the first homogeneity epitaxial layer of doping, the second homogeneity epitaxial layer that is positioned at the epitaxially deposited layer of the doping on described the first homogeneity epitaxial layer and is positioned at the doping on described epitaxially deposited layer.
Then this patent prepares a material layer at source-drain area by etching source-drain electrode, but removes after source-drain area in etching, may leave at interface impurity and particle, can cause defect at interface, and then affect device performance if directly prepare epitaxial loayer.
Summary of the invention
The invention provides a kind of method of improving strained layer boundary defect, in etching, remove after source-drain electrode and cleaning, then carry out a dry etch process, to remove the residual impurity of etching interface, and then carry out follow-up silicon germanium extension layer production technology.The present invention by increase a dry etching etching technics can be fine the impurity that exists of removal etching interface improve irregular surface, the defect of minimizing source/drain electrode and substrate interface.
The technical solution used in the present invention is:
A kind of method of improving strained layer boundary defect, be applied in the preparation technology of semiconductor device, this semiconductor device comprises a substrate, described substrate forms active area and drain region, between source region and drain region, be positioned on described substrate and be formed with grid, described grid also forms sidewall and sidewall structure, wherein, comprises the following steps:
Adopt the first etching technics etching to remove the part that is positioned at substrate source region and drain region; Then clean go forward side by side an actor's rendering of an operatic tune body burn into overlay film and a baking process;
Proceed the second etching technics and remove the impurity at interface, etching source/drain region, the strained layer of finally growing in source region and drain region.
Above-mentioned method, wherein, described the first etching technics is plasma etching industrial, and adopts wet-etching technology to clean.
Above-mentioned method wherein, passes into H when toasting
2.
Above-mentioned method, wherein, described the second etching technics is dry etch process.
Above-mentioned method, wherein, adopting hydrogen chloride is that reacting gas carries out described dry etch process.
Above-mentioned method wherein, is carried out described dry etch process under the environment of high-temperature low-pressure, in temperature, is 700～800 ℃, carries out etching under the condition that pressure is 100～600Torr.
Above-mentioned method, wherein, described strained layer is germanium-silicon layer.
Above-mentioned method, wherein, adopts selective epitaxial growth process to prepare described germanium-silicon layer.
Above-mentioned method, wherein, described method is applied to embedded or non-embedded SiGe outer growth technique.
Because the present invention has adopted above technical scheme, before source-drain area is prepared silicon germanium extension layer, first adopt a dry etch process to process the impurity at source-drain area interface, make source-drain area-substrate interface become more smooth, when follow-up formation SiGe, can avoid in interface, forming defect, improve production technology.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 forms the schematic diagram of germanium-silicon layer at substrate source-drain area in prior art;
Fig. 2 is device sectional view after etching removal source-drain electrode;
Fig. 3 is that prior art is through pretreated device sectional view;
Fig. 4 is the device sectional view of prior art after source-drain area grown silicon germanium layer;
Fig. 5 is the schematic diagram of the present invention while carrying out dry etch process;
Fig. 6 is the device sectional view after dry etch process of the present invention completes
Fig. 7 is the device sectional view of the present invention after source-drain area grown silicon germanium layer.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The invention provides a kind of method of improving strained layer boundary defect, be applied to, in the growth technique of embedded or non-embedded SiGe outer, comprise the following steps:
Step S1: first semiconductor structure is provided, and this semiconductor structure comprises a substrate 1, preferred, this substrate is silicon substrate; This substrate 1 is formed with source region and drain region, is formed with grid 2 being positioned between source region and drain region on substrate 1, and grid 2 also forms sidewall 3 and sidewall structure 4.
Step S2: adopt photoetching process and remove the source-drain area part that is positioned at substrate 1 in conjunction with dry etching.Concrete steps are: spin coating one deck photoresist, then carry out exposure imaging technique, and in photoresist, form an opening that exposes source-drain area, then utilize this Open Side Down and carry out plasma etching and remove the silicon that is positioned at source-drain area.After carrying out etching, the characteristic due to plasma etching, easily leaves impurity in etching interface, and possibility etching is insufficient simultaneously, forms irregular etching surface, therefore need to carry out follow-up treatment process etching interface is processed, can be with reference to shown in Fig. 2.
Step S3: substrate is carried out to pretreating process, comprising: wet-cleaned, to remove particle and the oxide-film of etching interface, then carry out chamber etching, overlay film, then substrate is carried out to baking process silicon chip is kept dry, as shown in Figure 3.Because simple wet-cleaned can not be removed the impurity of etching surface completely, cause also can leaving impurity in etching interface, can not obtain a smooth surface simultaneously, therefore the present invention continues next step remaining impurity is further cleared up, and then improves the evenness of source-drain area etching surface.
Step S4: under the environment of high-temperature low-pressure, adopt dry etching to remove the remaining granule foreign of source-drain area etching surface, and improve irregular etching surface.In an embodiment of the present invention, by silicon chip be placed in temperature be 700～800 ℃ (as 700 ℃, 750 ℃, 800 ℃ of equivalences), pressure be 100～600Torr(as 100Torr, 300Torr, 600Torr is equivalent) condition under, and to select hydrogen chloride be that reacting gas carries out dry etching, so that etching surface is further cleared up.After wafer is cleaned, because wet-cleaned liquid cannot accomplish the trickle impurity of crystal column surface and particle to remove, cause being formed with trickle particle or impurity at source-drain area etching surface, the degree of simultaneously improving out-of-flatness surface is also more limited, therefore the present invention continues to have adopted a dry etching to be further processed blemish surface in the situation that of high-temperature low-pressure, as shown in Fig. 5-6, adopt dry etching can effectively remove the impurity that source-drain area etching interface is not cleaned, also can remove the protrusion that etching surface may exist simultaneously, make etching surface more smooth, and then improve the smoothness of etching surface.
Further, the present invention adopts hydrogen chloride gas to carry out etching under the condition of high-temperature low-pressure (be that temperature is 700～800 ℃, pressure is 100～600Torr), can not cause damage to silicon substrate, can access the etching effect an of the best simultaneously.
Step S5: prepare a strained layer at source-drain area, this material layer can adopt different technical scheme preparations to form according to different technique, as in embedded or non-embedded SiGe process, adopt selectivity outer growth technique to prepare a germanium-silicon layer 6 in source-drain area, by prepare a germanium-silicon layer 6 at source-drain area, thereby at raceway groove place, produce compressive deformation, improve transistorized carrier mobility, and then raising drive current, be conducive to the lifting of transistor performance.Because the present invention is carrying out after traditional preliminary treatment source-drain area surface, under the environment of high-temperature low-pressure, adopt again hydrogen chloride to carry out dry etching as reacting gas, can more thoroughly remove the residual impurity in interface, and improve irregular surface, make the interface of SiGe strain layer and silicon substrate more level and smooth, in interface, should not produce defect and lattice damage, avoid the generation of leakage current, and then boost device performance.
In sum, because the present invention has adopted above technical scheme, after using the impurity of wet-cleaned removal etching interface, a dry etch process is carried out in continuation under the condition of high-temperature low-pressure, more thoroughly to remove the impurity at interface, improves roughness and the cleannes of etching surface, also make the germanium-silicon layer of subsequent growth and the interface of substrate more level and smooth simultaneously, can not produce lattice damage at interface, reduce the generation of leakage current, improve device performance.The present invention can be applicable in the growth technique of embedded or non-embedded SiGe outer, be not limited to this technique, in some technique, remove after source-drain area, the better cleaning performance that yet can reach by the technical solution used in the present invention at growing silicon carbide or other materials at source-drain area, therefore do not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (9)
1. a method of improving strained layer boundary defect, be applied in the preparation technology of semiconductor device, this semiconductor device comprises a substrate, described substrate forms active area and drain region, between source region and drain region, be positioned on described substrate and be formed with grid, described grid also forms sidewall and sidewall structure, it is characterized in that, comprises the following steps:
Adopt the first etching technics etching to remove the part that is positioned at substrate source region and drain region; Then clean go forward side by side an actor's rendering of an operatic tune body burn into overlay film and a baking process;
Proceed the second etching technics and remove the impurity at interface, etching source/drain region, the strained layer of finally growing in source region and drain region.
2. the method for claim 1, is characterized in that, described the first etching technics is plasma etching industrial, and adopts wet-etching technology to clean.
3. the method for claim 1, is characterized in that, passes into H when toasting
2.
4. the method for claim 1, is characterized in that, described the second etching technics is dry etch process.
5. method as claimed in claim 4, is characterized in that, adopting hydrogen chloride is that reacting gas carries out described dry etch process.
6. method as claimed in claim 5, is characterized in that, carries out described dry etch process under the environment of high-temperature low-pressure, in temperature, is 700～800 ℃, carries out etching under the condition that pressure is 100～600Torr.
7. the method for claim 1, is characterized in that, described strained layer is germanium-silicon layer.
8. method as claimed in claim 7, is characterized in that, adopts selective epitaxial growth process to prepare described germanium-silicon layer.
9. the method as described in claim 1～8 any one, is characterized in that, described method is applied to embedded or non-embedded SiGe outer growth technique.
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| CN201310554641.7A CN103646856A (en) | 2013-11-08 | 2013-11-08 | Method for improving strain-layer boundary defects |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887176A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for reducing source drain epitaxial growth defects |
| CN105097694A (en) * | 2014-05-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN105529266A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Improvement method for dislocation defects of embedded silicon-germanium epitaxy |
| CN106981451A (en) * | 2016-01-15 | 2017-07-25 | 沈阳硅基科技有限公司 | A kind of method of removal TM-SOI top layer defect silicons |
| US9953873B2 (en) | 2016-05-24 | 2018-04-24 | Globalfoundries Inc. | Methods of modulating the morphology of epitaxial semiconductor material |
| CN109119331A (en) * | 2017-06-23 | 2019-01-01 | 上海新昇半导体科技有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
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| US20090174005A1 (en) * | 2006-04-20 | 2009-07-09 | Texas Instruments Incorporated | Semiconductor device with gate-undercutting recessed region |
| CN102479753A (en) * | 2010-11-30 | 2012-05-30 | 台湾积体电路制造股份有限公司 | High performance strained source-drain structure and method of fabricating the same |
| US20120241815A1 (en) * | 2011-03-23 | 2012-09-27 | Samsung Electronics Co., Ltd | Semiconductor devices and methods of fabricating the same |
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2013
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| US20090174005A1 (en) * | 2006-04-20 | 2009-07-09 | Texas Instruments Incorporated | Semiconductor device with gate-undercutting recessed region |
| CN102479753A (en) * | 2010-11-30 | 2012-05-30 | 台湾积体电路制造股份有限公司 | High performance strained source-drain structure and method of fabricating the same |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887176A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for reducing source drain epitaxial growth defects |
| CN105097694A (en) * | 2014-05-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN105097694B (en) * | 2014-05-21 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN105529266A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Improvement method for dislocation defects of embedded silicon-germanium epitaxy |
| CN106981451A (en) * | 2016-01-15 | 2017-07-25 | 沈阳硅基科技有限公司 | A kind of method of removal TM-SOI top layer defect silicons |
| CN106981451B (en) * | 2016-01-15 | 2021-05-07 | 沈阳硅基科技有限公司 | Method for removing TM-SOI top layer silicon defect |
| US9953873B2 (en) | 2016-05-24 | 2018-04-24 | Globalfoundries Inc. | Methods of modulating the morphology of epitaxial semiconductor material |
| CN109119331A (en) * | 2017-06-23 | 2019-01-01 | 上海新昇半导体科技有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
| CN109119331B (en) * | 2017-06-23 | 2021-02-02 | 上海新昇半导体科技有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
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Application publication date: 20140319 |