CN103633993B - A kind of Programmable Logic Device comprising customizable fuse configuration module - Google Patents
A kind of Programmable Logic Device comprising customizable fuse configuration module Download PDFInfo
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- CN103633993B CN103633993B CN201310068752.7A CN201310068752A CN103633993B CN 103633993 B CN103633993 B CN 103633993B CN 201310068752 A CN201310068752 A CN 201310068752A CN 103633993 B CN103633993 B CN 103633993B
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Abstract
The invention discloses a kind of customizable Programmable Logic Device, its configuration bit is collectively formed by customizable static memory (SRAM) dispensing unit and the changeable customizable fuse dispensing unit for fuse bit control.When custom circuit is realized, according to certain flow process, by changing finite layer metal mask version, realize solidifying partial circuit function, the control bit of Key Circuit is switched to into fuse bit control simultaneously, keep for user to carry out voluntarily programming fuse configuration, finally realize subscriber's line circuit function, and while realize the security guarantee of subscriber's line circuit key message.The Programmable Logic Device of the present invention, inherit short general FPGA construction cycles, low cost, motility is strong, be capable of achieving the big advantage of circuit scale on the basis of, anti-single particle ability has obtained significant raising, while providing a kind of practicable solution for subscriber's line circuit safety.
Description
Technical field
It is the present invention relates to Programmable Logic Device technical field more particularly to a kind of comprising customizable fuse configuration module
Programmable Logic Device.
Background technology
With the development of integrated circuit technique, the appearance of field programmable gate array (FPGA), system has been provided the user
Programmable or reconfigurable ability, the signal processing and data processing circuit and system realization for many complexity provide new
Mentality of designing and verification method, while so that the design cycle significantly shorten, reduce design cost, reduce design risk, make new one
There is higher motility and higher adaptability for large scale integrated circuit, therefore be able in civilian and aerospace electronic system
Extensively apply.
But, with the increase of integrated level, impact of the space radiation environment to FPGA is increasingly severe.Exist in space
The electromagnetic radiation of the sun and particle radiation, its source include the radiation belt of the earth, solar cosmic ray and galactic comic ray.These are complicated
Ionizing radiation environment cause device performance parameter occur degenerate, even result in disabler, so as to have influence on circuit system
With the normal operation of whole machine so that circuit reliability weakens, shorten lifetime of system.Especially the single-particle inversion problem of FPGA is more
It is the bottleneck for affecting its AEROSPACE APPLICATION.
Most widely used at present is the general FPGA based on static memory SRAM structures, and the advantage of the device is system
Exploitation is flexible.But the feature contains a large amount of configuration static memories in also determining device simultaneously.These static memory numbers
Amount is big, it is weak to be distributed wide, anti-SEU abilities, is easiest to be written over, so as to cause disabler in spatial environmentss.Conventional solution
It is all passive error correction that method includes that triplication redundancy and configuration static memory circulation are cleaned, and these mode resource utilizations are low, and
Result in the in-orbit function momentary interruption of system.Additionally, aerospace system is frequently with the FPGA based on fuse technique, but this technique
One-off programming can only be realized, very flexible is designed and developed, high cost, and as its technique own characteristic is in scale and capacity
It is limited, there is significant limitation in application.
Fig. 1 shows schematic diagram of the current main flow based on the fpga chip 100 of SRAM type.It includes journey input/output mould
Block 110, programmable logic block 111, programmable storage 112 may be programmed multiplier 113, and 114 grade of programmable processor may be programmed
Resource, input and output pin 115 and each self-corresponding 120～124 configuration bit module of 110～114 modules.On chip after electricity, lead to
120～124 are read into usually through by the configuration data downloaded in nonvolatile memory such as EEPROM and Flash PROM in advance
Etc. in the static RAM SRAM in configuration module.The difference in functionality of chip is realized by these configuration bits.
Fig. 2 is the schematic diagram of the 6 pipe SRAM cell circuits 200 that the configuration bit module of the FPGA based on SRAM type is commonly used.It
Including the first access pipe 211A, the second access pipe 211Ab, and the cross coupled inverters being made up of reverser 215A and 215B
To 215.The paratope line bin and nbin of SRAM cell circuit 200 is coupled with accessing the respective drain electrode of pipe 211A and 211Ab.
Read/write Enable Pin wren of SRAM cell circuit 200 connects the grid of access pipe 211A and 211Ab respectively.When read/write Enable Pin
When wren is effective, paratope line bin and nbin are by accessing complementations of the pipe 211A and 211Ab to cross coupled inverters to 215
Node sd and nsd enter line access, correspondence output bout and nbout.
It is the schematic diagram of the common configuration dual-port SRAM cell circuit 300 of FPGA based on SRAM type in Fig. 3.It includes
First access pipe 311A, the second access pipe 311Ab, the 3rd access pipe 312B, the 4th access pipe 312Bb, and by reverser
The cross coupled inverters of 315A and 315B compositions are to 315.First couple of paratope line binA of dual-port SRAM cell circuit 300
It is coupled with accessing the respective drain electrode of pipe 311A and 311Ab with nbinA, second couple of paratope line binB and binB are coupled with depositing
Take the respective drain electrode of pipe 312B and 312Bb.First read/write Enable Pin wrenA of dual-port SRAM cell circuit 300 is connect respectively deposits
The grid of pipe 311A and 311Ab is taken, the second read/write Enable Pin wrenB connects the grid of access pipe 312B and 312Bb respectively.When read/
Write Enable Pin wrenA it is effective when, paratope line binA and nbinA by access pipe 311A and 311Ab to cross coupled inverters
Complementary node sd [0] and nsd [0] to 315 enters line access；When read/write Enable Pin wrenB is effective, paratope line binB and
NbinB by access pipe 312B and 312Bb to cross coupled inverters to 305 complementary node sd [0] and nsd [0] deposit
Take.
Based on primary particle inversion resistant consideration, propose in the industry the method for circuit is realized by customizing FPGA, customization FPGA is
After the completion of user's application and development, by configuration static memory state solidifications whole in general FPGA, by former logical in modification
It is with one layer or the finite layer mask plate of FPGA, configuration bit is straight with fixed high and low level according to the code stream of practical application circuit
Connect in succession, realize circuit function, solve from source based on the primary particle inversion resistant problems of the general FPGA of SRAM structures.Customization
FPGA adopts common CMOS process, and user's code stream is fully cured in the design, without the need for the data loading after upper electricity, eliminates code
Stream is subject to the probability stolen in loading procedure.But this mode is completely exposed due to physical arrangement, thus there is production ring
The danger of design is built or dialysed by reversely extracting to the mistake of section.And circuit safety for user particularly AEROSPACE APPLICATION extremely
Close important, especially key modules include that the safety of the information such as system key is directly connected to the safety of whole system in circuit
Property.
The content of the invention
In order to solve the above problems, i.e., on the basis of keeping chip jumbo, chip anti-single particle ability is improved, while
Allow user to retain crucial circuit information again, to ensure the safety of circuit, the present invention propose it is a kind of support customization mode and
Key configuration position can pass through fuse technique and realize providing user the new FPGA device structure of autonomous programming.That is circuit in the devices
In structure, most of configuration bit can be realized by customizing, and key message is configured by fuse-wires structure.
When device is used, by specified layout, Key Circuit is placed on specific position, while configuration bit stream is carried out
Distinguish, and the different modes by custom-modification finite layer mask plate and programming fuse bit are configured.
The present invention proposes several physical circuit implementations and control flow of the device simultaneously, realizes application electricity with final
Road function.
Application circuit is realized by this structure devices, with following features compared with existing several implementations.Phase
Than in ASIC (Application Specific Integrated Circuit), the design cycle is short, exploitation motility is high, wind
Danger is low；Compared to FPGA of the tradition based on SRAM structures, especially anti-single particle ability is higher for Flouride-resistani acid phesphatase, and reliability is high；Compare
In the FPGA based on fuse technique, achievable circuit scale is bigger, and performance is more excellent；Realize compared to single employing customization mode
FPGA, its circuit information need not inform foundry vendor, and subscriber's line circuit is safe, and autonomous controllability is strong, has been suitably applied height
The application circuit field of confidentiality demand.
Description of the drawings
Fig. 1 is the common fpga chip schematic diagram based on SRAM type；
Fig. 2 is the schematic diagram of 6 common pipe SRAM cell circuits；
Fig. 3 is the schematic diagram of common dual-port SRAM cell circuit；
Fig. 4 is 2 in the present invention based on 6 pipe sram cellsnThe customizable fuse configuration module in position；
Fig. 5 is 2 in the present invention based on dual-port sram cellnThe customizable fuse configuration module in position；
Fig. 6 is based on customizable fuse configuration bit circuit realiration flow chart in the present invention；
Fig. 7 is 4 fuse configuration modules and to arrange matching somebody with somebody for output in order by 4 common configuration units in the present invention
The exemplary plot of set array；
Fig. 84 fuse configuration modules and is exported by alternating sequence by 4 common configuration units in the present invention
Configuration bit array exemplary plot；
Fig. 9 is customizable fuse configuration bit layout type exemplary plot in the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
The present invention proposes a kind of customizable Programmable Logic Device, and which is supported that custom model, i.e. user specify and can compile
The concrete configuration of the programmable resource of journey logic circuit realizes that then the specific configuration information by specified by manufacturer is by user is solid
Change in common customizable configuration module；In addition, the key configuration position of customizable Programmable Logic Device proposed by the present invention
Can be realized by non-volatile type memorizers such as fuse, antifuse, Flash, be specified and solidified in customized module described by user
The specific configuration information of key configuration position.
A kind of customizable Programmable Logic Device proposed by the present invention, which includes that crucial position configuration module and common position are matched somebody with somebody
Module is put, the crucial position configuration module is used for the configuration information for storing programmable resource key position in Programmable Logic Device,
And control the configuration of programmable resource key position in the Programmable Logic Device；And the common position configuration module is used to store
The configuration information of the common position of programmable resource in Programmable Logic Device, and programmable resource is general in controlling Programmable Logic Device
The configuration of logical position.
In a preferred embodiment of the invention, crucial position configuration module realized by customizable fuse configuration module, and
Common position configuration module is made up of the configuration SRAM cell circuit including static memory SRAM.
Fig. 4 shows the schematic diagram of customizable fuse configuration module in the preferred embodiment of the present invention.The FPGA electricity
The customizable fuse configuration module on road realizes that circuit 400 includes：Configuration SRAM array module 410, configuration mode selecting module
421 and fuse bit generation module 430.SRAM array module 410 is configured wherein by 2nIndividual configuration SRAM cell circuit 416 is constituted,
Configuration SRAM cell circuit 416 includes the first access pipe 411A, the second access pipe 411Ab, the first reverser 415A, and second
Reverser 415B.Configuration mode selecting module 420 by 421～42m, totally 2nIndividual metal-oxide-semiconductor composition.Fuse bit generation module 430 is wrapped
Include control circuit 431, predecode circuit 433, array of fuses 432 and decoding circuit 434.
The bit line bin [0] of configuration SRAM cell circuit 416 is connected to the drain electrode of the first access pipe 411A, the first access pipe
The source electrode of 411A connects the outfan of the input of the first phase inverter 415A and the second phase inverter 415B.Configuration SRAM cell circuit
416 paratope line nbin [0] is connected to the drain electrode of the second access pipe 411Ab, and it is anti-that the second source electrode for accessing pipe 411Ab connects first
The input of the outfan of phase device 415A and the second phase inverter 415B.Read/write Enable Pin wren of configuration SRAM cell circuit 416
[0] it is connected respectively to the grid of the access pipe 411Ab of the first access pipe 411A and second.When read/write Enable Pin wren [0] effectively
When, bit line bin [0] and its corresponding paratope line nbin [0] are respectively by the first access pipe 411A and the second access pipe 411Ab
Line access is entered to complementary node sd [0] and nsd [0] of 415A and 415B to cross coupled inverters.
Bout [0] is exported as configuration bit, is connected on the programmable resource of the Programmable Logic Device and is configured
Control, to realize circuit function.
Control circuit 431 by the input sense_pulse of fuse bit generation module 430, prog_fuse_en,
The signal is input into by fuse_en is controlling the mode of operation of fuse bit generation module 430.
When prog_fuse_en is high level, and fuse_en is high level, fuse bit generation module 430 is made into programming
Energy pattern, fu_sc provide high level signal source for fuse bit programming；When prog_fuse_en is low level, fuse_en is low
During level, fuse bit generation module 430 enters reading mode, when the trailing edge of sense_pulse signals arrives, exports fuse_out
Effectively, will array of fuses 432 storage value output.
N bit address signal addr [n-1: 0] and fu_sc signals are sent into predecode circuit 433 and carry out pretreatment, and by solution
Code circuit 434 completes the decoding to address, and realizes the addressing access to memory element in array of fuses 432, and which corresponding 2n
Position storage element is output as fuse_out [2n-1∶0]。
Configuration mode selecting module 420 by 421～42m, totally 2nIndividual metal-oxide-semiconductor composition, input signal mode_sel connect this
The grid of a little metal-oxide-semiconductors, by controlling the signal, controls whether the output fuse_out [2 of fuse bit generation module 430n-1∶
0] signal delivers to respective nodes sd [2 of configuration SRAM array module 410 respectivelyn-1∶0].To mode_sel signals be 0 when, match somebody with somebody
Module 400 is put into general FPGA configuration modes, its output bout [2n- 1: 0] i.e. node sd [2n- 1: 0] current potential is by configuring
2 in SRAM array module 410nThe storage content control of individual configuration SRAM cell circuit 416；When mode_sel signals are 1, configuration
Module 400 enters customization FPGA fuse configuration modes, its output bout [2n- 1: 0] by the output of fuse bit generation module 430
fuse_out[2n- 1: 0] control.
Under above-mentioned FPGA configuration modes, user is by configure in SRAM array module 410 SRAM cell circuit 416 to configuring
Content be programmed debugging, with determine the programmable resource in final programmable circuit key position configuration information；Remaining
Configuration bit information may be notified that foundry vendor, by finite layer mask plate is changed on the basis of common FPGA, realize custom circuit.
Foundry vendor consigns to device after user, and user can be fixed to fire in the fuse by the configuration information of final crucial position
In the array of fuses of position generation module, and under custom model, realized using the programmable resource of the programmable circuit corresponding
Function.
2nThe 2 of individual configuration SRAM cell circuit 416nTo cross coupled inverters to 415A and 415B corresponding to 2nIndividual section
Point sd [2n- 1: 0] 2nIndividual complementary node nsd [2n- 1: 0] in addition to level is negated, with 2nIndividual node sd [2nCan -1: 0] wait
Effect is replaced, and this 2nIndividual complementary node nsd [2n- 1: 0] 2 are providednIndividual configuration bit nbout [2n- 1: 0], it is connected to programmable patrolling
The programmable resource of circuit is collected, can be with equivalence replacement 2nIndividual node sd [2n- 1: 0], with 2 with configuration mode selecting module 420n
Individual output is connected, and realization output is configuration status by the memory element in configuring SRAM cell circuit 416 or array of fuses 433
The selection of control.
Fig. 5 is comprising 2nThe new arrangement module principle of individual 515 gate array 516 of user's dual-port sram cell is illustrated
Figure.Including：Configuration SRAM array module 510, configuration mode selecting module 521, fuse bit generation module 530.Configuration SRAM battle arrays
Row module 510 is by 2nIndividual dual-port configuration SRAM cell circuit 516 is constituted；Configuration mode selecting module 520, fuse bit produces mould
Block 530 is identical with the corresponding module in circuit 400.
Dual-port SRAM cell circuit 516 includes the first access pipe 511A, the second access pipe 511Ab, the 3rd access pipe
512B, the 4th access pipe 512Bb, the first reverser 515A, and the second reverser 515B.Dual-port SRAM cell circuit 516
First pair of paratope line binA [0] and nbinA [0] be coupled with the accesses of the first access pipe 511A and second pipe 511Ab each
Drain electrode, second pair of paratope line binB [0] and nbinB [0] are coupled with the 3rd access pipe 512B and the 4th access pipe 512Bb
Respective drain electrode.The source electrode of the first access pipe 511A connects the output of the input and the second reverser 515B of the first reverser 515A
End；The source electrode of the second access pipe 511Ab connects the outfan and the input of the second reverser 515B of the 515A of the first reverser.The
The source electrode of three access pipe 512B connects the outfan of the input and the second reverser 515B of the first reverser 515A；4th access pipe
The source electrode of 512Bb connects the input of the outfan of the first reverser 515A and the second reverser 515B.2nIndividual dual-port SRAM is mono-
The 2 of first circuit 516nIndividual first read/write Enable Pin wrenA [2n- 1: 0] it is corresponding respectively to be connected to 2nIndividual dual-port sram cell electricity
The grid of the first access pipe 511A on road 516 and the second access pipe 511Ab, 2nIndividual second read/write Enable Pin wrenB [2n-1∶0]
It is corresponding respectively to be connected to 2nThe grid of the 3rd access pipe 512B of individual dual-port SRAM cell circuit 516 and the 4th access pipe 512Bb
Pole.When m the first read/write Enable Pin wrenA [2n- 1: 0] when difference is effective, paratope line binA [2n- 1: 0] and nbinA [2n-
1: 0] 2 are passed through respectivelynTo the first access pipe 511A and the second access pipe 511Ab to cross coupled inverters to 515A's and 515B
Node sd [2n- 1: 0] and its 2nIndividual complementary node enters line access；When 2nIndividual second read/write Enable Pin wrenB [2n- 1: 0] respectively
When effectively, paratope line binB and nbinB pass through 2 respectivelynTo the 3rd access pipe 512B and the 4th access pipe 510Bb to intersecting coupling
Close reverser to 515A and 515B 2nIndividual node sd [2n- 1: 0] and its 2nIndividual complementary node nsd [2n- 1: 0] enter line access.
In configuration module 500, configuration SRAM array module 510, configuration mode selecting module 521, fuse bit generation module
Annexation and operation principle between 530 is with circuit 400.
2nThe 2 of individual configuration dual-port SRAM cell circuit 516nCross coupled inverters are corresponded to 515A and 515B
2nIndividual node sd [2n- 1: 0] 2nIndividual complementary node nsd [2n- 1: 0] in addition to level is negated, with 2nIndividual node sd [2n-1∶0]
2 can be provided with equivalence replacementnIndividual configuration bit nbout [2n- 1: 0] be connected to the programmable resource of logic circuit, can with equivalence replacement with
The 2 of configuration mode selecting module 520nIndividual output is connected, and realizes that output is configuration status by configuring dual-port SRAM cell circuit
516 or array of fuses 533 in memory element control selection.
In a preferred embodiment, the configuration mode selecting module in Fig. 4 and Fig. 5 in 400/500 circuit of configuration module
420/520 can also remove, i.e., do not carry out model selection, during into custom model, directly by changing under general mode
The finite layer mask plate of FPGA, by the output fuse_out [2 of fuse bit generation module 430/530n- 1: 0] signal passes through metal
Line is directly connected to corresponding node sd [2n- 1: 0], configuration control is carried out to the function of circuit.The method can reduce configuration
Control metal-oxide-semiconductor number is selected, but cannot be switched between general mode and custom model.
In a preferred embodiment, the configuration SRAM array module in Fig. 4 and Fig. 5 in 400/500 circuit of configuration module
410/510 can also remove in the lump with configuration mode selecting module 420/520, when application circuit is realized in customization, directly by fuse
The output of position generation module 430/530 is connected to the configuration end of part programmable logical resource, and other common SRAM configuration bits
Realize jointly the control to circuit function.
Access pipe in Fig. 4 and Fig. 5 can carry out replaces realization identical function by gated devices such as transmission gates.Work(i.e. of the invention
By the concrete structure of the switch for being adopted and can not realize that logic is limited.And the metal-oxide-semiconductor in the configuration mode selecting module
Also can be realized by other any switching selector parts.
Fuse bit generation module by user's voluntarily programming Partial key configuration bit information, its output connection FPGA electricity
The control end of the programmable resource on road, with the different function of control realization.In Fig. 4 and Fig. 5, fuse bit generation module is merely illustrative
Figure, can pass through remaining control signal or control mode is realized, it is also possible to which by such as antifuse, flash etc., other are non-volatile
Memorizer is realized.Function i.e. of the invention is not produced and control mode by adopted configuration bit, and implements technique
Limit.
Fig. 6 is the embodiment flow chart carried out according to the present invention.The step of carrying out needed for which includes：
Step 601, user carry out application circuit exploitation debugging on FPGA, are connected up by specified layout, it would be desirable to user
The key message circuit for voluntarily configuring specifies the resource by being controlled by fuse configuration bit to realize；
Step 602, whole code stream informations are derived, and the code stream that will be configured by common SRAM using code stream isolation technics
Cfg_datal and the code stream cfg_data2 controlled by fuse configuration module are distinguished, and are stored in different files respectively；
Step 603, according to derive code stream cfg_datal destination files, produce masked edit program script；
Step 604), be programmed using masked edit program script, generate new replacement mask layer, cured portion user set
Meter；
Step 605, finite layer mask layer replacement is carried out, synthesize new flow mask；
Step 606, using new flow mask flow again；
Step 607, on new chip, according to cfg_data2, programming is voluntarily carried out to fuse configuration module by user；
Step 608, end user carry out circuit test.
Common position configuration module in the preferred embodiment of the present invention in programmable logic cells can be by customizable common position
Configuration sram cell is realized.
In a preferred embodiment of the invention, shown in Fig. 7 and Fig. 8, customizable configuration module include one 4 such as figure
Array 711/811 that customizable fuse configuration module described in 4 or Fig. 5 is constituted and mono- by 4 customizable common positions configuration SRAM
Structure chart as a example by being used in conjunction with of common position configuration module that unit 710/810 is constituted, which illustrate crucial position configuration module and
The different modes of emplacement of common position configuration module.Wherein customizable common position configuration sram cell 710/810 includes commonly
Configuration sram cell 721/821 and customization source 722/822, and described common its structure of configuration sram cell 721/821 can
With identical with the configuration SRAM cell circuit 416 or 415 in the customizable fuse configuration module, as shown in Figures 4 and 5, depending on
Source processed 722/822 is the offer source of the height fixed level under custom model.Customizable common position configures sram cell 710/
810 final outputs such as sram_out [0] signal is controlled by common configuration sram cell 721/821 in the configuration mode, fixed
Controlled by customization source 722/822 under molding formula, i.e., after user determines the implementing of programmable resource, according to described concrete
Realize that the low and high level that customization source 722/822 provides is connected on the common configuration position of the programmable resource.Customizable fuse
The final output of configuration module 711/811 such as sram_out [7] signal is in the configuration mode by customizable fuse configuration module
Configuration SRAM cell circuit control, under custom model by array of fuses output control.
The output of customizable common position configuration sram cell 710/810 and the output of fuse configuration module 711/811 are altogether
With the control bit sram_out that composition is final.The composition order of sram_out arbitrarily can be put, and in such as Fig. 7,4 customizable general
The logical output of position configuration sram cell 710 and the output of customizable fuse configuration module 711 constitute sequence sram_out in order
[7: 0], and in fig. 8,4 customizable common positions configure output and the customizable fuse configuration module 811 of sram cells 810
Output press alternating sequence constitute sequence sram_out [7: 0].Certainly, the visual actual demand of its modes of emplacement is selected, configuration bit
The different and different modes of emplacement of number belongs to scope of the presently claimed invention.
Fig. 9 illustrates Crestor in the present invention by taking the programmed logical module in the fpga chip 100 based on SRAM type as an example
The topology layout mode of fuse configuration module processed.Programmed logical module resource 900 in FPGA is general by switch enclosure 910, company
Connect box 911, multi-path choice module 912 and logical block cluster 913 and respective configuration module composition.Wherein, logical block
Cluster 913 is typically made up of multiple logical blocks 920 and logic control element 921.Logical block 920 in main flow fpga chip is led to
The normal lut932 containing one or more look-up tables, one or more depositors dff933, its configuration bit may be selected to carry using the present invention
For customizable fuse configuration module 931, to realize being controlled the function of look-up table 932 and depositor 933, remaining configuration
Position can be provided by common customizable SRAM configuration modules 930.Different logical blocks 920 can configure control mode can not
Together.Equally, as shown in figure 9, logic control element 921 can also be selected by customizable fuse configuration module 931 to therein
Key modules, the such as module such as carry control unit 934 are controlled.
As shown in figure 9, customizable fuse configuration module 931 is equally applicable to controlling switch box 910, connection box 911, multichannel
The configuration of the modules such as selecting module 912.In the same manner, customizable fuse configuration module except can be used for control programmable logic block, its
It is equally applicable to control the input/output module 110 shown in Fig. 1, programmable storage 112 may be programmed multiplier 113, can
114 grade other programmable resources of programmed process device.
As the area consumption of customizable fuse configuration module is bigger than common SRAM configuration modules, can consider
Equilibrium between performance area and user security requirement, completely or partially using customizable molten in configuration module in the chips
Silk configuration module.
The present invention is not limited by and circuit the is adopted logical form limited by the specific implementation method of circuit, for example,
All of bottom circuit can be the CMOS technology of standard or other techniques.
Particular embodiments described above, has been carried out to the purpose of the present invention, technical scheme and beneficial effect further in detail
Describe bright, the be should be understood that specific embodiment that the foregoing is only the present invention in detail, be not limited to the present invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., should be included in the guarantor of the present invention
Within the scope of shield.
Claims (7)
1. a kind of customizable Programmable Logic Device, which includes crucial position configuration module and common position configuration module, the pass
Key mapping configuration module is used for the configuration information for storing programmable resource key position in Programmable Logic Device, and can compile described in controlling
The configuration of programmable resource key position in journey logic circuit；The common position configuration module is used to store in Programmable Logic Device
The configuration information of the common position of programmable resource, and control the configuration of the common position of programmable resource in Programmable Logic Device；
The crucial position configuration module includes nonvolatile memory array, and which can in being used to store the Programmable Logic Device
The configuration information of programming resource key position；
The crucial position configuration module also includes static memory cell array, and which is used to store in the Programmable Logic Device
The configuration information of programmable resource key position, and programmable resource is closed in controlling the Programmable Logic Device in the configuration mode
The configuration of key mapping；And the nonvolatile memory array is may be programmed during the Programmable Logic Device is controlled under custom model
The configuration of resource key position；
The common position configuration module includes static memory cell and provides the customization source of fixed low and high level, the common position
Static memory cell in configuration module is used for the configuration for storing the common position of programmable resource in the Programmable Logic Device
Information, and be used in the configuration mode controlling the configuration of the common position of programmable resource in the Programmable Logic Device；And it is described
It is described to control that customization source directly provides fixed low and high level to the output of the common position configuration module under custom model
The configuration of the common position of programmable resource in Programmable Logic Device.
2. customizable Programmable Logic Device as claimed in claim 1, it is characterised in that the Programmable Logic Device is also
Including configuration mode selecting module, which is used to select the crucial position configuration module to be operated in configuration mode or custom model.
3. customizable Programmable Logic Device as claimed in claim 1, it is characterised in that
The output of the crucial position configuration module constitutes sequence by different order with the output of the common position configuration module, respectively
The configuration of programmable resource key position and common position in control Programmable Logic Device.
4. customizable Programmable Logic Device as claimed in claim 1, it is characterised in that
The static memory cell include cross coupling inverter, door control unit, a pair of Complementary input structure bit lines and at least one pair of
Complementary output node, wherein the pair of Complementary input structure bit line is equally anti-to cross-couplings under the control of the door control unit
Phase device writes data, the data that described at least one pair of complementary output node is used in equally output cross coupled inverters.
5. customizable Programmable Logic Device as claimed in claim 2, it is characterised in that configuration mode selecting module is by more
Individual switch selecting unit is constituted, and under the control of mode select signal, the multiple switch of the configuration mode selecting module is selected
During unit selects the output of array of fuses in the crucial position configuration module or the crucial position configuration module respectively, static state is deposited
The configuration of programmable resource crucial position of the output of reservoir to control the Programmable Logic Device.
6. customizable Programmable Logic Device as claimed in claim 1, it is characterised in that
The nonvolatile memory array includes array of fuses, antifuse array and flash memory array.
7. a kind of method for customizing of Programmable Logic Device as claimed in claim 1, the method include：
Step 1, the Programmable Logic Device is switched to into configuration mode, can be compiled described in the crucial position configuration module control
In journey logic circuit, the configuration of programmable resource key position, controls the Programmable Logic Device by the common position configuration module
The configuration of the common position of middle programmable resource, to debug the Programmable Logic Device, and can in finally determining Programmable Logic Device
The configuration information of programming resource, the configuration information of the programmable resource include that confidence is matched somebody with somebody in crucial position configuration information and common position
Breath；
Step 2, the customization source in the common position configuration module is connected to into programmable resource in the Programmable Logic Device
Common position, provides fixed low and high level from the customization source to the common position of programmable resource in the Programmable Logic Device,
And the low and high level of the fixation is then corresponding with the common position configuration information；
Step 3, the Programmable Logic Device is switched to into custom model, by the configuration information of programmable resource key position
It is solidificated in the nonvolatile memory array in the crucial position configuration module, it is direct by the nonvolatile memory array
Control the configuration of programmable resource key position in the Programmable Logic Device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Non-Patent Citations (1)
| Title |
|---|
| 基于扫描链的FPGA可编程逻辑模块测试;周发标等;《微电子学与计算机》;20120428;第29卷(第2期);第48-53页 * |
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