CN105260679B - A kind of asic chip implementation method and asic chip - Google Patents
A kind of asic chip implementation method and asic chip Download PDFInfo
- Publication number
- CN105260679B CN105260679B CN201510645938.3A CN201510645938A CN105260679B CN 105260679 B CN105260679 B CN 105260679B CN 201510645938 A CN201510645938 A CN 201510645938A CN 105260679 B CN105260679 B CN 105260679B
- Authority
- CN
- China
- Prior art keywords
- look
- antifuse
- netlist
- table standard
- programming control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 20
- 230000006870 function Effects 0.000 claims abstract description 20
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000003860 storage Methods 0.000 abstract description 5
- 230000006378 damage Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002730 additional effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009659 non-destructive testing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The embodiment of the invention discloses a kind of asic chip implementation method and asic chip, including：Using RTL code corresponding to asic chip as input, with logic synthesis tool by chip functions logic synthesis into antifuse look-up table standard block netlist；By all antifuse look-up table standard blocks in the netlist, increase unified programming Control circuit；By the netlist after increase programming Control circuit, the layout design flow based on routine draws the GDS domains for meeting target process, and manufactures silicon according to the GDS domains；Programming Control interface is used as using the input of the programming Control circuit of the silicon, all antifuse look-up table standard blocks in the silicon are programmed, this mode being programmed after silicon to antifuse look-up table standard block of the present embodiment, ensure that the core logic of chip not by the interference or destruction of wooden horse circuit, ensures that the safety storage of core private data is not stolen by rear gate circuit.
Description
Technical field
The present invention relates to IC design field, more specifically to a kind of asic chip implementation method and ASIC
Chip.
Background technology
Semi-custom design flow based on standard block is current ASIC (Application Specific
Integrated Circuit：Special chip) mainstay technology.In the design cycle, chip designer uses hardware
Description language design chips, i.e., be modeled to chip functions, then with the Automation Design software by design code synthesis into
Standard cell circuit, and then standard cell circuit is converted into what can be manufactured under corresponding making technology by the design of physics rear end
GDS domains, finally produce chip by foundries.Although the asic chip designing technique for being currently based on CMOS standard blocks obtains most
Extensive use, but there is also the problem of following security correlation.It is first, existing based on CMOS standard blocks for one
For asic chip, it is difficult to confirm that the logic circuit of chip is complete really with initial designs by the small non-destructive testing technology of expense
Unanimously, i.e., asic chip whether there is unexpected logic circuit, such as back door or wooden horse after can not confirming silicon.Second, chip is set
Meter person or IP (Intellectual Properpty：Refer to one party provide, form be logic unit, chip design can
Reuse module) core designer technically can not thoroughly protect knowledge-product, such as imitator to be reduced by reverse engineering
The logic circuit of asic chip, the unauthorized use of IP kernel supplier also uncontrollable IP kernel, i.e., uncontrollable IP kernel user
Produce and exceed limited number of chip.
Therefore, how to ensure that the core logic of chip not by the interference or destruction of wooden horse circuit, ensures core private data
Safety storage without being stolen by rear gate circuit be to need to solve the problems, such as now.
The content of the invention
It is an object of the invention to provide a kind of asic chip implementation method and asic chip, to ensure that the core of chip is patrolled
Collect not by the interference or destruction of wooden horse circuit, ensure the safety storage of core private data without being stolen by rear gate circuit.
To achieve the above object, the embodiments of the invention provide following technical scheme：
A kind of asic chip implementation method, including：
Using RTL code corresponding to asic chip as input, with logic synthesis tool by chip functions logic synthesis into
Antifuse look-up table standard block netlist；
By all antifuse look-up table standard blocks in the netlist, increase unified programming Control circuit；
By the netlist after increase programming Control circuit, the layout design flow based on routine, which is drawn, meets target process
GDS domains, and silicon is manufactured according to the GDS domains；
Using the input of the programming Control circuit of the silicon as programming Control interface, to the institute in the silicon
There is antifuse look-up table standard block to be programmed.
Preferably, using the input of the programming Control circuit of the silicon as programming Control interface, to the silicon core
All antifuse look-up table standard blocks in piece are programmed, including：
Programming enable signal is arranged to low level, program voltage is arranged to high-breakdown-voltage；
With the address of the wordline address decoder in the programming Control circuit, looked into as the target antifuse for needing to program
Look for the line identifier of table standard block；With the address of the bit line address decoder in the programming Control circuit, as the target
The row mark of antifuse look-up table standard block；
According to the line identifier and the row mark, select to need to compile in the antifuse look-up table standard block netlist
The target antifuse look-up table standard block of journey；
The programming enable signal is arranged to high level, and maintains preset time, by the antifuse look-up table standard
Antifuse fusing in unit.
A kind of asic chip, including：
All antifuse in antifuse look-up table standard block netlist, with the antifuse look-up table standard block netlist
The connected programming Control circuit of look-up table standard block；
Wherein, the antifuse look-up table standard block netlist is by using RTL code corresponding to asic chip as defeated
Enter, with logic synthesis tool by chip functions logic synthesis into；And with the input of the programming Control circuit of the silicon
End is used as programming Control interface, and all antifuse look-up table standard blocks in the silicon are programmed.
Preferably, the programming Control circuit includes：
The wordline address decoder being connected with all antifuse look-up table standard blocks in the netlist；
The bit line address decoder being connected with all antifuse look-up table standard blocks in the netlist；
The big resistance being connected with all antifuse look-up table standard blocks in the netlist；
Wherein, the other end of the big resistance is connected with program voltage input；
All antifuse look-up table standard blocks in the netlist are connected with programming enabled input signal.
Preferably, the big resistance and the AF transistors in all antifuse look-up table standard blocks in the netlist
Grid is connected.
Preferably, the wordline enable signal that the wordline address decoder for decoding goes out, it is and all anti-molten in the netlist
Silk look-up table standard block is connected by row.
Preferably, the bit line enable signal that the bit line address decoder for decoding goes out, it is and all anti-molten in the netlist
Silk look-up table standard block is in parallel.
By above scheme, a kind of asic chip implementation method provided in an embodiment of the present invention and asic chip, bag
Include：Using RTL code corresponding to asic chip as input, with logic synthesis tool by chip functions logic synthesis into antifuse
Look-up table standard block netlist；By all antifuse look-up table standard blocks in the netlist, increase unified programming Control
Circuit；By the netlist after increase programming Control circuit, the layout design flow based on routine draws the GDS versions for meeting target process
Figure, and silicon is manufactured according to the GDS domains；Programming Control is used as using the input of the programming Control circuit of the silicon
Interface, all antifuse look-up table standard blocks in the silicon are programmed.
Because anti-fuse circuit does not have invertibity after programming, and it can only program once, even if with reverse engineering
Also the state of anti-fuse circuit after programming can not be cracked, therefore based on the standard block of antifuse disposable programmable look-up table
Circuit and based on this standard block structure asic chip there is very high security feature.It is in particular in：IP suppliers can
Fundamentally to protect intellectual property based on the method, without being programmed after the silicon of IP suppliers, IP user can not obtain complete work(
Can, function can not be also cracked, the chip more than authorized quantity can not be produced.Due to before chip manufacturing comes out, decoring
Other people or entity do not grasp the complete function of chip outside piece designer, therefore are difficult the injection needle in chip manufacturing proces
The security control logic for making chip to gate circuit after the wooden horse of property fails, or leakage chip internal status information.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of asic chip implementation method flow chart disclosed in the embodiment of the present invention；
Fig. 2 is programming Control electrical block diagram disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The embodiment of the invention discloses a kind of asic chip implementation method and asic chip, to ensure the core logic of chip
Not by the interference or destruction of wooden horse circuit, ensure the safety storage of core private data without being stolen by rear gate circuit.
Referring to Fig. 1, a kind of asic chip implementation method provided in an embodiment of the present invention, including：
S101, using RTL code corresponding to asic chip as input, it is with logic synthesis tool that chip functions logic is comprehensive
Synthesize antifuse look-up table standard block netlist；
Specifically, it should be noted that the antifuse look-up table standard block netlist in S101 is only combinational logic netlist,
Used trigger and latch are still the logic unit of conventional cmos structure, this part trigger and latch in chip
Logic unit does not have additional effect for the implementation process of asic chip.
Here, all antifuse look-up table standard blocks are designated as AF respectively0,AF1,…,AFN-1, wherein N is antifuse
The sum of look-up table standard block, the input signal quantity of N number of antifuse look-up table standard block is respectively I0,I1,…,IN-1,
Output signal quantity is respectively O0,O1,…,ON-1, the wordline enable signal quantity W of each antifuse look-up table standard block0,
W1,…,Wi,…,WN-1, wherein0≤i≤N；Each antifuse look-up table standard block neutrality line enable signal number
Measure as B0,B1,…,BN-1, wherein Bi=Oi, 0≤i≤N.Antifuse programmable unit group in antifuse look-up table standard block
It is made into WiRow BiThe two-dimensional structure of row, 0≤i≤N.The state of each antifuse programmable unit is designated as S respectivelyi,j,k, wherein 0≤
I ＜ N, 0≤j<Wi, 0≤k<Bi, Si,j,kValue be 0 or 1；If Si,j,kFor 0, then need to be programmed anti-fuse cell
Fuse, if Si,j,kFor 1, then without being programmed to anti-fuse cell.
S102, by all antifuse look-up table standard blocks in the netlist, increase unified programming Control circuit；
Specifically, increase unified programming Control circuit for all antifuse look-up table standard blocks, for after silicon
Each antifuse look-up table standard block is programmed.
The programming Control circuit structure diagram provided referring to Fig. 2, the present embodiment, the main of programming Control circuit are included wordline
Location decoder 100 and bit line address decoder 200, and shared big resistance RBLK, program voltage input VP, programming are enabled defeated
Enter signal PGM.PGM is connected to all antifuse look-up table standard blocks, and RBLK one end is connected to VP, and the other end is connected to
The AF-G ends of all antifuse programmable units.
In programming mode, PGM is high level, and VP is can be with the high voltage of breakdown antifuse transistor；In normal work
During pattern, PGM is low level, and VP is the normal working voltage of transistor.Wordline address decoder needs to decode out sum for W's
Wordline enable signal, whereinWordline enable signal quantity in i.e. all antifuse look-up table standard blocks
Maximum；Bit line address decoder needs to decode out the bit line enable signal that sum is B, whereinWordline
The address of location decoder is designated as WA, and WA bit wide is X, X=log2W,The address of bit line address decoder
BA is designated as, BA bit wide is Y, Y=log2B,
Antifuse look-up table standard block AFiMiddle jth row wordline enable signal is connected to the jth row of wordline address decoder
Output, wherein 0≤i<N, 0≤j<Wi；B output of bit line address decoder is total with all antifuse look-up table standard blocks
Common B bit line enable signal is connected one by one.The wordline enable signal of each antifuse look-up table standard block is connected by row, each
The bit line of antifuse look-up table standard block is in parallel, i.e., forms two-dimensional structure in the way of W rows B is arranged.Translated according to wordline address
Some specific antifuse programmable unit may be selected in the combination of the address of code device and the address of bit line address decoder, is compiling
It can be programmed under journey pattern and antifuse fuses.The logic of wordline address decoder and bit line address decoder electricity
Road is realized using conventional CMOS standard blocks, rather than antifuse look-up table standard block is realized.
S103, the netlist after programming Control circuit will be increased, the layout design flow based on routine draws and meets target work
The GDS domains of skill, and silicon is manufactured according to the GDS domains；
Specifically, in the present embodiment to insert the netlist after programming Control circuit as input, the ASIC based on routine
Rear end design cycle and eda tool design and the GDS domains for realizing chip；Then according to asic chip manufacturing process, according to GDS
Domain manufactures silicon；
S104, using the input of the programming Control circuit of the silicon as programming Control interface, to the silicon
In all antifuse look-up table standard blocks be programmed.
Specifically, after silicon is produced, by the programming Control interface of chip, antifuse all in piece is looked into
Look for table programming unit to be programmed, be finally completed the realization of chip logic function.
Preferably, using the input of the programming Control circuit of the silicon as programming Control interface, to the silicon core
All antifuse look-up table standard blocks in piece are programmed, including：
Programming enable signal is arranged to low level, program voltage is arranged to high-breakdown-voltage；
With the address of the wordline address decoder in the programming Control circuit, looked into as the target antifuse for needing to program
Look for the line identifier of table standard block；With the address of the bit line address decoder in the programming Control circuit, as the target
The row mark of antifuse look-up table standard block；
According to the line identifier and the row mark, select to need to compile in the antifuse look-up table standard block netlist
The target antifuse look-up table standard block of journey；
The programming enable signal is arranged to high level, and maintains preset time, by the antifuse look-up table standard
Antifuse fusing in unit.
Specifically, S104 can be：
1st, it is low level to put programming enable signal PGM, and VP is high-breakdown-voltage；
The 2nd, the address of wordline address decoder and bit line address decoder is set to gate the anti-fuse cell for needing to program,
Concrete mode is：If antifuse look-up table standard block AFiIn some antifuse programmable unit value Si,j,kFor 0, that is, need
Gate the of wordline address decoder jth row and bit line address decoderAntifuse may be programmed corresponding to row
The address WA of unit, now corresponding wordline address decoderi,j,kFor j, the address BA of corresponding bit line address decoderi,j,k
For0≤i ＜ N, 0≤j<Wi, 0≤k<Bi。
3rd, it is high level to put PGM, and maintains enough time to ensure that anti-fuse cell programming is completed；
4th, it is low level to put PGM.If the anti-fuse cell of programming also in need, goes to step 2；Otherwise programming is completed.
Specifically, the asic chip realized in the present embodiment based on antifuse look-up table standard block can be after silicon to anti-
Fuse standard block is programmed, so as to be finally completed the realization of asic chip function.Due to anti-fuse circuit after programming
It without invertibity, and can only program once, can not also crack even if with reverse engineering anti-fuse circuit after programming
State, therefore the standard cell circuit based on antifuse disposable programmable look-up table and the ASIC cores based on this standard block structure
Piece has very high security feature.
It is in particular in：IP suppliers can fundamentally protect intellectual property based on the method, without IP suppliers'
Programmed after silicon, IP user can not obtain complete function, can not also crack function, can not produce the core more than authorized quantity
Piece.Chip designer can be programmed after silicon to realize specific security control logic, or injection can not crack plus
Key realizes the safety storage of sensitive data.Due to chip manufacturing come out before, other people in addition to chip designer
Or entity does not grasp the complete function of chip, therefore it is difficult to gate circuit makes after targetedly wooden horse is injected in chip manufacturing proces
The security control logic failure of chip, or leakage chip internal status information.
A kind of asic chip implementation method provided in an embodiment of the present invention, including：Made with RTL code corresponding to asic chip
For input, with logic synthesis tool by chip functions logic synthesis into antifuse look-up table standard block netlist；By the net
All antifuse look-up table standard blocks in table, increase unified programming Control circuit；After increase programming Control circuit
Netlist, the layout design flow based on routine draws the GDS domains for meeting target process, and manufactures silicon according to the GDS domains
Chip；Using the input of the programming Control circuit of the silicon as programming Control interface, to all in the silicon
Antifuse look-up table standard block is programmed.
Because anti-fuse circuit does not have invertibity after programming, and it can only program once, even if with reverse engineering
Also the state of anti-fuse circuit after programming can not be cracked, therefore based on the standard block of antifuse disposable programmable look-up table
Circuit and based on this standard block structure asic chip there is very high security feature.It is in particular in：IP suppliers can
Fundamentally to protect intellectual property based on the method, without being programmed after the silicon of IP suppliers, IP user can not obtain complete work(
Can, function can not be also cracked, the chip more than authorized quantity can not be produced.Due to before chip manufacturing comes out, decoring
Other people or entity do not grasp the complete function of chip outside piece designer, therefore are difficult the injection needle in chip manufacturing proces
The security control logic for making chip to gate circuit after the wooden horse of property fails, or leakage chip internal status information.
A kind of asic chip provided in an embodiment of the present invention, including：
All antifuse in antifuse look-up table standard block netlist, with the antifuse look-up table standard block netlist
The connected programming Control circuit of look-up table standard block；
Wherein, the antifuse look-up table standard block netlist is by using RTL code corresponding to asic chip as defeated
Enter, with logic synthesis tool by chip functions logic synthesis into；And with the input of the programming Control circuit of the silicon
End is used as programming Control interface, and all antifuse look-up table standard blocks in the silicon are programmed.
Preferably, referring to Fig. 2, the programming Control circuit that the present embodiment provides includes：
The wordline address decoder 100 being connected with all antifuse look-up table standard blocks in the netlist；
The bit line address decoder 200 being connected with all antifuse look-up table standard blocks in the netlist；
The big resistance RBLK being connected with all antifuse look-up table standard blocks in the netlist；
Wherein, the other end of the big resistance is connected with program voltage input VP；
All antifuse look-up table standard blocks in the netlist are connected with programming enabled input signal PGM.
Preferably, in another embodiment of the invention, the big resistance is searched with all antifuse in the netlist
The grid of AF transistors in table standard block is connected.
Preferably, in another embodiment of the invention, the wordline enable signal that the wordline address decoder for decoding goes out,
Connected with all antifuse look-up table standard blocks in the netlist by row.
Preferably, in another embodiment of the invention, the bit line enable signal that the bit line address decoder for decoding goes out,
It is in parallel with all antifuse look-up table standard blocks in the netlist.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (7)
- A kind of 1. asic chip implementation method, it is characterised in that including：Using RTL code corresponding to asic chip as input, with logic synthesis tool by chip functions logic synthesis Cheng Fanrong Silk look-up table standard block netlist；By all antifuse look-up table standard blocks in the netlist, increase unified programming Control circuit；By the netlist after increase programming Control circuit, the GDS domains for meeting target process, and root are drawn based on layout design flow Silicon is manufactured according to the GDS domains；Using the input of the programming Control circuit of the silicon as programming Control interface, to all anti-in the silicon Fuse look-up table standard block is programmed.
- 2. implementation method according to claim 1, it is characterised in that with the input of the programming Control circuit of the silicon End is used as programming Control interface, and all antifuse look-up table standard blocks in the silicon are programmed, including：Programming enable signal is arranged to low level, program voltage is arranged to high-breakdown-voltage；With the address of the wordline address decoder in the programming Control circuit, the target antifuse look-up table programmed as needs The line identifier of standard block；With the address of the bit line address decoder in the programming Control circuit, melt as the target is counter The row mark of silk look-up table standard block；According to the line identifier and the row mark, selection needs program in the antifuse look-up table standard block netlist Target antifuse look-up table standard block；The programming enable signal is arranged to high level, and maintains preset time, by the antifuse look-up table standard block In antifuse fusing.
- A kind of 3. asic chip, it is characterised in that including：All antifuse in antifuse look-up table standard block netlist, with the antifuse look-up table standard block netlist are searched The connected programming Control circuit of table standard block；Wherein, the antifuse look-up table standard block netlist is by using RTL code corresponding to asic chip as input, transporting With logic synthesis tool by chip functions logic synthesis into；By with logic synthesis tool by chip functions logic synthesis into All antifuse look-up table standard blocks in antifuse look-up table standard block netlist, increase unified programming Control circuit； By the netlist after increase programming Control circuit, the GDS domains for meeting target process are drawn based on layout design flow, and according to institute GDS domains manufacture silicon is stated, using the input of the programming Control circuit of the silicon as programming Control interface, to described All antifuse look-up table standard blocks in silicon are programmed to obtain asic chip.
- 4. asic chip according to claim 3, it is characterised in that the programming Control circuit includes：The wordline address decoder being connected with all antifuse look-up table standard blocks in the netlist；The bit line address decoder being connected with all antifuse look-up table standard blocks in the netlist；The big resistance being connected with all antifuse look-up table standard blocks in the netlist；Wherein, the other end of the big resistance is connected with program voltage input；All antifuse look-up table standard blocks in the netlist are connected with programming enabled input signal.
- 5. asic chip according to claim 4, it is characterised in that all anti-molten in the big resistance and the netlist The grid of AF transistors in silk look-up table standard block is connected.
- 6. asic chip according to claim 5, it is characterised in that the wordline that the wordline address decoder for decoding goes out makes Energy signal, connected with all antifuse look-up table standard blocks in the netlist by row.
- 7. asic chip according to claim 6, it is characterised in that the bit line that the bit line address decoder for decoding goes out makes Energy signal, it is in parallel with all antifuse look-up table standard blocks in the netlist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510645938.3A CN105260679B (en) | 2015-10-08 | 2015-10-08 | A kind of asic chip implementation method and asic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510645938.3A CN105260679B (en) | 2015-10-08 | 2015-10-08 | A kind of asic chip implementation method and asic chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105260679A CN105260679A (en) | 2016-01-20 |
| CN105260679B true CN105260679B (en) | 2018-02-09 |
Family
ID=55100363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510645938.3A Active CN105260679B (en) | 2015-10-08 | 2015-10-08 | A kind of asic chip implementation method and asic chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105260679B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633993A (en) * | 2013-03-05 | 2014-03-12 | 中国科学院电子学研究所 | Programmable logic circuit containing customizable fuse configuration module |
| CN103761991A (en) * | 2013-12-30 | 2014-04-30 | 深圳市国微电子有限公司 | Lookup table and lookup table circuit for programmable chip |
-
2015
- 2015-10-08 CN CN201510645938.3A patent/CN105260679B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633993A (en) * | 2013-03-05 | 2014-03-12 | 中国科学院电子学研究所 | Programmable logic circuit containing customizable fuse configuration module |
| CN103761991A (en) * | 2013-12-30 | 2014-04-30 | 深圳市国微电子有限公司 | Lookup table and lookup table circuit for programmable chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105260679A (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Vijayakumar et al. | Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques | |
| US10129037B2 (en) | System and method for authenticating and enabling functioning of a manufactured electronic device | |
| Gu et al. | Improved reliability of FPGA-based PUF identification generator design | |
| Shamsi et al. | Cross-lock: Dense layout-level interconnect locking using cross-bar architectures | |
| US20130346928A1 (en) | Method for protecting rtl ip core | |
| Colombier et al. | Survey of hardware protection of design data for integrated circuits and intellectual properties | |
| CN113544688B (en) | System and method for designing integrated circuits | |
| Jin et al. | Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing | |
| Koushanfar | Integrated circuits metering for piracy protection and digital rights management: An overview | |
| US7550324B1 (en) | Interface port for electrically programmed fuses in a programmable logic device | |
| US8427193B1 (en) | Intellectual property core protection for integrated circuits | |
| CN104798338A (en) | Fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing | |
| US7941769B1 (en) | Method and apparatus for integrated circuits design security | |
| Sun et al. | A new pay-per-use scheme for the protection of FPGA IP | |
| US7987358B1 (en) | Methods of authenticating a user design in a programmable integrated circuit | |
| Keshavarz et al. | SAT-based reverse engineering of gate-level schematics using fault injection and probing | |
| CN105260679B (en) | A kind of asic chip implementation method and asic chip | |
| Shi et al. | Obfuscated built-in self-authentication with secure and efficient wire-lifting | |
| US8863230B1 (en) | Methods of authenticating a programmable integrated circuit in combination with a non-volatile memory device | |
| CN105243342B (en) | A kind of standard cell logic circuit based on disposable programmable look-up table | |
| CN104951579A (en) | Circuit credibility design method based on ID and FSM combination | |
| Sumathi et al. | Structural modification based netlist obfuscation technique for plds | |
| US20220197982A1 (en) | Hardware-Based Obfuscation of Digital Data | |
| Karri et al. | Physical unclonable functions and intellectual property protection techniques | |
| Sumathi et al. | Hardware Obfuscation Using Different Obfuscation Cell Structures for PLDs. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |