CN105260679A - ASIC chip implementation method and ASIC chip - Google Patents
ASIC chip implementation method and ASIC chip Download PDFInfo
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- CN105260679A CN105260679A CN201510645938.3A CN201510645938A CN105260679A CN 105260679 A CN105260679 A CN 105260679A CN 201510645938 A CN201510645938 A CN 201510645938A CN 105260679 A CN105260679 A CN 105260679A
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- antifuse
- look
- programming control
- table standard
- control circuit
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- 238000000034 method Methods 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000003786 synthesis reaction Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract 1
- 230000000875 corresponding effect Effects 0.000 description 10
- 230000006378 damage Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002730 additional effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
Abstract
Embodiments of the present invention disclose an ASIC chip implementation method and an ASIC chip. The method comprises: using an RTL code corresponding to the ASIC chip as an input, and integrating a chip function logic into a netlist of antifuse lookup table standard cells by using a logic integration tool; adding a uniform programming control circuit to all the antifuse lookup table standard cells in the netlist; processing the netlist added with the programming control circuit, obtaining a GDS layout in accordance with a target processbased on conventional layout design flow, and manufacturing a silicon chip according to the GDS layout; and using an input end of the programming control circuit of the silicon chip as a programming control interface, and carrying out programming on all the antifuse lookup table standard cells of the silicon chip. According to the embodiments, the mode of programming the antifuse lookup table standard cells after silicification guarantees a core logic of the chip not to be interfered or damaged by a Trojans circuit, and guarantees safe storage of core private data not to be stolen by a back door circuit.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, more particularly, relate to a kind of asic chip implementation method and asic chip.
Background technology
Semi-custom design flow based on standard block is the mainstay technology of current ASIC (ApplicationSpecificIntegratedCircuit: special chip).In this design cycle, chip designer adopts hardware description language design chips, namely modeling is carried out to chip functions, then use the Automation Design software that design code is comprehensively become standard cell circuit, and then standard cell circuit is converted to the GDS domain that can manufacture under corresponding making technology by the design of physics rear end, finally produce chip by foundries.Although at present obtain most widespread use based on the asic chip designing technique of CMOS standard block, also there is the problem that following security is correlated with.One is for an existing asic chip based on CMOS standard block, be difficult to confirm that the logical circuit of chip is certain and initial designs is completely the same by the Dynamic Non-Destruction Measurement that expense is little, namely after cannot confirming silicon, whether asic chip exists unexpected logical circuit, such as back door or wooden horse.Two is that chip designer or IP (IntellectualProperpty: refer to the reusable module that one party provides, form is logical block, chip design) core deviser thoroughly cannot protect knowledge-product technically; such as imitator can reduce the logical circuit of asic chip by reverse engineering; the unauthorized use of IP kernel supplier also uncontrollable IP kernel, namely uncontrollable IP kernel user produces the chip exceeding and limit quantity.
Therefore, the core logic how ensureing chip, by interference or the destruction of wooden horse circuit, ensures the safe storage of core private data and not stolen by rear gate circuit be the problem needing now to solve.
Summary of the invention
The object of the present invention is to provide a kind of asic chip implementation method and asic chip, to ensure that the core logic of chip is not by interference or the destruction of wooden horse circuit, ensures the safe storage of core private data and do not stolen by rear gate circuit.
For achieving the above object, following technical scheme is embodiments provided:
A kind of asic chip implementation method, comprising:
Using RTL code corresponding to asic chip as input, logic synthesis tool is used chip functions logic synthesis to be become antifuse look-up table standard block net table;
By all antifuse look-up table standard blocks in described net table, increase unified programming Control circuit;
To increase the net table after programming Control circuit, the layout design flow based on routine draws the GDS domain meeting target process, and manufactures silicon according to described GDS domain;
Using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
Preferably, using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed, comprising:
Be low level by program enable signal setting, program voltage is set to high-breakdown-voltage;
With the address of the wordline address code translator in described programming Control circuit, as the line identifier needing the target antifuse look-up table standard block of programming; With the address of the bit line address code translator in described programming Control circuit, the row as described target antifuse look-up table standard block identify;
According to described line identifier and described row mark, in described antifuse look-up table standard block net table, select the target antifuse look-up table standard block needing programming;
Be high level by described program enable signal setting, and maintain Preset Time, by the antifuse fusing in described antifuse look-up table standard block.
A kind of asic chip, comprising:
Antifuse look-up table standard block net table, the programming Control circuit be all connected with all antifuse look-up table standard blocks in described antifuse look-up table standard block net table;
Wherein, described antifuse look-up table standard block net table is by using RTL code corresponding to asic chip as input, uses logic synthesis tool chip functions logic synthesis to be become; And using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
Preferably, described programming Control circuit comprises:
The wordline address code translator be all connected with all antifuse look-up table standard blocks in described net table;
The bit line address code translator be all connected with all antifuse look-up table standard blocks in described net table;
With the described large resistance netted all antifuse look-up table standard blocks in showing and be all connected;
Wherein, the other end of described large resistance is connected with program voltage input end;
All antifuse look-up table standard blocks in described net table are all connected with program enable input signal.
Preferably, described large resistance is connected with the grid of the described AF transistor netted in all antifuse look-up table standard blocks in showing.
Preferably, the word line enable signal that described wordline address decoder for decoding goes out, connects by row with all antifuse look-up table standard blocks in described net table.
Preferably, the bit line enable signal that described bit line address decoder for decoding goes out, with described to net all antifuse look-up table standard blocks in showing in parallel.
Known by above scheme, a kind of asic chip implementation method that the embodiment of the present invention provides and asic chip, comprise: using RTL code corresponding to asic chip as input, use logic synthesis tool chip functions logic synthesis to be become antifuse look-up table standard block net table; By all antifuse look-up table standard blocks in described net table, increase unified programming Control circuit; To increase the net table after programming Control circuit, the layout design flow based on routine draws the GDS domain meeting target process, and manufactures silicon according to described GDS domain; Using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
Because anti-fuse circuit does not have reversibility after programming, and can only programme once, even if use reverse engineering also cannot crack anti-fuse circuit state after programming, therefore based on the standard cell circuit of antifuse disposable programmable look-up table and have very high security feature based on the asic chip that this standard block builds.Be in particular in: IP supplier fundamentally can protect the intellectual property based on the method, programme after not having the silicon of IP supplier, IP user cannot obtain complete function, also cannot crack function, more can not produce the chip exceeding authorized quantity.Due to before chip manufacturing out, except chip designer, other people or entity do not grasp the complete function of chip, therefore be difficult to inject in chip manufacturing proces targetedly after wooden horse gate circuit the security control logic of chip was lost efficacy, or leak chip internal status information.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of asic chip implementation method process flow diagram disclosed in the embodiment of the present invention;
Fig. 2 is programming Control electrical block diagram disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the invention discloses a kind of asic chip implementation method and asic chip, to ensure that the core logic of chip is not by interference or the destruction of wooden horse circuit, ensures the safe storage of core private data and do not stolen by rear gate circuit.
See Fig. 1, a kind of asic chip implementation method that the embodiment of the present invention provides, comprising:
S101, using RTL code corresponding to asic chip as input, logic synthesis tool is used chip functions logic synthesis to be become antifuse look-up table standard block net table;
Concrete, it should be noted that, antifuse look-up table standard block net table in S101 is only combinational logic net table, trigger used in chip and latch remain the logical block of conventional cmos structure, and this part trigger and latch logical block do not have additional effect for the realization flow of asic chip.
At this, all antifuse look-up table standard blocks are designated as AF respectively
0, AF
1..., AF
n-1, wherein N is the sum of antifuse look-up table standard block, and the input signal quantity of N number of antifuse look-up table standard block is respectively I
0, I
1..., I
n-1, output signal quantity is respectively O
0, O
1..., O
n-1, the word line enable number of signals W of each antifuse look-up table standard block
0, W
1..., W
i..., W
n-1, wherein
0≤i≤N; Each antifuse look-up table standard block neutrality line enable signal quantity is B
0, B
1..., B
n-1, wherein B
i=O
i, 0≤i≤N.Antifuse programmable unit in antifuse look-up table standard block is organized into W
irow B
ithe two-dimensional structure of row, 0≤i≤N.The state of each antifuse programmable unit is designated as S respectively
i, j, k, wherein 0≤i < N, 0≤j<W
i, 0≤k<B
i, S
i, j, kvalue be 0 or 1; If S
i, j, kbe 0, then namely needing programmes to anti-fuse cell fuses, if S
i, j, kbe 1, then without the need to programming to anti-fuse cell.
S102, by described net table in all antifuse look-up table standard blocks, increase unified programming Control circuit;
Concrete, for all antifuse look-up table standard blocks increase unified programming Control circuit, for programming to each antifuse look-up table standard block after silicon.
See Fig. 2, the programming Control circuit structure diagram that the present embodiment provides, programming Control circuit mainly comprise wordline address code translator 100 and bit line address code translator 200, and share large resistance RBLK, program voltage input VP, program enable input signal PGM.PGM is connected to all antifuse look-up table standard blocks, and one end of RBLK is connected to VP, and the other end is connected to the AF-G end of all antifuse programmable units.
When programming mode, PGM is high level, and VP is can the high voltage of breakdown antifuse transistor; When normal mode of operation, PGM is low level, and VP is the normal working voltage of transistor.Wordline address code translator needs decoding to go out to add up to the word line enable signal of W, wherein
the i.e. maximal value of word line enable number of signals in all antifuse look-up table standard blocks; Bit line address code translator needs decoding to go out to add up to the bit line enable signal of B, wherein
the address of wordline address code translator is designated as WA, and the bit wide of WA is X, X=log
2w,
the address of bit line address code translator is designated as BA, and the bit wide of BA is Y, Y=log
2b,
Antifuse look-up table standard block AF
ithe jth row that middle jth row word line enable signal is connected to wordline address code translator exports, wherein 0≤i<N, 0≤j<W
i; B output of bit line address code translator is connected one by one with B altogether bit line enable signal of all antifuse look-up table standard blocks.The word line enable signal of each antifuse look-up table standard block is connected by row, and the bit line of each antifuse look-up table standard block is in parallel, namely forms two-dimensional structure according to the mode of the capable B row of W.According to the antifuse programmable unit that the combination of the address of wordline address code translator and the address of bit line address code translator can select certain concrete, can programme to it under programming mode and to fuse by antifuse.The logical circuit of wordline address code translator and bit line address code translator adopts conventional CMOS standard block to realize, instead of antifuse look-up table standard block realizes.
S103, the net table that will increase after programming Control circuit, the layout design flow based on routine draws the GDS domain meeting target process, and manufactures silicon according to described GDS domain;
Concrete, in the present embodiment to insert net table after programming Control circuit for inputting, based on the ASIC rear end design cycle of routine and the GDS domain of eda tool Design and implementation chip; Then according to asic chip manufacturing process, silicon is manufactured according to GDS domain;
S104, using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon to be programmed.
Concrete, after producing silicon, by the programming Control interface of chip, antifuse look-up table programming units all in sheet is programmed, finally completes the realization of chip logic function.
Preferably, using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed, comprising:
Be low level by program enable signal setting, program voltage is set to high-breakdown-voltage;
With the address of the wordline address code translator in described programming Control circuit, as the line identifier needing the target antifuse look-up table standard block of programming; With the address of the bit line address code translator in described programming Control circuit, the row as described target antifuse look-up table standard block identify;
According to described line identifier and described row mark, in described antifuse look-up table standard block net table, select the target antifuse look-up table standard block needing programming;
Be high level by described program enable signal setting, and maintain Preset Time, by the antifuse fusing in described antifuse look-up table standard block.
Concrete, S104 can be:
1, putting program enable signal PGM is low level, and VP is high-breakdown-voltage;
2, the address arranging wordline address code translator and bit line address code translator needs the anti-fuse cell of programming with gating, concrete mode is: if antifuse look-up table standard block AF
iin the value S of certain antifuse programmable unit
i, j, kbe 0, namely need of gating wordline address code translator jth row and bit line address code translator
the antifuse programmable unit that row are corresponding, the address WA of now corresponding wordline address code translator
i, j, kfor j, the address BA of corresponding bit line address code translator
i, j, kfor
0≤i < N, 0≤j<W
i, 0≤k<B
i.
3, putting PGM is high level, and maintains enough time to guarantee that anti-fuse cell has been programmed;
4, putting PGM is low level.If also have the anti-fuse cell needing programming, then go to step 2; Otherwise programme.
Concrete, the asic chip realized based on antifuse look-up table standard block in the present embodiment can be programmed to antifuse standard block after silicon, thus finally completes the realization of asic chip function.Because anti-fuse circuit does not have reversibility after programming, and can only programme once, even if use reverse engineering also cannot crack anti-fuse circuit state after programming, therefore based on the standard cell circuit of antifuse disposable programmable look-up table and have very high security feature based on the asic chip that this standard block builds.
Be in particular in: IP supplier fundamentally can protect the intellectual property based on the method, programme after not having the silicon of IP supplier, IP user cannot obtain complete function, also cannot crack function, more can not produce the chip exceeding authorized quantity.Chip designer can carry out programming to realize specific security control logic after silicon, or injects the safe storage that the encryption key that can not crack realizes sensitive data.Due to before chip manufacturing out, except chip designer, other people or entity do not grasp the complete function of chip, therefore be difficult to inject in chip manufacturing proces targetedly after wooden horse gate circuit the security control logic of chip was lost efficacy, or leak chip internal status information.
A kind of asic chip implementation method that the embodiment of the present invention provides, comprising: using RTL code corresponding to asic chip as input, uses logic synthesis tool chip functions logic synthesis to be become antifuse look-up table standard block net table; By all antifuse look-up table standard blocks in described net table, increase unified programming Control circuit; To increase the net table after programming Control circuit, the layout design flow based on routine draws the GDS domain meeting target process, and manufactures silicon according to described GDS domain; Using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
Because anti-fuse circuit does not have reversibility after programming, and can only programme once, even if use reverse engineering also cannot crack anti-fuse circuit state after programming, therefore based on the standard cell circuit of antifuse disposable programmable look-up table and have very high security feature based on the asic chip that this standard block builds.Be in particular in: IP supplier fundamentally can protect the intellectual property based on the method, programme after not having the silicon of IP supplier, IP user cannot obtain complete function, also cannot crack function, more can not produce the chip exceeding authorized quantity.Due to before chip manufacturing out, except chip designer, other people or entity do not grasp the complete function of chip, therefore be difficult to inject in chip manufacturing proces targetedly after wooden horse gate circuit the security control logic of chip was lost efficacy, or leak chip internal status information.
A kind of asic chip that the embodiment of the present invention provides, comprising:
Antifuse look-up table standard block net table, the programming Control circuit be all connected with all antifuse look-up table standard blocks in described antifuse look-up table standard block net table;
Wherein, described antifuse look-up table standard block net table is by using RTL code corresponding to asic chip as input, uses logic synthesis tool chip functions logic synthesis to be become; And using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
Preferably, see Fig. 2, the programming Control circuit that the present embodiment provides comprises:
The wordline address code translator 100 be all connected with all antifuse look-up table standard blocks in described net table;
The bit line address code translator 200 be all connected with all antifuse look-up table standard blocks in described net table;
With the described large resistance RBLK netting all antifuse look-up table standard blocks in showing and be all connected;
Wherein, the other end of described large resistance is connected with program voltage input end VP;
All antifuse look-up table standard blocks in described net table are all connected with program enable input signal PGM.
Preferably, in another embodiment of the invention, described large resistance is connected with the grid of the described AF transistor netted in all antifuse look-up table standard blocks in showing.
Preferably, in another embodiment of the invention, the word line enable signal that described wordline address decoder for decoding goes out, connects by row with all antifuse look-up table standard blocks in described net table.
Preferably, in another embodiment of the invention, the bit line enable signal that described bit line address decoder for decoding goes out, with described to net all antifuse look-up table standard blocks in showing in parallel.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (7)
1. an asic chip implementation method, is characterized in that, comprising:
Using RTL code corresponding to asic chip as input, logic synthesis tool is used chip functions logic synthesis to be become antifuse look-up table standard block net table;
By all antifuse look-up table standard blocks in described net table, increase unified programming Control circuit;
To increase the net table after programming Control circuit, the layout design flow based on routine draws the GDS domain meeting target process, and manufactures silicon according to described GDS domain;
Using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
2. implementation method according to claim 1, is characterized in that, using the input end of the programming Control circuit of described silicon as programming Control interface, programmes, comprising all antifuse look-up table standard blocks in described silicon:
Be low level by program enable signal setting, program voltage is set to high-breakdown-voltage;
With the address of the wordline address code translator in described programming Control circuit, as the line identifier needing the target antifuse look-up table standard block of programming; With the address of the bit line address code translator in described programming Control circuit, the row as described target antifuse look-up table standard block identify;
According to described line identifier and described row mark, in described antifuse look-up table standard block net table, select the target antifuse look-up table standard block needing programming;
Be high level by described program enable signal setting, and maintain Preset Time, by the antifuse fusing in described antifuse look-up table standard block.
3. an asic chip, is characterized in that, comprising:
Antifuse look-up table standard block net table, the programming Control circuit be all connected with all antifuse look-up table standard blocks in described antifuse look-up table standard block net table;
Wherein, described antifuse look-up table standard block net table is by using RTL code corresponding to asic chip as input, uses logic synthesis tool chip functions logic synthesis to be become; And using the input end of the programming Control circuit of described silicon as programming Control interface, all antifuse look-up table standard blocks in described silicon are programmed.
4. asic chip according to claim 3, is characterized in that, described programming Control circuit comprises:
The wordline address code translator be all connected with all antifuse look-up table standard blocks in described net table;
The bit line address code translator be all connected with all antifuse look-up table standard blocks in described net table;
With the described large resistance netted all antifuse look-up table standard blocks in showing and be all connected;
Wherein, the other end of described large resistance is connected with program voltage input end;
All antifuse look-up table standard blocks in described net table are all connected with program enable input signal.
5. asic chip according to claim 4, is characterized in that, described large resistance is connected with the grid of the described AF transistor netted in all antifuse look-up table standard blocks in showing.
6. asic chip according to claim 5, is characterized in that, the word line enable signal that described wordline address decoder for decoding goes out, and connects by row with all antifuse look-up table standard blocks in described net table.
7. asic chip according to claim 6, is characterized in that, the bit line enable signal that described bit line address decoder for decoding goes out, with described to net all antifuse look-up table standard blocks in showing in parallel.
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