CN103633993A - Programmable logic circuit containing customizable fuse configuration module - Google Patents
Programmable logic circuit containing customizable fuse configuration module Download PDFInfo
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Abstract
The invention discloses a programmable logic circuit containing a customized fuse configuration module. A configuration position of the circuit is composed of a static random access memory (SRAM) configuration unit and a customizable fuse configuration unit which can be switched to fuse position control. When a customized circuit is realized, according to a certain process, a limited metal mask layer board is changed to solidify part of circuit functions, and at the same time a control position of a key circuit is switched to fuse position control, so that fuse configuration can be realized by writing by a user, and finally functions of a user circuit are realized while safety of key information of the user circuit is ensured. On the basis of advantages including short development period, low cost, strong flexibility, and large circuit scale of a general field programmable gate array, the programmable logic circuit of the invention also has the advantages that the capability of resisting a single particle is substantially improved, and the safety of the user circuit is ensured.
Description
Technical field
The present invention relates to Programmable Logic Device technical field, relate in particular to a kind of Programmable Logic Device that comprises customizable fuse configuration module.
Background technology
Development along with integrated circuit technique, the appearance of field programmable gate array (FPGA), for user provides system programmable or reconfigurable ability, for the signal of many complexity is processed and data processing circuit and system realization provide new mentality of designing and verification method, make the design cycle significantly shorten simultaneously, reduce design cost, reduce design risk, make large scale integrated circuit of new generation there is higher flexibility and stronger adaptability, be therefore able to extensive use in civilian and aerospace electronic system.
But along with the increase of integrated level, space radiation environment is more and more serious on the impact of FPGA.The electromagnetic radiation and the particle radiation that in space, exist the sun, its source comprises the radiation belt of the earth, solar cosmic ray and galactic comic ray.These complicated ionizing radiation environments are degenerated the performance parameter of device, even cause disabler, thereby have influence on the normal operation of circuit system and complete machine, and circuit reliability is weakened, and shorten lifetime of system.Especially the single-particle inversion problem of FPGA affects the bottleneck of its AEROSPACE APPLICATION especially.
At present most widely used is general FPGA based on static memory SRAM structure, and the advantage of this device is that system development is flexible.But this feature has also determined to have comprised in device a large amount of configuring static memories simultaneously.These static memory quantity are large, a little less than wide, the anti-SEU ability that distributes, the most easily rewritten, thereby cause disabler in space environment.Conventional solution comprises that it is all passive error correction that triplication redundancy and configuring static memory cycle are cleaned, and these mode resource utilizations are low, and caused the system instantaneous interruption of function in-orbit.In addition, aerospace system often adopts the FPGA based on fuse technique, but this technique can only realize one-off programming, designs and develops very flexible, and cost is high, and because its technique own characteristic is limited on scale and capacity, in application, has significant limitation.
Fig. 1 shows the schematic diagram of the fpga chip 100 of current main flow based on SRAM type.It comprises journey input/output module 110, programmable logic block 111, programmable storage 112, multiplier 113 able to programme, programmable processor 114 programmable resources such as grade, each self-corresponding 120～124 configuration bit modules of input and output pin one 15 and 110～114 modules.After chip power, conventionally by nonvolatile memory is read in the static RAM SRAM in the configuration modules such as 120～124 as the configuration data of downloading in advance in EEPROM and Flash PROM.By these configuration bits, realize the difference in functionality of chip.
Fig. 2 is the schematic diagram of 6 conventional pipe sram cell circuit 200 of the configuration bit module of the FPGA based on SRAM type.It comprises the first access pipe 211A, the second access pipe 211Ab, and the cross-couplings reverser being comprised of reverser 215A and 215B is to 215.The paratope line bin of sram cell circuit 200 and nbin receive respectively access pipe 211A and 211Ab drain electrode separately.The read/write Enable Pin wren of sram cell circuit 200 connects respectively the grid of access pipe 211A and 211Ab.When read/write Enable Pin wren is effective, paratope line bin and nbin carry out access, corresponding output bout and nbout to cross-couplings reverser to 215 complementary node sd and nsd by access pipe 211A and 211Ab.
It in Fig. 3, is the schematic diagram of the common configuration dual-port sram cell circuit 300 of the FPGA based on SRAM type.It comprises the first access pipe 311A, the second access pipe 311Ab, the 3rd access pipe 312B, the 4th access pipe 312Bb, and the cross-couplings reverser being comprised of reverser 315A and 315B is to 315.The first couple of paratope line binA and the nbinA of dual-port sram cell circuit 300 receive respectively access pipe 311A and 311Ab drain electrode separately, and the second couple of paratope line binB and binB receive respectively access pipe 312B and 312Bb drain electrode separately.The first read/write Enable Pin wrenA of dual-port sram cell circuit 300 connects respectively the grid of access pipe 311A and 311Ab, and the second read/write Enable Pin wrenB connects respectively the grid of access pipe 312B and 312Bb.When read/write Enable Pin wrenA is effective, paratope line binA and nbinA by access pipe 311A and 311Ab to cross-couplings reverser to 315 complementary node sd[0] and nsd[0] carry out access; When read/write Enable Pin wrenB is effective, paratope line binB and nbinB by access pipe 312B and 312Bb to cross-couplings reverser to 305 complementary node sd[0] and nsd[0] carry out access.
Based on primary particle inversion resistant consideration, propose in the industry to realize by customization FPGA the way of circuit, customization FPGA is after user's application and development completes, configuring static memory states whole in general FPGA is solidified, by one deck or finite layer mask plate revising former general FPGA, according to the code stream of practical application circuit, configuration bit is directly connected with fixing high and low level, realize circuit function, from source, solved the primary particle inversion resistant problem based on the general FPGA of SRAM structure.Customization FPGA adopts common CMOS process, and user's code stream is solidificated in design completely, without the data after powering on, loads, and has eliminated the possibility that code stream is stolen in loading procedure.But this mode is because physical structure exposes completely, thereby exist the mistake of production link to build or by oppositely extracting the danger of dialyse and designing.And circuit safety is particularly most important AEROSPACE APPLICATION concerning user, especially in circuit, key modules comprises that the safety of the information such as system key is directly connected to the fail safe of whole system.
Summary of the invention
In order to address the above problem, keeping on the jumbo basis of chip, improve chip anti-single particle ability, allow again user retain crucial circuit information simultaneously, to guarantee the fail safe of circuit, the present invention proposes and a kind ofly support customization mode and key configuration position to realize the novel FPGA device architecture that the autonomous programming of user is provided by fuse technique.In device on circuit structure, most of configuration bit can be realized by customization, and key message is configured by fuse-wires structure.
When device is used, by specified layout, Key Circuit is placed on specific position, configuration bit stream is distinguished simultaneously, and be configured by the different modes of custom-modification finite layer mask plate and programming fuse bit.
The present invention proposes several physical circuit implementations and the control flow of this device simultaneously, finally to realize application circuit function.
By this structure devices, realize application circuit, compare and there is following features with existing several implementations.Than ASIC (Application Specific Integrated Circuit), the design cycle is short, and exploitation flexibility is high, and risk is low; FPGA than tradition based on SRAM structure, especially anti-single particle ability is stronger for anti-irradiation, and reliability is high; Than the FPGA based on fuse technique, can realize circuit scale larger, performance is more excellent; The FPGA realizing than single employing customization mode, its circuit information is without informing foundry vendor, and subscriber line circuit is safe, and autonomous controllability is strong, is applicable to being applied to the application circuit field of high security demand.
Accompanying drawing explanation
Fig. 1 is the common fpga chip schematic diagram based on SRAM type;
Fig. 2 is the schematic diagram of common 6 pipe sram cell circuit;
Fig. 3 is the schematic diagram of common dual-port sram cell circuit;
Fig. 4 is based on 2 of 6 pipe sram cells in the present invention
nthe customizable fuse configuration module in position;
Fig. 5 is based on 2 of dual-port sram cell in the present invention
nthe customizable fuse configuration module in position;
Fig. 6 is based on customizable fuse configuration bit circuit realization flow figure in the present invention;
Fig. 7 is 4 fuse configuration modules and the exemplary plot of being arranged in order the configuration bit array of output by 4 common configuration unit in the present invention;
Fig. 8 is 4 fuse configuration module and arranged the exemplary plot of the configuration bit array of output by 4 common configuration unit by alternating sequence in the present invention;
Fig. 9 is customizable fuse configuration bit layout type exemplary plot in the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention proposes a kind of customizable Programmable Logic Device, it supports custom model, the concrete configuration that is user's programmable resource of specifying Programmable Logic Device realizes, and then by manufacturer, the specified specific configuration information of user is solidificated in common customizable configuration module; In addition, the key configuration position of the customizable Programmable Logic Device that the present invention proposes can be realized by non-volatile type memorizers such as fuse, anti-fuse, Flash, by user, specifies and solidify the specific configuration information of described key configuration position in customized module.
A kind of customizable Programmable Logic Device that the present invention proposes, it comprises pass key mapping configuration module and common position configuration module, described pass key mapping configuration module closes the configuration information of key mapping for storing Programmable Logic Device programmable resource, and controls the configuration of programmable resource pass key mapping in described Programmable Logic Device; And described common position configuration module is for storing the configuration information of the common position of Programmable Logic Device programmable resource, and control the configuration of the common position of programmable resource in Programmable Logic Device.
In a preferred embodiment of the invention, close key mapping configuration module and realized by customizable fuse configuration module, and common position configuration module consists of the configuration sram cell circuit that comprises static memory SRAM.
Fig. 4 shows the schematic diagram of customizable fuse configuration module in the preferred embodiment of the present invention.The circuit 400 of realizing of the customizable fuse configuration module of this Programmable Logic Device comprises: configuration SRAM array module 410, configuration mode is selected module 421 and fuse bit generation module 430.Wherein configure SRAM array module 410 by 2
nindividual configuration sram cell circuit 416 forms, and configuration sram cell circuit 416 comprises the first access pipe 411A, the second access pipe 411Ab, the first reverser 415A, and the second reverser 415B.Configuration mode selects module 420 by 421～42m, and totally 2
nindividual metal-oxide-semiconductor forms.Fuse bit generation module 430 comprises control circuit 431, predecode circuit 433, array of fuses 432 and decoding circuit 434.
The bit line bin[0 of configuration sram cell circuit 416] be connected to the drain electrode of the first access pipe 411A, the source electrode of the first access pipe 411A connects the input of the first inverter 415A and the output of the second inverter 415B.The paratope line nbin[0 of configuration sram cell circuit 416] be connected to the drain electrode of the second access pipe 411Ab, the source electrode of the second access pipe 411Ab connects the output of the first inverter 415A and the input of the second inverter 415B.The read/write Enable Pin wren[0 of configuration sram cell circuit 416] be connected respectively to the grid of the first access pipe 411A and the second access pipe 411Ab.As read/write Enable Pin wren[0] effectively time, bit line bin[0] and its corresponding paratope line nbin[0] respectively by the first access pipe 411A and the second access pipe 411Ab to cross-couplings reverser the complementary node sd[0 to 415A and 415B] and nsd[0] carry out access.
Bout[0] as configuration bit output, be connected on the programmable resource of described Programmable Logic Device and be configured control, to realize circuit function.
Input sense_pulse, the prog_fuse_en of control circuit 431 by fuse bit generation module 430, the signal that fuse_en inputs are controlled the mode of operation of fuse bit generation module 430.
When prog_fuse_en is high level, when fuse_en is high level, fuse bit generation module 430 enters programming enable mode, and fu_sc originates for fuse bit programming provides high level signal; When prog_fuse_en is low level, when fuse_en is low level, fuse bit generation module 430 enters reading mode, and when the trailing edge of sense_pulse signal arrives, fuse_out is effective in output, is about to the storing value output of array of fuses 432.
N bit address signal addr[n-1: 0] and fu_sc signal send into predecode circuit 433 and carry out preliminary treatment, and complete the decoding to address by decoding circuit 434, and realize the addressing access to memory cell in array of fuses 432, they are corresponding 2 years old
nposition storage element is output as fuse_out[2
n-1: 0].
Configuration mode selects module 420 by 421～42m, and totally 2
nwhether individual metal-oxide-semiconductor forms, and input signal mode_sel connects the grid of these metal-oxide-semiconductors, by controlling this signal, control by the output fuse_out[2 of fuse bit generation module 430
n-1: 0] signal is delivered to respectively the respective nodes sd[2 of configuration SRAM array module 410
n-1: 0].To mode_sel signal, be 0 o'clock, configuration module 400 enters general FPGA configuration mode, and it exports bout[2
n-1: 0] be node sd[2
n-1: 0] current potential is by configuring SRAM array module 410 interior 2
nthe storage content-control of individual configuration sram cell circuit 416; Mode_sel signal is 1 o'clock, and configuration module 400 enters customization FPGA fuse configuration mode, and it exports bout[2
n-1: 0] by the output fuse_out[2 of fuse bit generation module 430
n-1: 0] control.
Under above-mentioned FPGA configuration mode, user is by carrying out detail programming to configuring the content of sram cell circuit 416 in configuration SRAM array module 410, to determine that the programmable resource in final programmable circuit closes the configuration information of key mapping; All the other configuration bit information can be informed foundry vendor, by revise finite layer mask plate on the basis of common FPGA, realize custom circuit.Foundry vendor consigns to device after user, and user can fixedly fire the configuration information of final pass key mapping in the array of fuses of described fuse bit generation module, and under custom model, uses the programmable resource of this programmable circuit to realize corresponding function.
2
n2 of individual configuration sram cell circuit 416
nto cross-couplings reverser to 415A and 415B corresponding to 2
nindividual node sd[2
n-1: 0] 2
nindividual complementary node nsd[2
n-1: 0] except level negate, with 2
nindividual node sd[2
n-1: 0] can equivalence replace, these are 2 years old
nindividual complementary node nsd[2
n-1: 0] provide 2
nindividual configuration bit nbout[2
n-1: 0], be connected to the programmable resource of Programmable Logic Device, can equivalence replace 2
nindividual node sd[2
n-1: 0], to select 2 of module 420 with configuration mode
nindividual output is connected, and realizing output is the selection that configuration status is controlled by the memory cell configuring in sram cell circuit 416 or array of fuses 433.
Fig. 5 comprises 2
nthe new arrangement module principle schematic diagram of individual user's dual-port sram cell 515 gate array 516.Comprise: configuration SRAM array module 510, configuration mode is selected module 521, fuse bit generation module 530.Configuration SRAM array module 510 is by 2
nindividual dual-port configuration sram cell circuit 516 forms; Configuration mode selects module 520, fuse bit generation module 530 identical with the corresponding module in circuit 400.
Dual-port sram cell circuit 516 comprises the first access pipe 511A, the second access pipe 511Ab, the 3rd access pipe 512B, the 4th access pipe 512Bb, the first reverser 515A, and the second reverser 515B.First couple of paratope line binA[0 of dual-port sram cell circuit 516] and nbinA[0] receive respectively the first access pipe 511A and the second access pipe 511Ab drain electrode separately, second couple of paratope line binB[0] and nbinB[0] the 3rd access pipe 512B and the 4th access pipe 512Bb drain electrode separately received respectively.The source electrode of the first access pipe 511A connects the input of the first reverser 515A and the output of the second reverser 515B; The source electrode of the second access pipe 511Ab connects the output of 515A and the input of the second reverser 515B of the first reverser.The source electrode of the 3rd access pipe 512B connects the input of the first reverser 515A and the output of the second reverser 515B; The source electrode of the 4th access pipe 512Bb connects the output of the first reverser 515A and the input of the second reverser 515B.2
n2 of individual dual-port sram cell circuit 516
nindividual the first read/write Enable Pin wrenA[2
n-1: 0] correspondingly respectively receive 2
nthe first access pipe 511A of individual dual-port sram cell circuit 516 and the grid of the second access pipe 511Ab, 2
nindividual the second read/write Enable Pin wrenB[2
n-1: 0] correspondingly respectively receive 2
nthe 3rd access pipe 512B of individual dual-port sram cell circuit 516 and the grid of the 4th access pipe 512Bb.As m the first read/write Enable Pin wrenA[2
nwhen-1: 0] difference is effective, paratope line binA[2
n-1: 0] and nbinA[2
n-1: 0] respectively by 2
nto the first access pipe 511A and the second access pipe 511Ab to cross-couplings reverser the node sd[2 to 515A and 515B
n-1: 0] and its 2
nindividual complementary node is carried out access; When 2
nindividual the second read/write Enable Pin wrenB[2
nwhen-1: 0] difference is effective, paratope line binB and nbinB are respectively by 2
nto the 3rd access pipe 512B and the 4th access pipe 510Bb to cross-couplings reverser to 515A and 515B 2
nindividual node sd[2
n-1: 0] and its 2
nindividual complementary node nsd[2
n-1: 0] carry out access.
In configuration module 500, configuration SRAM array module 510, configuration mode is selected module 521, and the annexation between fuse bit generation module 530 and operation principle are with circuit 400.
2
n2 of individual configuration dual-port sram cell circuit 516
nto cross-couplings reverser to 515A and 515B corresponding to 2
nindividual node sd[2
n-1: 0] 2
nindividual complementary node nsd[2
n-1: 0] except level negate, with 2
nindividual node sd[2
n-1: 0] can equivalence replacement provide 2
nindividual configuration bit nbout[2
n-1: 0] receive the programmable resource of logical circuit, can equivalence replace and 2 of configuration mode selection module 520
nindividual output is connected, and realizing output is the selection that configuration status is controlled by the memory cell configuring in dual-port sram cell circuit 516 or array of fuses 533.
In a preferred embodiment, configuration mode in Fig. 4 and Fig. 5 in configuration module 400/500 circuit selects module 420/520 also can remove, do not carry out model selection, while entering custom model, directly by revising the finite layer mask plate of the FPGA under general mode, by the output fuse_out[2 of fuse bit generation module 430/530
n-1: 0] signal is directly connected to corresponding node sd[2 by metal wire
n-1: 0], the function of circuit is configured to control.The method can reduce configuration to be selected to control metal-oxide-semiconductor number, but cannot between general mode and custom model, switch.
In a preferred embodiment, configuration SRAM array module 410/510 in Fig. 4 and Fig. 5 in configuration module 400/500 circuit also can select module 420/520 to remove in the lump with configuration mode, when customization realizes application circuit, directly the output of fuse bit generation module 430/530 is connected to the configuration end of part programmable logic resource, and other common SRAM configuration bit is realized the control to circuit function jointly.
Access pipe in Fig. 4 and Fig. 5 can be replaced and be realized identical function by gated devices such as transmission gates.Be the concrete structure and the restriction that realizes logic that function of the present invention is not subject to adopted switch.And described configuration mode selects the metal-oxide-semiconductor in module also can be realized by other any switching selector part.
Fuse bit generation module is by user's programming part voluntarily key configuration position information, and its output connects the control end of the programmable resource of Programmable Logic Device, to control, realizes different functions.In Fig. 4 and Fig. 5, fuse bit generation module is only exemplary plot, can realize by all the other control signals or control mode, also can be by realizing as other nonvolatile memories such as anti-fuse, flash.Be that function of the present invention is not produced and control mode by adopted configuration bit, and the restriction of specific implementation technique.
Fig. 6 is the embodiment flow chart carrying out according to the present invention.Its required step of carrying out comprises:
Step 601, user carry out application circuit exploitation debugging on FPGA, by specified layout, connect up, and the key message circuit that needs user to configure is voluntarily specified and realized by the resource of being controlled by fuse configuration bit;
Step 602, whole code stream information are derived, and adopt code stream isolation technics that the code stream cfg_datal configuring by common SRAM and the code stream cfg_data2 that controls by fuse configuration module are distinguished, be kept at respectively different files;
Step 603, according to deriving code stream cfg_datal destination file, produce masked edit program script;
Step 604), use masked edit program script to programme, generate new replacement mask layer, cured portion user's design;
Step 605, carry out the replacement of finite layer mask layer, synthetic new flow mask;
Step 606, use new flow mask flow again;
Step 607, on new chip, according to cfg_data2, by user, fuse configuration module is carried out to programming voluntarily;
Step 608, end user carries out circuit test.
Common position configuration module in the preferred embodiment of the present invention in programmable logic cells can be realized by customizable common position configuration sram cell.
In a preferred embodiment of the invention, shown in Fig. 7 and Fig. 8, customizable configuration module comprises the structure chart that the common use of the array 711/811 that the customizable fuse configuration module as described in Fig. 4 or Fig. 5 of 4 forms and the common position configuration module consisting of 4 customizable common position configuration sram cells 710/810 is example, and it has illustrated to close the different modes of emplacement of key mapping configuration module and common position configuration module.Wherein customizable common position configuration sram cell 710/810 comprises common configuration sram cell 721/821 and custom source 722/822, and described common configuration sram cell 721/821 its structure can be identical with the configuration sram cell circuit 416 or 415 in described customizable fuse configuration module, as shown in Figures 4 and 5, and the source that provides of under custom model height fixed level is provided custom source 722/822.The final output of customizable common position configuration sram cell 710/810 is as sram_out[0] signal controlled by common configuration sram cell 721/821 under configuration mode, under custom model, by custom source 722/822, controlled, user, determined after the specific implementation of programmable resource, the low and high level providing according to described specific implementation custom source 722/822 is connected on the common configuration position of described programmable resource.The final output of customizable fuse configuration module 711/811 is as sram_out[7] signal configuration sram cell circuit in customizable fuse configuration module under configuration mode controls, under custom model, by the output of array of fuses, controlled.
The customizable common position configuration output of sram cell 710/810 and the final control bit sram_out of the common formation of the output of fuse configuration module 711/811.The formation order of sram_out can arbitrarily be put, in Fig. 7,4 customizable common position configuration output of sram cell 710 and the output of customizable fuse configuration module 711 form sequence sram_out[7 in order: 0], and in Fig. 8, alternating sequence formation sequence sram_out[7 press in 4 customizable common position configuration output of sram cell 810 and the output of customizable fuse configuration module 811: 0].Certainly, the visual actual demand of its modes of emplacement is selected, and number of configuration bits difference and different modes of emplacements all belong to claim scope of the present invention.
Programmed logical module in the fpga chip 100 that Fig. 9 be take based on SRAM type is example, has illustrated the topology layout mode of customizable fuse configuration module in the present invention.Programmed logical module resource 900 in FPGA generally by switch enclosure 910, connecting box 911, multichannel select module 912 and logical block bunches 913 and separately corresponding configuration module form.Wherein, logical block bunches 913 generally consists of a plurality of logical blocks 920 and logic control element 921.Logical block 920 in main flow fpga chip is conventionally containing one or more look-up table lut932, one or more register dff933, its configuration bit can choice for use customizable fuse configuration module 931 provided by the invention, to realize, the function of look-up table 932 and register 933 is controlled, all the other configuration bits can be provided by common customizable SRAM configuration module 930.Different logical blocks 920 can configure control mode can be different.Equally, as shown in Figure 9, logic control element 921 also can be selected by 931 pairs of customizable fuse configuration modules key modules wherein, as the modules such as carry control unit 934 are controlled.
As shown in Figure 9, customizable fuse configuration module 931 can be used for the configuration of the modules such as control switch box 910, connecting box 911, multichannel selection module 912 equally.In like manner, customizable fuse configuration module is except can be used for controlling programmable logic block, and it can be used for the input/output module 110 shown in control chart 1 equally, programmable storage 112, multiplier 113 able to programme, programmable processor 114 other programmable resources such as grade.
Because the area consumption of customizable fuse configuration module is larger than common SRAM configuration module, can be in the equilibrium considering between performance area and user security requirement, the customizable fuse configuration module of all or part of employing in the configuration module in chip.
The present invention is not subject to the restriction of specific implementation method and the restriction of the logical form that circuit adopts of circuit, and for example, all bottom circuit can be the CMOS technique of standard or other technique.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a customizable Programmable Logic Device, it comprises pass key mapping configuration module and common position configuration module, described pass key mapping configuration module closes the configuration information of key mapping for storing Programmable Logic Device programmable resource, and controls the configuration of programmable resource pass key mapping in described Programmable Logic Device; Described common position configuration module is used for storing the configuration information of the common position of Programmable Logic Device programmable resource, and controls the configuration of the common position of programmable resource in Programmable Logic Device.
2. customizable Programmable Logic Device as claimed in claim 1, is characterized in that,
Described pass key mapping configuration module comprises nonvolatile memory array, and it closes the configuration information of key mapping for storing described Programmable Logic Device programmable resource.
3. customizable Programmable Logic Device as claimed in claim 2, is characterized in that,
Described pass key mapping configuration module also comprises static memory cell array, it closes the configuration information of key mapping for storing described Programmable Logic Device programmable resource, and under configuration mode, controls the configuration of programmable resource pass key mapping in described Programmable Logic Device; And described nonvolatile memory array is controlled the configuration of programmable resource pass key mapping in described Programmable Logic Device under custom model.
4. customizable Programmable Logic Device as claimed in claim 2, is characterized in that, described Programmable Logic Device also comprises configuration mode selection module, and it is for selecting described customizable fuse configuration module to be operated in configuration mode or custom model.
5. customizable Programmable Logic Device as claimed in claim 1, is characterized in that,
Described common position configuration module comprises static memory cell and the fixedly custom source of low and high level is provided, described static memory cell is for storing the configuration information of the common position of described programmable circuit programmable resource, and under configuration mode for controlling the configuration of the common position of described programmable circuit programmable resource; And described custom source directly provides fixing low and high level to control the configuration of the common position of programmable resource in described Programmable Logic Device to the output of described common position configuration module under custom model.
6. customizable Programmable Logic Device as claimed in claim 1, is characterized in that,
The output of the output of described pass key mapping configuration module and described common position configuration module forms sequence by different order, controls respectively the configuration that programmable resource in Programmable Logic Device closes key mapping and common position.
7. customizable Programmable Logic Device as claimed in claim 2, is characterized in that,
Described static memory comprises cross coupling inverter, door control unit, a pair of Complementary input structure bit line and at least one pair of complementary output node, wherein said a pair of Complementary input structure bit line is write data to cross coupling inverter equivalently under the control of described door control unit, and described at least one pair of complementary output node is used for the data of output cross coupled inverters equivalently.
8. customizable Programmable Logic Device as claimed in claim 3, it is characterized in that, configuration mode selects module to consist of a plurality of switch selected cells, under the control of mode select signal, the programmable resource that described configuration mode selects a plurality of switch selected cells of module to select respectively the output of static memory in the output of array of fuses in the key mapping configuration module of described pass or described pass key mapping configuration module to control described Programmable Logic Device closes the configuration of key mapping.
9. customizable Programmable Logic Device as claimed in claim 2, is characterized in that,
Described nonvolatile memory array comprises array of fuses, anti-array of fuses and flash memory array.
10. a method for customizing for Programmable Logic Device as claimed in claim 1, the method comprises:
Step 1, described Programmable Logic Device is switched to configuration mode, by described pass key mapping configuration module, control the configuration that programmable resource in described Programmable Logic Device closes key mapping, by described common position configuration module, control the configuration of the common position of programmable resource in described Programmable Logic Device, to debug this Programmable Logic Device, and finally determine the configuration information of programmable resource in Programmable Logic Device, the configuration information of described programmable resource comprises crucial position configuration information and common position configuration information;
Step 2, the custom source in the configuration module of described common position is connected to the common position of programmable resource in described Programmable Logic Device, by described custom source, to the common position of programmable resource in described Programmable Logic Device, provide fixing low and high level, described fixing low and high level is corresponding with described common position configuration information;
Step 3, described Programmable Logic Device is switched to custom model, the configuration information that described programmable resource is closed to key mapping is solidificated in the nonvolatile memory array in the key mapping configuration module of described pass, by described nonvolatile memory array, directly controls the configuration of programmable resource pass key mapping in described Programmable Logic Device.
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Cited By (3)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104133655A (en) * | 2014-07-11 | 2014-11-05 | 中国人民解放军信息工程大学 | Design method of anti-radiation multiplier based on satellite-borne MIMO detection |
| CN104133655B (en) * | 2014-07-11 | 2017-02-15 | 中国人民解放军信息工程大学 | Design method of anti-radiation multiplier based on satellite-borne MIMO detection |
| CN105260679B (en) * | 2015-10-08 | 2018-02-09 | 浪潮(北京)电子信息产业有限公司 | A kind of asic chip implementation method and asic chip |
| CN109086467A (en) * | 2017-06-14 | 2018-12-25 | 上海复旦微电子集团股份有限公司 | I/O cell layout method and device, medium and the equipment of programmable logic device |
| CN109086467B (en) * | 2017-06-14 | 2023-05-02 | 上海复旦微电子集团股份有限公司 | I/O unit layout method and device, medium and equipment of programmable logic device |
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