CN105354381B - FPGA redundance implementation methods based on reconstruct - Google Patents
FPGA redundance implementation methods based on reconstruct Download PDFInfo
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Abstract
The FPGA redundance implementation methods based on reconstruct that the invention discloses a kind of, this method firstly generates each remaining module FPGA configuration data, statistics configuration data length determines timeout parameter, then it establishes remaining switching table and remaining handover module is set up according to the table, remaining handover module FPGA configuration data is generated, after later integrating configuration data in programming to FPGA configuration chips；Remaining handover module configures house dog according to remaining switching table, carries out remaining scheduling, using specified remaining module configuration data configuration FPGA and run, remaining handover module is returned to when selected remaining breaks down and carries out remaining selection, until all remainings fail.The method of the present invention realizes the redundance of single FPGA using reconstruct mode, compared with non-reconstruct mode, the increase of FPGA hardware cost is avoided, reduces the transport protocol requirement to input data, the flexibility for increasing system design, makes user that can establish more structurally sound multiplicated system.
Description
Technical field
The invention belongs to FPGA redundances to realize field, be related to a kind of FPGA redundance implementation methods based on reconstruct.
Background technology
Redundancy technology is a kind of important means of raising system functional reliability, since FPGA has good may customize
Property, diversified remaining switching demand can be met, therefore be widely applied in multiplicated system.It is traditional based on FPGA
Multiplicated system use two kinds of realization methods of single FPGA or more FPGA of non-reconstruct, wherein single FPGA is achieved in that multichannel
It is sent into FPGA simultaneously using the data of same or like agreement transmission, FPGA carries out correction judgement and accordingly to each circuit-switched data
Carry out system controls and data selection.More FPGA realization methods are then to constitute hardware redundancy using 2 or more fpga chips,
Another FPGA is automatically switched to when some FPGA operation irregularity, to ensure the normal work of system.
Both the above realization method has achieved the purpose that raising system reliability, meets the remaining of system to a certain extent
Design requirement is spent, but there are the following problems：Single FPGA realization method requires the data of input to be assisted using same or similar transmission
View, if transport protocol is different, FPGA needs to establish different hardware processing logics for each agreement, to need bigger
The FPGA and configuration chip of scale, increase hardware cost；More FPGA realization methods not only increase hardware cost, due also to FPGA
Between control and the introducing of decision logic and increase the failure rate of system to a certain extent.
Invention content
(1) goal of the invention
The purpose of the present invention is：To avoid the increase of hardware cost in the realization of FPGA redundances, increase the spirit of system design
Activity provides a kind of FPGA redundance implementation methods based on reconstruct.
(2) technical solution
The FPGA redundance implementation methods based on reconstruct that in order to solve the above technical problem, the present invention provides a kind of, packet
Include following steps：
1) each remaining module FPGA configuration data is generated, configuration data length is counted, determines timeout parameter；
2) remaining switching table is established according to the statistical data of step 1)；
3) remaining handover module is set up according to remaining switching table, generates remaining handover module FPGA configuration data；
4) configuration data integrates programming；
5) remaining handover module configures house dog, dispatches remaining module；
6) it configures FPGA using specified remaining module configuration data and runs；
7) step 5) and step 6) are repeated, until all remainings fail；
In the step 1), each remaining module is the concrete function to be realized in each remaining of user, by
House dog submodule is added on the basis of original subscriber's desired function to realize；House dog submodule is the band that FPGA development environments provide
There is the IP kernel of watchdog function, watchdog reset signal is carried, if certain remaining module is not within a certain period of time by house dog
Reset signal is set to effectively, then watchdog reset time-out, is shown that the function that the remaining is realized breaks down, is needed to carry out remaining
Switching；
In the step 2), the remaining switching table includes the dispatching priority of total remaining number N and each remaining, adjusts
Spend initial address and timeout parameter；Dispatching priority refers to the priority that the remaining is scheduled in all remaining modules, scheduling
Initial address refers to the initial address that the corresponding FPGA configuration data of remaining module stores in configuring chip, and timeout parameter refers to this
Remaining module how long in without reset house dog then show that the remaining function has broken down, need to call more than other
Spend module；The determination for dispatching initial address should be using priority and configuration data length as foundation, and the scheduling of high priority remaining rises
Beginning address should be less than the scheduling initial address of low priority remaining, and the difference of two neighboring remaining scheduling initial address should be greater than
The configuration data length of high priority remaining in two remainings；The scheduling initial address of highest priority remaining in remaining switching table
It is not 0, and the address should be greater than the length of remaining handover module FPGA configuration data in step 3).
Wherein, in the step 3), the remaining handover module is the main control module for carrying out remaining scheduling comprising reconstruct
Three submodules are dispatched with house dog control, remaining data storage and remaining；Wherein reconstruct and house dog control submodule are
The IP kernel with reconstruct and watchdog function that FPGA programmed environments provide, remaining data storage is for storing remaining switching table
In the dispatching priorities of all remainings, scheduling initial address and timeout parameter data, and be each provided with 1 bit for each remaining
Space, the effective status current for recording the remaining are read and write, remaining dispatches submodule and changes remaining according to remaining fault condition
Remaining effective status in data storage, and more than each remaining effective status progress according to remaining dispatching priority and after changing
Degree selection configures reconstruct and house dog control submodule according to selected remaining parameter, enables FPGA reconstruct；Utilize FPGA
The scheduling that the remaining handover module FPGA configuration data length of environment generation is less than highest priority remaining in remaining switching table rises
Beginning address.
Wherein, in the step 4), it is to configure text using the FPGA that FPGA development environments provide that the configuration data, which is integrated,
The remaining handover module that part crossover tool will generate in each remaining module FPGA configuration data and step 3) that are generated in step 1)
FPGA configuration data is integrated, and is integrated into a FPGA configuration chip programming file and FPGA configuration chips are written；In data
When integration, it is 0 to specify initial address of the remaining handover module configuration data in configuring chip, and each remaining module configuration data exists
The initial address stored in configuration chip is consistent with each remaining scheduling initial address finally determined in step 2).
Wherein, in the step 5), the remaining handover module configures house dog, dispatches remaining module, specifically exists
Acquiescence reads configuration data from the address 0 in configuration chip when FPGA is powered on, if the remaining scheduled in remaining scheduler module exists
Remaining switching table does not carry out reset operation in the specified time to house dog, and FPGA is reconstructed automatically, configures FPGA to remaining
The function of handover module；When remaining handover module is run, remaining dispatches submodule and controls son by reconstruct and house dog first
Module reads the configuration data initial address of last time reconstruct, if the address is not 0, by the ground in remaining data storage
The corresponding remaining in location is set in vain, is shown that the remaining function has occurred and that failure, will be no longer scheduled before next FPGA is powered on；
If the address is 0, shows that current state is to carry out remaining scheduling for the first time after the power is turned in FPGA, set in vain without carrying out remaining
Operation；After the completion of above step, remaining scheduling submodule reads remaining data from remaining data storage, and selection has
Then effective remaining of highest priority records the scheduling initial address and timeout parameter of the remaining, scheduling initial address is write
Enter reconstruct and house dog control submodule, and the overtime timer threshold value of house dog, enabled house dog specified according to timeout parameter,
Finally by reconstruct and the enabled reconstruct of house dog control submodule.
Wherein, in the step 6), the specified remaining module configuration data configuration FPGA of the use is simultaneously run, specifically
It is after the enabled reconstruct of step 5), FPGA reads the configuration number stored in configuration chip from specified scheduling initial address automatically
According to carrying out itself reconstruct, FPGA is configured to designate the function of remaining module later, and reconstructs completion and automatically reset operation；
Under normal condition, which can reset house dog within the scheduling switching table specified time, and FPGA will not be reconstructed；Work as failure
When generation, which will cause watchdog reset overtime without completion data transmit-receive and processing before the deadline,
FPGA can read configuration data from the address 0 of configuration chip, automatic to reconstruct.
(3) advantageous effect
The redundance implementation method for the FPGA based on reconstruct that above-mentioned technical proposal is provided realizes list using reconstruct mode
The redundance of FPGA avoids the increase of FPGA hardware cost compared with non-reconstruct mode, reduces the transmission to input data
Protocol requirement increases the flexibility of system design, makes user that can establish more structurally sound multiplicated system.
Description of the drawings
Fig. 1 be the FPGA the present invention is based on reconstruct redundance implementation method in remaining handover module schematic diagram.
Fig. 2 be the FPGA the present invention is based on reconstruct redundance implementation method in remaining module diagram.
Fig. 3 be the FPGA the present invention is based on reconstruct redundance implementation method in remaining handover module and remaining module operation
Flow chart.
Specific implementation mode
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the tool of the present invention
Body embodiment is described in further detail.
In order to solve the technical problems existing in the prior art, the FPGA redundances provided by the invention based on reconstruct are realized
Method includes the following steps：
Step 1) generates each remaining module FPGA configuration data, counts configuration data length, determines timeout parameter；
Specifically, each remaining module is the concrete function to be realized in each remaining of user, by it is expected in original subscriber
House dog submodule is added on the basis of function to realize；House dog submodule is the offer of FPGA development environments with house dog work(
The IP kernel of energy carries watchdog reset signal, if certain remaining module does not within a certain period of time set watchdog reset signal
To be effective, then watchdog reset time-out, shows that the function that the remaining is realized breaks down, needs to carry out remaining switching；User
Each remaining module FPGA configuration data is generated using FPGA development environments, counts configuration data length, and according to each remaining
Concrete function and application environment determine timeout parameter.
Step 2) establishes remaining switching table according to the statistical data of step 1)；
Specifically, remaining switching table include total remaining number N and each remaining dispatching priority, scheduling initial address and
Timeout parameter；Dispatching priority refers to the priority that the remaining is scheduled in all remaining modules, and scheduling initial address refers to this
The initial address that the corresponding FPGA configuration data of remaining module stores in configuring chip, timeout parameter refer to the remaining module more
Then show that the remaining function has broken down without resetting house dog in long-time, needs to call other remaining modules；Scheduling
The determination of initial address should be using priority and configuration data length as foundation, and the scheduling initial address of high priority remaining should be less than
The scheduling initial address of low priority remaining, and the difference of two neighboring remaining scheduling initial address should be greater than height in two remainings
The configuration data length of priority remaining；The scheduling initial address of highest priority remaining not should be 0 in remaining switching table, and should
Address should be greater than the length of remaining handover module FPGA configuration data in step 3), specifically can configure number according to FPGA in step 3)
According to being adjusted after generation.
Step 3) sets up remaining handover module according to remaining switching table, generates remaining handover module FPGA configuration data；
Specifically, remaining handover module be carry out remaining scheduling main control module, the module by reconstruct and house dog control,
Remaining data storage and remaining dispatch three sub- module compositions, wherein reconstruct and house dog control submodule are FPGA programming rings
The IP kernel with reconstruct and watchdog function that border provides, remaining data storage is for storing all remainings in remaining switching table
Dispatching priority, scheduling initial address and timeout parameter data, and the read-write space for being each provided with for each remaining 1 bit is used
In recording the current effective status of the remaining, remaining is dispatched submodule and is changed in remaining data storage according to remaining fault condition
Remaining effective status, and according to remaining dispatching priority and change after each remaining effective status carry out remaining selection, according to
Selected remaining parameter configures reconstruct and house dog control submodule, enables FPGA reconstruct；Utilize FPGA environment generations
Remaining handover module FPGA configuration data length should be less than the scheduling initial address of highest priority remaining in remaining switching table, no
It then answers the remaining switching table established in set-up procedure 2 and stored phase in 3 remaining data storages is changed the step according to the table
Close data.
Step 4) configuration data integrates programming；
Specifically, the FPGA configuration file crossover tool provided using FPGA development environments is each remaining by what is generated in step 1)
The remaining handover module FPGA configuration data generated in degree module FPGA configuration data and step 3) is integrated, and is integrated into one
FPGA configures chip programming file and FPGA configuration chips is written；In Data Integration, remaining handover module should be specified to configure number
It is 0 according to the initial address in configuring chip, the initial address and step that each remaining module configuration data stores in configuring chip
It is rapid 2) in finally determine each remaining scheduling initial address it is consistent.
Step 5) remaining handover module configures house dog, dispatches remaining module；
Specifically, when FPGA is powered on, acquiescence reads configuration data from the address 0 in configuration chip, i.e. FPGA is configured as
The function of remaining handover module, if the remaining scheduled in remaining scheduler module is no pair within the time that remaining switching table is specified
House dog carries out reset operation, and FPGA can also be reconstructed automatically, configure FPGA to the function of remaining handover module；Switch in remaining
When module is run, remaining dispatches the configuration data that submodule reads last time reconstruct by reconstructing with house dog control submodule first
The corresponding remaining in the address is set in vain in remaining data storage, shows if the address is not 0 by initial address
The remaining function has occurred and that failure, will no longer be scheduled before next FPGA is powered on；If the address is 0, show current shape
State is to carry out remaining scheduling for the first time after the power is turned in FPGA, and invalid operation is set without carrying out remaining.After the completion of above step,
Remaining scheduling submodule reads remaining data from remaining data storage, selects effective remaining with highest priority, so
Scheduling initial address write-in reconstruct and house dog are controlled submodule by the scheduling initial address and timeout parameter for recording the remaining afterwards
Block, and the overtime timer threshold value of house dog, enabled house dog are specified according to timeout parameter, finally by reconstruct and house dog control
The enabled reconstruct of system module.
Step 6) is using specified remaining module configuration data configuration FPGA and runs；
Specifically, after the enabled reconstruct of step 5), FPGA is read from specified scheduling initial address in configuration chip automatically
The configuration data of storage carries out itself reconstruct, and FPGA is configured to designate the function of remaining module later, and it is automatic to reconstruct completion
Reset operation；In normal state, which can reset house dog within the scheduling switching table specified time, and FPGA will not
Reconstruct；When an error occurs, which will lead to house dog without completing data transmit-receive and processing before the deadline
Time-out is resetted, FPGA can read configuration data from the address 0 of configuration chip, automatic to reconstruct.
Step 7) repeats step 5) and arrives step), until all remainings fail；
Specifically, in step 5), remaining handover module carries out remaining scheduling, configures FPGA to the work(of specified remaining
Energy；In step 6), when specified remaining function breaks down, FPGA will be reconstructed into the function of remaining handover module again, return to
Step 5)；System running state will repeat step 5) and step 6), until all remainings break down, i.e., without effective remaining
Degree can be scheduled for.
Based on the technical solution of above-mentioned implementation method, a specific example is provided below, the present invention program is done further
Detailed description
This example chips model and development environment and the IP kernel used first is introduced：Fpga chip selects Altera
The EP3C55 of company, FPGA configure the EPCS128 that chip selects altera corp, and development environment selects Quartus II 10.1.
Two kinds of IP kernels are used altogether, and one is ALTREMOTE_UPDATE, which provides reconstruct and watchdog function；Another kind is RAM：
1-PORT is single port memory, for storing the dispatching priority of all remainings in remaining switching table, scheduling initial address and surpassing
When the data such as parameter.
The application environment of this example is introduced below：This exemplary application is in using the three of the transmission of tri- kinds of agreements of A, B, C
Redundant system, FPGA receive the data from A protocol channels, B protocol channels or C protocol channels, parse initial data and locate
Result is exported after reason.Three channels do not work at the same time, and use A protocol channels to carry out data receiver first, when the channel occurs
B protocol channels are automatically switched to when failure, and C protocol channels are switched to again when B protocol channels break down.That is A protocol channels
Priority is higher than B protocol channels, and the priority of B protocol channels is higher than C protocol channels.Due to the data processing method in three channels
It has differences, when using traditional non-reconstruct single FPGA remaining realization method, resource occupation has been more than total money that FPGA is provided
Source cannot be satisfied design requirement.And can then meet design requirement by the method for the invention, and referring to Fig.1~Fig. 3, case step
It is as follows：
Step 1) generates each remaining module FPGA configuration data, counts configuration data length, determines timeout parameter；This example
In altogether use three remaining modules, A remainings module, B remainings module and C remaining modules.According to concrete application environment, what is determined is super
When parameter be：A remainings are T1, and B remainings are T2, and C remainings are T3.It is that three module additions carry house dog according to timeout parameter
The IP kernel ALTREMOTE_UPDATE of function, and watchdog reset function is added respectively, the reset cycle is less than respective time-out and joins
Number.Three modules are compiled under 10.1 environment of Quartus II later, obtain the configuration data length of three modules：A
Remaining is L1, and B remainings are L2, and C remainings are L3.
Step 2) establishes remaining switching table according to the statistical data of step 1)：Total remaining number is 3, A remaining dispatching priorities
Grade is 1, dispatches initial address M1, timeout parameter T1；B remaining dispatching priorities are 2, dispatch initial address M2, timeout parameter T2；
C remaining module schedules priority is 3, dispatches initial address M3, timeout parameter T3.Ensure M3>M2>M1, and M2-M1>L1, M3-
M2>L2, M1 ≠ 0.
Step 3) sets up remaining handover module according to remaining switching table, generates remaining handover module FPGA configuration data；
Under 10.1 development environments of Quartus II, IP kernel RAM is used：1-PORT builds remaining data storage submodule, uses IP kernel
The reconstruct of ALTREMOTE_UPDATE structures and house dog control submodule dispatch submodule using logic structure remaining, and by IP
Core RAM：1-PORT and IP kernel ALTREMOTE_UPDATE is connected with remaining scheduling submodule respectively.At the beginning of remaining data storage
Beginning value is the dispatching priority i of each remaining, dispatches initial address Mi, timeout parameter Ti and effective status Vi, wherein Vi values
It is 1.Remaining scheduling submodule changes the remaining effective status Vi in remaining data storage according to remaining fault condition, according to
Remaining dispatching priority i carries out remaining selection with each remaining effective status Vi after changing, and according to selected remaining parameter to IP
Core ALTREMOTE_UPDATE is configured, and FPGA reconstruct is enabled；After the completion of remaining handover module is set up, Quartus is utilized
II 10.1 is compiled the module, obtains configuration data length L0, it should be ensured that M1>Otherwise L0 answers set-up procedure 2) in establish
Remaining switching table and stored related data in 3) remaining data storage is changed the step according to the table.
Step 4) configuration data integrates programming；The FPGA configuration file crossover tool provided using Quartus II 10.1
Convert Programming File configure the A remainings module generated in step 1), B remainings module, C remaining modules FPGA
The remaining handover module FPGA configuration data generated in data and step 3) is integrated, and is integrated into a FPGA configuration chip and is burnt
Simultaneously FPGA configuration chips EPCS128 is written by programmable device in written document；In Data Integration, remaining handover module is specified to configure number
It is 0 according to the initial address in configuring chip, the initial address and step that each remaining module configuration data stores in configuring chip
It is rapid 2) in each remaining scheduling initial address Mi for finally determining it is consistent.
Step 5) remaining handover module configures house dog, dispatches remaining module；When FPGA is powered on, from the ground of EPCS128
Location 0 starts to read configuration data, and FPGA is configured as the function of remaining handover module, if remaining scheduled in remaining scheduler module
Degree A, B or C does not carry out reset operation in respectively specified timeout parameter Ti to house dog, and FPGA can also be reconstructed into remaining automatically
Spend the function of handover module；When remaining handover module is run, remaining scheduling submodule passes through IP kernel ALTREMOTE_ first
UPDATE reads the configuration data initial address of last time reconstruct, if address M=Mi (i=1,2,3), then by IP kernel RAM：1-
Vi in PORT is set to 0, shows that the remaining module is invalid.If M=0, without changing the Vi values of each remaining module.Later,
Remaining dispatches submodule from IP kernel RAM：Remaining data are read in 1-PORT, select the highest priority remaining of Vi ≠ 0, record should
IP kernel ALTREMOTE_UPDATE is written in Mi by Mi the and Ti values of remaining, specifies reconstruct initial address, and IP kernel is written in Ti values
ALTREMOTE_UPDATE specifies the overtime timer threshold value of house dog.It is enabled finally by IP kernel ALTREMOTE_UPDATE
House dog enables reconstruct.
Step 6) is using specified remaining module configuration data configuration FPGA and runs；After the enabled reconstruct of step 5),
The configuration data that FPGA is stored from reading EPCS128 from specified scheduling initial address Mi automatically carries out itself reconstruct, later
FPGA is configured as the function of the remaining module；When fault-free occurs, which can reset house dog within the Ti times,
FPGA is not reconstructed；When an error occurs, which can cause FPGA to weigh automatically without resetting house dog within the Ti times
Structure is reconstructed into the function of remaining handover module.
Step 7) repeats step 5) and arrives step 6), until the Vi values of A, B, C remaining module are 0, i.e., all remaining modules
Break down.
The method of the present invention realizes the redundance of single FPGA using reconstruct mode it can be seen from above-mentioned technical proposal, and non-
Reconstruct mode is compared, and the increase of FPGA hardware cost is avoided, and reduces the transport protocol requirement to input data, is increased and is
The flexibility for design of uniting, makes user that can establish more structurally sound multiplicated system；And entire method implementation process is without complexity
Hardware design does not need user and is substantially changed to original remaining function, has stronger practicability.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of FPGA redundance implementation methods based on reconstruct, which is characterized in that include the following steps：
1) each remaining module FPGA configuration data is generated, configuration data length is counted, determines timeout parameter；
2) remaining switching table is established according to the statistical data of step 1)；
3) remaining handover module is set up according to remaining switching table, generates remaining handover module FPGA configuration data；
4) configuration data integrates programming；
5) remaining handover module configures house dog, dispatches remaining module；
6) it configures FPGA using specified remaining module configuration data and runs；
7) step 5) and step 6) are repeated, until all remainings fail；
In the step 1), each remaining module is the concrete function to be realized in each remaining of user, by being used in original
House dog submodule is added on the basis of the desired function of family to realize；House dog submodule is that carrying for FPGA development environments offer is seen
The IP kernel of door dog function, carries watchdog reset signal, if certain remaining module is not within a certain period of time by watchdog reset
Signal is set to effectively, then watchdog reset time-out, shows that the function that the remaining is realized breaks down, progress remaining is needed to cut
It changes；
In the step 2), the remaining switching table includes the dispatching priority of total remaining number N and each remaining, dispatches
Beginning address and timeout parameter；Dispatching priority refers to the priority that the remaining is scheduled in all remaining modules, scheduling starting
Address refers to the initial address that the corresponding FPGA configuration data of remaining module stores in configuring chip, and timeout parameter refers to the remaining
Module how long in without reset house dog then show that the remaining function has broken down, need to call other remaining moulds
Block；The determination for dispatching initial address should be using priority and configuration data length as foundation, the scheduling starting point of high priority remaining
Location should be less than the scheduling initial address of low priority remaining, and the difference of two neighboring remaining scheduling initial address should be greater than two
The configuration data length of high priority remaining in remaining；The scheduling initial address of highest priority remaining is not in remaining switching table
0, and the address should be greater than the length of remaining handover module FPGA configuration data in step 3).
2. the FPGA redundance implementation methods based on reconstruct as described in claim 1, which is characterized in that in the step 3),
The remaining handover module is the main control module for carrying out remaining scheduling comprising reconstruct and house dog control, the storage of remaining data
Device and remaining dispatch three submodules；Wherein reconstruct and house dog control submodule are the offers of FPGA programmed environments with reconstruct
With the IP kernel of watchdog function, remaining data storage is for storing the dispatching priority of all remainings in remaining switching table, adjusting
Initial address and timeout parameter data are spent, and are each provided with the read-write space of 1 bit for each remaining, are worked as recording the remaining
Preceding effective status, remaining dispatch submodule according to the effective shape of remaining in remaining fault condition change remaining data storage
State, and each remaining effective status according to remaining dispatching priority and after changing carries out remaining selection, according to selected remaining parameter
Reconstruct and house dog control submodule are configured, FPGA reconstruct is enabled；Utilize the remaining handover module of FPGA environment generations
FPGA configuration data length is less than the scheduling initial address of highest priority remaining in remaining switching table.
3. the FPGA redundance implementation methods based on reconstruct as claimed in claim 2, which is characterized in that in the step 4),
It is the FPGA configuration file crossover tool provided using FPGA development environments that the configuration data, which is integrated, to be generated in step 1)
The remaining handover module FPGA configuration data generated in each remaining module FPGA configuration data and step 3) is integrated, and is integrated into
One FPGA configures chip programming file and FPGA configuration chips is written；In Data Integration, remaining handover module configuration is specified
Initial address of the data in configuring chip is 0, initial address that each remaining module configuration data stores in configure chip and
Each remaining scheduling initial address finally determined in step 2) is consistent.
4. the FPGA redundance implementation methods based on reconstruct as claimed in claim 3, which is characterized in that in the step 5),
The remaining handover module configures house dog, dispatches remaining module, specifically gives tacit consent to when FPGA is powered on from configuration chip
Configuration data is read in address 0, if the remaining scheduled in remaining scheduler module is no pair within the time that remaining switching table is specified
House dog carries out reset operation, and FPGA is reconstructed automatically, configures FPGA to the function of remaining handover module；In remaining handover module
When operation, remaining is dispatched submodule and is originated first by the configuration data reconstructed and house dog control submodule reading last time reconstructs
The corresponding remaining in the address is set in vain in remaining data storage if the address is not 0, shows that this is remaining by address
Degree function has occurred and that failure, will no longer be scheduled before next FPGA is powered on；If the address is 0, show that current state is
Remaining scheduling is carried out for the first time after the power is turned in FPGA, and invalid operation is set without carrying out remaining；After the completion of above step, remaining
Scheduling submodule reads remaining data from remaining data storage, selects effective remaining with highest priority, then remembers
The scheduling initial address and timeout parameter for recording the remaining, by scheduling initial address write-in reconstruct and house dog control submodule, and
The overtime timer threshold value of house dog, enabled house dog are specified according to timeout parameter, son is controlled finally by reconstruct and house dog
The enabled reconstruct of module.
5. the FPGA redundance implementation methods based on reconstruct as claimed in claim 4, which is characterized in that in the step 6),
The specified remaining module configuration data configuration FPGA of the use is simultaneously run, specifically after the enabled reconstruct of step 5), FPGA
Automatically the configuration data stored in configuration chip is read from specified scheduling initial address, carries out itself reconstruct, later FPGA quilts
It is configured to the function of specified remaining module, and reconstructs completion and automatically resets operation；In normal state, which can adjust
It spends in the switching table specified time and resets house dog, FPGA will not be reconstructed；When an error occurs, which is not providing
Time in complete data transmit-receive and processing, watchdog reset will be caused overtime, FPGA can be read from the address 0 of configuration chip match
Data are set, it is automatic to reconstruct.
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| CN110535788B (en) * | 2019-07-12 | 2021-09-10 | 中国人民解放军战略支援部队信息工程大学 | Multi-protocol controller and multi-protocol exchange chip |
| CN110928217A (en) * | 2019-11-18 | 2020-03-27 | 天津津航计算技术研究所 | CPU (Central processing Unit) triple-redundancy voting circuit applied to aviation electric heating control system |
| CN111679927A (en) * | 2020-05-29 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | Fault-tolerant computer of redundancy reconsitution |
| CN112578723B (en) * | 2020-12-07 | 2022-09-13 | 天津津航计算技术研究所 | Redundancy CPLD switching control device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576836A (en) * | 2009-06-12 | 2009-11-11 | 北京航空航天大学 | Degradable three-machine redundancy fault-tolerant system |
| CN101833536A (en) * | 2010-04-16 | 2010-09-15 | 北京航空航天大学 | Reconfigurable on-board computer of redundancy arbitration mechanism |
| CN103440171A (en) * | 2013-08-25 | 2013-12-11 | 浙江大学 | Realization method of real-time operating system of component-based hardware |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7971051B2 (en) * | 2007-09-27 | 2011-06-28 | Fujitsu Limited | FPGA configuration protection and control using hardware watchdog timer |
-
2015
- 2015-11-05 CN CN201510744148.0A patent/CN105354381B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576836A (en) * | 2009-06-12 | 2009-11-11 | 北京航空航天大学 | Degradable three-machine redundancy fault-tolerant system |
| CN101833536A (en) * | 2010-04-16 | 2010-09-15 | 北京航空航天大学 | Reconfigurable on-board computer of redundancy arbitration mechanism |
| CN103440171A (en) * | 2013-08-25 | 2013-12-11 | 浙江大学 | Realization method of real-time operating system of component-based hardware |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的星载机容错技术研究与设计;郭林;《中国优秀硕士学位论文全文数据库 工程科技II辑》;20111215(第S2期);摘要、正文第21-37,44页 * |
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