CN105354381A - Reconstruction-based FPGA multi-redundancy implementation method - Google Patents
Reconstruction-based FPGA multi-redundancy implementation method Download PDFInfo
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Abstract
The present invention discloses a reconstruction-based FPGA multi-redundancy implementation method. The method comprises: firstly, generating FPGA configuration data of each redundancy module; collecting statistics on the length of configuration data and determining a timeout parameter; then establishing a redundancy switching table, and building a redundancy switching module according to the table; generating FPGA configuration data of the redundancy switching module; then, after integrating the configuration data, programming the configuration data into an FPGA configuration chip; the redundancy switching module configuring a watchdog and performing redundancy scheduling according to the redundancy switching table; using configuration data of a specified redundancy module to configure an FPGA and running the FPGA; and when the selected redundancy is faulty, returning to the redundancy switching module to select a redundancy until all redundancies fail. According to the method disclosed by the present invention, multi-redundancy of a single FPGA is achieved by using a reconstruction method; compared with a non-reconstruction method, an increase in FPGA hardware costs is avoided, a requirement on a transport protocol of input data is reduced, and flexibility of system design is increased, so that a user can build a more reliable multi-redundancy system.
Description
Technical field
The invention belongs to FPGA redundance and realize field, relate to a kind of FPGA redundance implementation method based on reconstruct.
Background technology
Redundancy technology is a kind of important means improving system works reliability, because FPGA has good customizability, can meet diversified remaining and switch demand, therefore be widely applied in multiplicated system.Traditional multiplicated system based on FPGA adopts single FPGA or many FPGA two kinds of implementations of non-reconstruct, wherein simultaneously single FPGA implementation multichannel is adopted the data of identical or similar protocol transmission to send in FPGA, and FPGA carries out correction judgement to each circuit-switched data and carries out Systematical control and data selection accordingly.Many FPGA implementation is then that the fpga chip of employing 2 or more forms hardware redundancy, automatically switches to another FPGA when certain FPGA operation irregularity, thus the normal work of the system of guarantee.
Above two kinds of implementations reach the object improving system reliability, meet the redundancy design demand of system to a certain extent, but there is following problem: single FPGA implementation requires the same or similar host-host protocol of data acquisition of input, if host-host protocol is different, then FPGA needs to set up different hardware processing logic for often kind of agreement, thus need more massive FPGA and configuring chip, increase hardware cost; Many FPGA implementation not only increases hardware cost, also adds the failure rate of system to a certain extent due to the introducing of control and decision logic between FPGA.
Summary of the invention
(1) goal of the invention
The object of the invention is: the increase of hardware cost in realizing for avoiding FPGA redundance, increases the dirigibility of system, provides a kind of FPGA redundance implementation method based on reconstruct.
(2) technical scheme
In order to solve the problems of the technologies described above, the invention provides one
(3) beneficial effect
The redundance implementation method of the FPGA based on reconstruct that technique scheme provides, reconstruct mode is adopted to realize the redundance of single FPGA, compared with non-reconstruct mode, avoid the increase of FPGA hardware cost, reduce the host-host protocol requirement to input data, add the dirigibility of system, make user can set up more reliable multiplicated system.
Accompanying drawing explanation
Fig. 1 is remaining handover module schematic diagram in the redundance implementation method of the FPGA that the present invention is based on reconstruct.
Fig. 2 is remaining module diagram in the redundance implementation method of the FPGA that the present invention is based on reconstruct.
Fig. 3 is remaining handover module and remaining module operational flow diagram in the redundance implementation method of the FPGA that the present invention is based on reconstruct.
Embodiment
For making object of the present invention, content and advantage clearly, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
In order to solve the technical matters existed in prior art, the FPGA redundance implementation method based on reconstruct provided by the invention, comprises the following steps:
Step 1) generate each remaining module FPGA configuration data, statistics configuration data length, determines timeout parameter;
Particularly, each remaining module is the concrete function that user will realize in each remaining, realizes by adding house dog submodule on the basis of original subscriber's desired function; House dog submodule is the IP kernel with watchdog function that FPGA development environment provides, with watchdog reset signal, if watchdog reset signal is not set to effectively by certain remaining module within a certain period of time, then watchdog reset time-out, show that the function that this remaining realizes breaks down, need to carry out remaining switching; User utilizes FPGA development environment to generate each remaining module FPGA configuration data, statistics configuration data length, and according to the concrete function of each remaining and applied environment determination timeout parameter.
Step 2) according to step 1) statistics set up remaining switching table;
Particularly, remaining switching table comprises dispatching priority, the scheduling start address and timeout parameter of total remaining number N and each remaining; Dispatching priority refers to the priority that this remaining is scheduled in all remaining modules, scheduling start address refers to the start address that FPGA configuration data corresponding to this remaining module stores in configuring chip, timeout parameter refers to that this remaining module house dog that do not reset in how long then shows that this remaining function breaks down, and needs to call other remaining modules; The determination of scheduling start address should with priority and configuration data length for foundation, the scheduling start address of high priority remaining should be less than the scheduling start address of low priority remaining, and the difference of adjacent two remainings scheduling start address should be greater than the configuration data length of high priority remaining in two remainings; In remaining switching table, the scheduling start address of limit priority remaining not should be 0, and this address should be greater than step 3) in the length of remaining handover module FPGA configuration data, specifically can according to step 3) in FPGA configuration data generate laggard Row sum-equal matrix.
Step 3) set up remaining handover module according to remaining switching table, generate remaining handover module FPGA configuration data;
Particularly, remaining handover module is the main control module carrying out remaining scheduling, this module controls with house dog by reconstructing, remaining data-carrier store and remaining dispatch three sub-module compositions, wherein reconstruct and house dog control submodule be FPGA programmed environment provide with reconstructing and the IP kernel of watchdog function, remaining data-carrier store is for storing the dispatching priority of all remainings in remaining switching table, scheduling start address and timeout parameter data, and all provide the read-write space of 1 bit for recording the current effective status of this remaining for each remaining, remaining scheduling sublayer module changes the remaining effective status in remaining data-carrier store according to remaining failure condition, and carry out remaining selection according to remaining dispatching priority and each remaining effective status after changing, control submodule according to selected remaining parameter to reconstruct and house dog to be configured, enable FPGA reconstruct, utilize the remaining handover module FPGA configuration data length of FPGA environment generation should be less than the scheduling start address of limit priority remaining in remaining switching table, otherwise answer the remaining switching table of foundation in set-up procedure 2 and change the related data stored in step 3 remaining data-carrier store according to this table.
Step 4) configuration data integration programming;
Particularly, the FPGA configuration file crossover tool utilizing FPGA development environment to provide is by step 1) in generate each remaining module FPGA configuration data and step 3) in generate remaining handover module FPGA configuration data integrate, be integrated into a FPGA configuring chip programming file and write FPGA configuring chip; When Data Integration, the start address of remaining handover module configuration data in configuring chip should be specified to be 0, the start address that each remaining module configuration data stores in configuring chip and step 2) in each remaining of finally determining to dispatch start address consistent.
Step 5) remaining handover module configuration house dog, scheduling remaining module;
Particularly, when FPGA powers on, acquiescence reads configuration data from the address 0 configuring chip, namely FPGA is configured to the function of remaining handover module, if the remaining that remaining scheduler module is dispatched does not carry out reset operation to house dog within the time that remaining switching table is specified, FPGA also can automatic reconfiguration, FPGA is configured to the function of remaining handover module; When remaining handover module runs, first remaining scheduling sublayer module controls by reconstruct and house dog the configuration data start address that submodule reads reconstruct last time, if this address is not 0, it is invalid then remaining corresponding for this address to be set in remaining data-carrier store, show that this remaining function breaks down, will no longer be scheduled before next FPGA powers on; If this address is 0, shows that current state carries out remaining scheduling for the first time after FPGA powers on, putting invalid operation without the need to carrying out remaining.After above step completes, remaining scheduling sublayer module reads remaining data from remaining data-carrier store, select effective remaining with limit priority, then scheduling start address and the timeout parameter of this remaining is recorded, start address write reconstruct and house dog control submodule will be dispatched, and specify the overtime timer threshold value of house dog, enable house dog according to timeout parameter, control the enable reconstruct of submodule finally by reconstruct and house dog.
Step 6) use the remaining module configuration data of specifying configure FPGA and run;
Particularly, in step 5) after enable reconstruct, FPGA reads from the scheduling start address of specifying the configuration data stored configuring chip automatically, carries out self reconstruct, and FPGA is configured to the function of specifying remaining module afterwards, and has reconstructed the operation that automatically resets; In normal state, this remaining module can reset house dog within scheduling switching table time of specifying, and FPGA can not reconstruct; When an error occurs, this remaining module does not complete data transmit-receive and process in official hour, and will cause watchdog reset time-out, FPGA can read configuration data, automatic reconfiguration from the address 0 of configuring chip.
Step 7) repeat step 5) to step), until all remainings lost efficacy;
Particularly, in step 5) in, remaining handover module carries out remaining scheduling, FPGA is configured to the function of specifying remaining; In step 6) in, when specifying remaining function to break down, FPGA, by being again reconstructed into the function of remaining handover module, gets back to step 5); System running state will repeat step 5) and step 6), until all remainings all break down, namely do not have effective remaining to supply scheduling.
Based on the technical scheme of above-mentioned implementation method, a concrete example is provided to do further detailed description to the present invention program below
First the IP kernel of this example chips model and development environment and use is introduced: fpga chip selects the EP3C55 of altera corp, and FPGA configuring chip selects the EPCS128 of altera corp, and development environment selects QuartusII10.1.Use two kinds of IP kernels altogether, one is ALTREMOTE_UPDATE, and this IP kernel provides reconstruct and watchdog function; Another kind is RAM:1-PORT, is single port storer, for storing dispatching priority, the data such as scheduling start address and timeout parameter etc. of all remainings in remaining switching table.
Below the applied environment of this example is introduced: this exemplary application is in the triplex redundance system adopting A, B, C tri-kinds of protocol transmission, FPGA receives the data from A protocol channel, B protocol channel or C protocol channel, parses raw data and result is exported after process.Work when three passages are different, first uses A protocol channel to carry out data receiver, automatically switches to B protocol channel, be switched to C protocol channel again when B protocol channel breaks down when this passage breaks down.Namely the priority of A protocol channel is higher than B protocol channel, and the priority of B protocol channel is higher than C protocol channel.Because the data processing method of three passages there are differences, when adopting traditional non-reconstruct single FPGA remaining implementation, resource occupation has exceeded the total resources that FPGA provides, and cannot meet design requirement.Then can meet design requirement by the inventive method, with reference to Fig. 1 ~ Fig. 3, case step is as follows:
Step 1) generate each remaining module FPGA configuration data, statistics configuration data length, determines timeout parameter; Three remaining modules are used altogether, A remaining module, B remaining module and C remaining module in this example.According to embody rule environment, the timeout parameter determined is: A remaining is T1, B remaining be T2, C remaining is T3.According to timeout parameter, be the IP kernel ALTREMOTE_UPDATE that three modules add with watchdog function, and add watchdog reset function respectively, the reset cycle is less than respective timeout parameter.Under QuartusII10.1 environment, three modules are compiled afterwards, obtain the configuration data length of three modules: A remaining is L1, B remaining be L2, C remaining is L3.
Step 2) according to step 1) statistics set up remaining switching table: total remaining number is 3, A remaining dispatching priority is 1, scheduling start address M1, timeout parameter T1; B remaining dispatching priority is 2, scheduling start address M2, timeout parameter T2; C remaining module schedules priority is 3, scheduling start address M3, timeout parameter T3.Guarantee M3>M2>M1, and M2-M1>L1, M3-M2>L2, M1 ≠ 0.
Step 3) set up remaining handover module according to remaining switching table, generate remaining handover module FPGA configuration data; Under QuartusII10.1 development environment, IP kernel RAM:1-PORT is used to build remaining data-carrier store submodule, IP kernel ALTREMOTE_UPDATE is used to build reconstruct and house dog control submodule, use logic to build remaining scheduling sublayer module, and IP kernel RAM:1-PORT is connected with remaining scheduling sublayer module respectively with IP kernel ALTREMOTE_UPDATE.The initialization value of remaining data-carrier store is the dispatching priority i of each remaining, and scheduling start address Mi, timeout parameter Ti and effective status Vi, wherein Vi value is 1.Remaining scheduling sublayer module changes the remaining effective status Vi in remaining data-carrier store according to remaining failure condition, remaining selection is carried out according to remaining dispatching priority i and each remaining effective status Vi after changing, and according to selected remaining parameter, IP kernel ALTREMOTE_UPDATE is configured, enable FPGA reconstruct; After remaining handover module has been set up, QuartusII10.1 is utilized to compile this module, obtain configuration data length L0, should M1>L0 be guaranteed, otherwise answer set-up procedure 2) in the remaining switching table set up and change step 3 according to this table) related data that stored in remaining data-carrier store.
Step 4) configuration data integration programming; The FPGA configuration file crossover tool ConvertProgrammingFile utilizing QuartusII10.1 to provide is by step 1) in generate A remaining module, B remaining module, C remaining module FPGA configuration data and step 3) in the remaining handover module FPGA configuration data that generates integrate, be integrated into a FPGA configuring chip programming file and by programmable device write FPGA configuring chip EPCS128; When Data Integration, specify the start address of remaining handover module configuration data in configuring chip to be 0, the start address that each remaining module configuration data stores in configuring chip and step 2) in each remaining of finally determining to dispatch start address Mi consistent.
Step 5) remaining handover module configuration house dog, scheduling remaining module; When FPGA powers on, configuration data is read from the address 0 of EPCS128, FPGA is configured to the function of remaining handover module, if remaining A, B or C that remaining scheduler module is dispatched do not carry out reset operation to house dog in the timeout parameter Ti specified separately, FPGA can automatic reconfiguration be also the function of remaining handover module; When remaining handover module runs, first remaining scheduling sublayer module reads the configuration data start address of reconstruct last time by IP kernel ALTREMOTE_UPDATE, if this address M=Mi (i=1,2,3), then the Vi in IP kernel RAM:1-PORT is set to 0, shows that this remaining module is invalid.If M=0, then without the need to changing the Vi value of each remaining module.Afterwards, remaining scheduling sublayer module reads remaining data from IP kernel RAM:1-PORT, select the limit priority remaining of Vi ≠ 0, record Mi and the Ti value of this remaining, Mi is write IP kernel ALTREMOTE_UPDATE, specify reconstruct start address, by Ti value write IP kernel ALTREMOTE_UPDATE, specify the overtime timer threshold value of house dog.Finally by the enable house dog of IP kernel ALTREMOTE_UPDATE, enable reconstruct.
Step 6) use the remaining module configuration data of specifying configure FPGA and run; In step 5) after enable reconstruct, FPGA automatically reads from the scheduling start address Mi specified the configuration data stored in EPCS128 and carries out self reconstruct, and FPGA is configured to the function of this remaining module afterwards; When non-fault occurs, this remaining module can reset house dog within the Ti time, and FPGA does not reconstruct; When an error occurs, this remaining module does not reset house dog within the Ti time, can cause FPGA automatic reconfiguration, be reconstructed into the function of remaining handover module.
Step 7) repeat step 5) to step 6), until the Vi value of A, B, C remaining module is 0, namely all remaining modules all break down.
As can be seen from technique scheme, the inventive method adopts reconstruct mode to realize the redundance of single FPGA, compared with non-reconstruct mode, avoid the increase of FPGA hardware cost, reduce the host-host protocol requirement to input data, add the dirigibility of system, make user can set up more reliable multiplicated system; And whole method implementation process is without the need to the hardware design of complexity, does not need user significantly to change original remaining function, there is stronger practicality.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and distortion, these improve and distortion also should be considered as protection scope of the present invention.
Claims (7)
1., based on a FPGA redundance implementation method for reconstruct, it is characterized in that, comprise the following steps:
1) generate each remaining module FPGA configuration data, statistics configuration data length, determines timeout parameter;
2) according to step 1) statistics set up remaining switching table;
3) set up remaining handover module according to remaining switching table, generate remaining handover module FPGA configuration data;
4) configuration data integrates programming;
5) remaining handover module configuration house dog, scheduling remaining module;
6) use the remaining module configuration data configuration FPGA specified and run;
7) step 5 is repeated) and step 6), until all remainings lost efficacy.
2. as claimed in claim 1 based on the FPGA redundance implementation method of reconstruct, it is characterized in that, described step 1) in, described each remaining module is the concrete function that user will realize in each remaining, realizes by adding house dog submodule on the basis of original subscriber's desired function; House dog submodule is the IP kernel with watchdog function that FPGA development environment provides, with watchdog reset signal, if watchdog reset signal is not set to effectively by certain remaining module within a certain period of time, then watchdog reset time-out, show that the function that this remaining realizes breaks down, need to carry out remaining switching.
3., as claimed in claim 2 based on the FPGA redundance implementation method of reconstruct, it is characterized in that, described step 2) in, described remaining switching table comprises the dispatching priority of total remaining number N and each remaining, scheduling start address and timeout parameter; Dispatching priority refers to the priority that this remaining is scheduled in all remaining modules, scheduling start address refers to the start address that FPGA configuration data corresponding to this remaining module stores in configuring chip, timeout parameter refers to that this remaining module house dog that do not reset in how long then shows that this remaining function breaks down, and needs to call other remaining modules; The determination of scheduling start address should with priority and configuration data length for foundation, the scheduling start address of high priority remaining should be less than the scheduling start address of low priority remaining, and the difference of adjacent two remainings scheduling start address should be greater than the configuration data length of high priority remaining in two remainings; In remaining switching table, the scheduling start address of limit priority remaining is not 0, and this address should be greater than step 3) in the length of remaining handover module FPGA configuration data.
4. as claimed in claim 3 based on the FPGA redundance implementation method of reconstruct, it is characterized in that, described step 3) in, described remaining handover module is the main control module carrying out remaining scheduling, and it comprises reconstruct and house dog control, remaining data-carrier store and remaining dispatch three submodules, wherein reconstruct and house dog control submodule be FPGA programmed environment provide with reconstructing and the IP kernel of watchdog function, remaining data-carrier store is for storing the dispatching priority of all remainings in remaining switching table, scheduling start address and timeout parameter data, and be the read-write space that each remaining all provides 1 bit, for recording the current effective status of this remaining, remaining scheduling sublayer module changes the remaining effective status in remaining data-carrier store according to remaining failure condition, and carry out remaining selection according to remaining dispatching priority and each remaining effective status after changing, control submodule according to selected remaining parameter to reconstruct and house dog to be configured, enable FPGA reconstruct, the remaining handover module FPGA configuration data length of FPGA environment generation is utilized to be less than the scheduling start address of limit priority remaining in remaining switching table.
5. as claimed in claim 4 based on the FPGA redundance implementation method of reconstruct, it is characterized in that, described step 4) in, described configuration data integrate be utilize FPGA development environment to provide FPGA configuration file crossover tool by step 1) in each remaining module FPGA configuration data of generating and step 3) in the remaining handover module FPGA configuration data that generates integrate, be integrated into a FPGA configuring chip programming file and write FPGA configuring chip; When Data Integration, specify the start address of remaining handover module configuration data in configuring chip to be 0, the start address that each remaining module configuration data stores in configuring chip and step 2) in each remaining of finally determining to dispatch start address consistent.
6. as claimed in claim 5 based on the FPGA redundance implementation method of reconstruct, it is characterized in that, described step 5) in, described remaining handover module configuration house dog, scheduling remaining module, specifically when FPGA powers on, acquiescence reads configuration data from the address 0 configuring chip, if the remaining that remaining scheduler module is dispatched does not carry out reset operation to house dog within the time that remaining switching table is specified, FPGA automatic reconfiguration, is configured to the function of remaining handover module by FPGA; When remaining handover module runs, first remaining scheduling sublayer module controls by reconstruct and house dog the configuration data start address that submodule reads reconstruct last time, if this address is not 0, it is invalid then remaining corresponding for this address to be set in remaining data-carrier store, show that this remaining function breaks down, will no longer be scheduled before next FPGA powers on; If this address is 0, shows that current state carries out remaining scheduling for the first time after FPGA powers on, putting invalid operation without the need to carrying out remaining; After above step completes, remaining scheduling sublayer module reads remaining data from remaining data-carrier store, select effective remaining with limit priority, then scheduling start address and the timeout parameter of this remaining is recorded, start address write reconstruct and house dog control submodule will be dispatched, and specify the overtime timer threshold value of house dog, enable house dog according to timeout parameter, control the enable reconstruct of submodule finally by reconstruct and house dog.
7. as claimed in claim 6 based on the FPGA redundance implementation method of reconstruct, it is characterized in that, described step 6) in, the remaining module configuration data configuration FPGA that described use is specified also runs, specifically in step 5) after enable reconstruct, FPGA reads from the scheduling start address of specifying the configuration data stored configuring chip automatically, carries out self reconstruct, FPGA is configured to the function of specifying remaining module afterwards, and has reconstructed the operation that automatically resets; In normal state, this remaining module can reset house dog within scheduling switching table time of specifying, and FPGA can not reconstruct; When an error occurs, this remaining module does not complete data transmit-receive and process in official hour, and will cause watchdog reset time-out, FPGA can read configuration data, automatic reconfiguration from the address 0 of configuring chip.
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