CN109902061B

CN109902061B - Digital logic circuit and microprocessor

Info

Publication number: CN109902061B
Application number: CN201910108983.3A
Authority: CN
Inventors: 汪泳江
Original assignee: Xuanzhi Electronic Technology Shanghai Co ltd
Current assignee: Xuanzhi Electronic Technology Shanghai Co ltd
Priority date: 2019-02-03
Filing date: 2019-02-03
Publication date: 2023-06-02
Anticipated expiration: 2039-02-03
Also published as: CN109902061A

Abstract

The digital logic circuit combines a programmable logic unit and a data processing unit, and can execute digital logic functions according to programming information by using the programmable logic unit and execute digital logic operations by calling a logic control program by using the data processing unit, so that the advantages of a plane logic control technology based on the programmable logic unit and a time domain logic control technology based on the data processing unit can be exerted, the flexibility of the circuit is improved, the cost is saved, the instantaneity is ensured, and the energy consumption is reduced.

Description

Digital logic circuit and microprocessor

Technical Field

The present application relates to a digital logic circuit and a microprocessor.

Background

Digital logic has a wide range of applications in digital systems, and is indispensable for performing high-speed computation, particularly for signal processing. Particularly in high performance microprocessors, digital signal processors, graphic image systems, scientific computing and certain specific data processing devices.

Conventional digital logic implementations can be divided into two categories: planar logic and time domain methods.

The plane logic method realizes complex logic by using pure logic gates, so that all logic gates can realize parallel operation, and the method has the advantages of high operation speed, high efficiency and the like. However, each logic implementation is designed for a specific logic characteristic and is difficult to reuse. Moreover, if there is an error, the implementation of the entire logic must be redesigned. To overcome the defects of reuse and error repair, a programmable logic device (Programmable Logic Device, abbreviated as PLD) having a programmable function has been developed. The programmable Logic device is produced as a general-purpose integrated circuit, and its Logic function is determined according to the programming of the device by a user, especially, an FPGA chip (Field-Programmable Gate Array, i.e., field programmable gate array) is represented therein, and the FPGA chip contains a large number of Logic units (Logic elements, abbreviated as LE), so that the user can freely combine these Logic units to implement different Logic circuit functions, and when implementing digital Logic, the user can write corresponding results (e.g., the correspondence between input and output) into a storage unit in advance to form a Look-Up Table (LUT), so that different Logic functions are implemented under the same circuit condition, and because the FPGA based on the LUT has very high integration, the device density varies from tens of thousands to thousands of gates, so that the FPGA is suitable for the Field of designing high-speed, high-density high-end digital Logic circuits. However, there are some significant disadvantages to programmable logic devices represented by FPGAs, such as: the digital logic implemented by the FPGA is dependent on the LUT, so that to implement the required digital logic, in practical application, the FPGA may have redundant logic circuits (some parts of some logic units in the FPGA are often not used or may not be used), resulting in high cost and a certain power consumption problem.

The time domain method is to realize digital logic by the time domain method. Taking the most common central processing unit (Central Processing Unit, simply CPU) as an example, the CPU divides the complex logic into many small tasks, and each task can be completed by a certain instruction set(s), so that the complex work can be implemented by software. The method has the advantage that complex work can be completed as long as the CPU speed is high. Further, since logic is implemented using software, logic implementation can be changed by modifying the software. However, the CPU processing requires software interrupt to drive and complete, and is limited by such an architecture, and even if the CPU is fast, there may be problems such as real-time performance when the software runs.

Disclosure of Invention

In view of the foregoing drawbacks of the related art, an object of the present application is to disclose a digital logic circuit and a microprocessor for solving the problems caused by the single digital logic implementation in the related art.

To achieve the above and other objects, a first aspect of the present application discloses a digital logic circuit, comprising:

a multi-path input selecting unit for receiving multi-path input signals and selecting an output path of at least one of the multi-path input signals;

The programmable logic unit is used for receiving the at least one input signal and executing a digital logic function according to programming information when the multi-path input selection unit selects the at least one input signal as a first output path;

the data processing unit is used for receiving the at least one input signal and calling a logic control program to execute digital logic operation when the multi-path input selection unit selects the at least one input signal as a second output path;

a register unit storing at least one of an operation result of the programmable logic unit and an operation result of the data processing unit;

the two-way gating unit is used for outputting a selection signal to selectively connect signals for the programmable logic unit or the data processing unit so that the programmable logic unit or the data processing unit which are connected by the signals can execute operation on the register unit; and

and the multiplexing output selection unit is used for generating multiplexing output signals according to the storage information of the register unit.

In certain embodiments of the first aspect of the present application, the programmable logic unit is a field programmable gate array FPGA or a complex programmable logic device CPLD.

In certain embodiments of the first aspect of the present application, the two-way gating unit includes a plurality of two-way multiplexers, where each of the two-way gating units includes two input terminals, an output terminal, and a control terminal, where the two input terminals are respectively connected to the programmable logic unit and the data processing unit, the output terminal is connected to the register unit, and the control terminal is connected to the control logic unit.

In certain embodiments of the first aspect of the present application, the data processing unit includes: the control and calculation module is connected with the multi-path input selection unit and the two-path gating unit; the instruction storage module is connected with the control and calculation module; and the data storage module is connected with the control and calculation module.

In certain embodiments of the first aspect of the present application, the instruction storage module is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

In certain embodiments of the first aspect of the present application, the data storage module is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

In certain embodiments of the first aspect of the present application, the control and calculation module, the instruction storage module, the data storage module, and the register unit are integrated on the same chip.

In certain embodiments of the first aspect of the present application, the register unit is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

In certain embodiments of the first aspect of the present application, the digital logic circuit further includes a control logic unit, connected to the multiple-input selecting unit and the register unit, for generating a control signal for controlling the two-way gating unit according to at least one of an input signal of the multiple-input selecting unit and stored information of the register unit;

in certain embodiments of the first aspect of the present application, the digital logic circuit further includes a counting unit connected to the control logic unit, so that the control logic unit generates a control signal for controlling the two-way gating unit according to a counting result of the counting unit.

In certain embodiments of the first aspect of the present application, the counting unit comprises a plurality of counters.

In certain embodiments of the first aspect of the present application, the control logic unit is connected to the multiplexing selection unit, and is configured to monitor an output signal of the multiplexing selection unit.

In certain embodiments of the first aspect of the present application, the digital logic circuit further comprises a system clock management unit for generating a system clock signal and transmitting the system clock signal to the data processing unit, the register unit, and the control logic unit.

A second aspect of the present application discloses a microprocessor comprising a digital logic circuit as previously described.

The application discloses a digital logic circuit and a microprocessor with the digital logic circuit, which combine a programmable logic unit and a data processing unit together, so that the advantages of a plane logic control technology based on the programmable logic unit and a time domain logic control technology based on the data processing unit can be exerted, the flexibility of the circuit is improved, the cost is saved, the instantaneity is ensured, and the energy consumption is reduced.

Drawings

Fig. 1 is a schematic diagram of a digital logic circuit according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a digital logic circuit according to another embodiment of the present application.

Fig. 3 is a schematic diagram of a digital logic circuit according to another embodiment of the present application.

Fig. 4 is a schematic diagram of a digital logic circuit according to another embodiment of the present application.

Detailed Description

Further advantages and effects of the present application will be readily apparent to those skilled in the art from the present disclosure, by describing the embodiments of the present application with specific examples.

In the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that compositional and operational changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the patent of the present application. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Although the terms first, second, etc. may be used herein to describe various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first preset threshold may be referred to as a second preset threshold, and similarly, the second preset threshold may be referred to as a first preset threshold, without departing from the scope of the various described embodiments. The first preset threshold and the preset threshold are both described as one threshold, but they are not the same preset threshold unless the context clearly indicates otherwise.

Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.

Digital logic operation has wide application in digital systems, and in general, a planar logic control technology based on a programmable logic device and a time domain logic control technology based on a data processing unit are adopted in a digital logic implementation method, but some defects are generated by adopting a single technology. For example: in the planar logic control technology based on the programmable logic device, the digital logic realized by the programmable logic device depends on the pre-established logic circuit and the programmable information thereof, so that the programmable logic device has a redundant logic circuit, which results in higher cost. In the time domain logic control technology based on the data processing unit, each task is completed sequentially according to time sequence, and the problems of instantaneity and the like exist. In view of this, the applicant creatively envisages a new architecture to realize complete logic, and discloses a digital logic circuit, a microprocessor and a logic processing method, which combine programmable logic devices with data processing units, so as to exert the advantages of the rapid efficiency of parallel logic in planar logic control technology based on the programmable logic devices and the programmability and flexibility in time domain logic control technology based on the data processing units.

Referring to fig. 1, a schematic diagram of a digital logic circuit according to an embodiment of the present application is shown. As shown in fig. 1, the digital logic circuit of the present application may include: a multi-input selecting unit 11, a programmable logic unit 12, a data processing unit 13, a register unit 14, a two-way gating unit 15, and a multi-output selecting unit 16.

The multiple input selecting unit 11 is configured to receive multiple input signals and select an output path of at least one input signal of the multiple input signals. In this embodiment, the multiple-input selecting unit 11 has a plurality of input terminals and at least two output terminals, for example, one output terminal of the multiple-input selecting unit 11 is connected to the programmable logic unit 12, and one output terminal of the multiple-input selecting unit 11 is connected to the data processing unit 13, so that the multiple-input selecting unit 11 receives multiple-input signals and can select a first output path to be output to the programmable logic unit 12 or a second output path to be output to the data processing unit 13 for the received input signals. In practical applications, taking the case that the multiple input selecting unit 11 is selectively connected with the programmable logic unit 12 and the data processing unit 13, the multiple input selecting unit 11 may include a many-to-two switch to realize the switching of the circuits.

The programmable logic unit 12 is connected to the multiple input selection unit 11 for performing a digital logic function on the received input signal. In this embodiment, the programmable logic unit 12 receives the at least one input signal when the multiple input selecting unit 11 selects the at least one input signal as the first output path, and performs a digital logic function according to the programming information.

The programmable logic unit 12 is a programmable logic device (Programmable Logic Device, abbreviated as PLD) having a programmable function. Programmable logic devices are semi-custom logic chips produced by manufacturers as a generic device whose logic functions are determined by user programming of the device, which is essentially an extension and development of gate arrays and standard cell design techniques. In some embodiments, the programmable logic unit 12 may employ a complex programmable logic device (Complex Programmable Logic Device, abbreviated as CPLD). The CPLD chip mainly comprises programmable interconnection matrix units (MC, macro Cell) surrounding the center, wherein the MC structure is complex and has an I/O unit interconnection structure, and a specific circuit structure can be generated by a user according to the needs to complete certain logic functions. In some embodiments, the programmable logic units 12 may employ a Field programmable gate array (Field-Programmable Gate Array, abbreviated as FPGA). The FPGA chip comprises a large number of Logic units (LE for short), a user can realize different Logic circuit functions by freely combining the Logic units, when digital Logic is realized, corresponding results (such as corresponding relation between input and output and the like) are burnt into a storage unit in advance to form a Look-Up Table (LUT for short), so that different Logic functions are realized under the same circuit condition, and the FPGA based on the LUT has very high integration level, has different device densities from tens of thousands of gates to thousands of gates, can finish extremely complex digital Logic circuit functions, and is suitable for the field of high-speed and high-real-time high-density high-end digital Logic circuit design.

The data processing unit 13 is connected to the multiple input selecting unit 11 for performing a digital logic function on the received input signal. In this embodiment, the programmable logic unit 12 receives the at least one input signal when the multiple input selecting unit 11 selects the at least one input signal as the second output path, and invokes the logic control program to perform the digital logic operation. In the present embodiment, the data processing unit 13 may employ a microprocessor having logic operation, data storage, and control. Taking the most common central processing unit (Central Processing Unit, simply CPU) as an example, the CPU divides the complex logic into many small tasks, and each task can be completed by a certain instruction set(s), so that the complex work can be implemented by software. The method has the advantage that complex work can be completed as long as the CPU speed is high. Further, since logic is implemented using software, logic implementation can be changed by modifying the software.

The register unit 14 is connected to the programmable logic unit 12 and the data processing unit 13 through the two-way strobe unit 15, and is used for storing at least one of the operation result of the programmable logic unit 12 and the operation result of the data processing unit 13. In some embodiments, when the register unit 14 is connected to the programmable logic unit 12 through the two-way strobe unit 15, the operation result of the programmable logic unit 12 performing the digital logic function according to the programming information may be stored into the register unit 14. In some embodiments, when the register unit 14 is connected to the data processing unit 13 through the two-way strobe unit 15, the operation result of the data processing unit 13 calling the logic control program to perform the digital logic operation may be stored in the register unit 14. In practical applications, the register unit 14 may be, for example, a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

The two-way strobe unit 15 is located between the programmable logic unit 12, the data processing unit 13 and the register unit 14, and is used for outputting a selection signal to selectively signal the programmable logic unit 12 or the data processing unit 13 so that the programmable logic unit 12 or the data processing unit 13 which are in signal connection perform operations on the register unit 14. In this embodiment, the two-way gating unit 15 may include a plurality of two-way multiplexers, where each of the two-way multiplexers includes two input terminals, an output terminal, and a control terminal, where the two input terminals are respectively connected to the programmable logic unit 12 and the data processing unit 13, and the output terminal is connected to the register unit 14, and the control terminal is used to receive the control instruction.

The multiplexing output selecting unit 16 is connected to the registering unit 14, and is configured to generate a multiplexing output signal according to the stored information of the registering unit 14.

The digital logic circuit in this embodiment may further include a system clock management unit (not shown in the drawings) which may be connected to the data processing unit 13 and the register unit 14 for generating a system clock signal and transmitting the system clock signal to the data processing unit 13 and the register unit 14.

As the digital logic circuit in the embodiment shown in fig. 1 combines the programmable logic unit 12 and the data processing unit 13, the programmable logic unit 12 can be used to execute digital logic functions according to programming information and the data processing unit 13 can be used to call logic control programs to execute digital logic operations, so that the advantages of the planar logic control technology based on the programmable logic unit 12 and the time domain logic control technology based on the data processing unit 13 can be exerted, the flexibility of the circuit is improved, the cost is saved, the instantaneity is ensured, and the energy consumption is reduced.

In fact, the digital logic circuit shown in fig. 1 may be changed, and as shown in fig. 2, a schematic diagram of the structure of the data logic circuit in another embodiment of the present application is shown. As shown in fig. 2, the digital logic circuit in this embodiment may include: a multiplexing input selecting unit 11, a programmable logic unit 12, a data processing unit 13, a registering unit 14, a two-way gating unit 15, a control logic unit 17, and a multiplexing output selecting unit 16.

In the digital logic circuit shown in fig. 2, a control logic unit 17 is also included, as compared with the digital logic circuit in fig. 1. The control logic unit 17 is connected to the multiple input selecting unit 11 and the registering unit 14, and is configured to generate a control signal for controlling the two-way gating unit 15 according to at least one of an input signal of the multiple input selecting unit 11 and stored information of the registering unit 14. Specifically, the control logic unit 17 may be configured to selectively monitor the multiple input signals received by the multiple input selecting unit 11, or selectively monitor the stored information in the register unit 14, or monitor both the multiple input signals received by the multiple input selecting unit 11 and the stored information in the register unit 14.

In some embodiments, the control logic unit 17 determines the logic of the input signal received by the multiple input selection unit 11, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the data processing unit 13, so that the data processing unit 13 connected with the signal invokes a logic control program to execute a digital logic operation, and stores the operation result into the register unit 14; on the contrary, the control logic unit 17 determines the logic of the input signal received by the multiple input selection unit 11, and when the other specific state(s) is (are) satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the signal connected programmable logic unit 12 performs a digital logic function according to the programming information, and stores the operation result in the register unit 14.

In some embodiments, the control logic unit 17 determines the logic of the logic combination state after the logic combination state is changed and stored in the register unit 14, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the data processing unit 13 connected with the signals invokes a logic control program to perform digital logic operation, and stores the operation result into the register unit 14; the control logic unit 17 determines the logic of the logic combination state after the logic combination state is changed, which is stored in the register unit 14, and when the other specific state(s) is (are) satisfied, sends a control signal to the two-way gating unit, and makes the two-way gating unit 15 output a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the signal connected programmable logic unit 12 performs a digital logic function according to the programming information, and stores the operation result into the register unit 14.

In practice, as shown in fig. 2, the control logic unit 17 is connected to the multiple-output selecting unit 16 in addition to the multiple-input selecting unit 11 and the registering unit 14, for monitoring the output signal of the multiple-output selecting unit 16. For example, in some embodiments, the control logic unit 17 determines the logic of the output signal of the multiple output selection unit 16, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the data processing unit 13, so that the data processing unit 13 connected with the signal invokes a logic control program to perform a digital logic operation, and stores the operation result into the register unit 14; on the contrary, the control logic unit 17 determines the logic of the output signal of the multiple output selection unit 16, and when the other specific state(s) is (are) satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the signal connected programmable logic unit 12 performs a digital logic function according to the programming information, and stores the operation result in the register unit 14.

Furthermore, as shown in fig. 2, in some embodiments, the control logic unit 17 performs comprehensive logic judgment on the input signal received by the multiple input selection unit 11, the logic combination state after the logic combination state stored by the register unit 14 is changed, and the output signal of the multiple output selection unit 16, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the data processing unit 13 connected by the signal calls a logic control program to perform a digital logic operation, and stores the operation result into the register unit 14; on the contrary, the control logic unit 17 performs comprehensive logic judgment on the input signal received by the multiple input selection unit 11, the logic combination state after the logic combination state stored by the register unit 14 is changed, and the output signal of the multiple output selection unit 16, and when the other specific state(s) are satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the programmable logic unit 12, so that the programmable logic unit 12 in signal connection performs a digital logic function according to programming information, and stores an operation result into the register unit 14.

Further, the digital logic circuit shown in fig. 1 may be changed, and as shown in fig. 3, a schematic diagram of a data logic circuit in another embodiment of the present application is shown. As shown in fig. 3, the digital logic circuit in this embodiment may include: a multi-input selecting unit 11, a programmable logic unit 12, a data processing unit 13, a registering unit 14, a two-way gating unit 15, a control logic unit 17, a counting unit 18, and a multi-output selecting unit 16.

In comparison with the digital logic circuit in fig. 1, in the digital logic circuit shown in fig. 3, a control logic unit 17 and a counting unit 18 are also included.

The control logic unit 17 is selectively connected to the multiple-input selecting unit 11, the registering unit 14, the counting unit 18, and the multiple-output selecting unit 16, and is configured to generate a control signal for controlling the two-way gating unit 15 according to at least one of an input signal of the multiple-input selecting unit 11, stored information of the registering unit 14, a count result of the counting unit 18, and an output signal of the multiple-output selecting unit 16.

The counting unit 18 realizes a timing function by counting. In this embodiment, the counting unit 18 may include a plurality of counters.

In practice, the control logic unit 17 may be configured to selectively monitor one or more of the multiple input signals received by the multiple input selecting unit 11, the stored information in the register unit 14, the count result of the counting unit 18, and the multiple output signals generated by the multiple output selecting unit 16.

In some embodiments, the control logic unit 17 performs logic judgment on the counting result of the counting unit 18, and when a certain specific state(s) is (are) satisfied (for example, the first timing setting is satisfied), sends a control signal to the two-way gating unit 15, and makes the two-way gating unit 15 output a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the data processing unit 13 in signal connection invokes a logic control program to perform a digital logic operation, and stores the operation result into the register unit 14. The control logic unit 17 performs logic judgment on the count result of the counting unit 18, and when a certain other specific state(s) is (are) satisfied (for example, the second timing setting is satisfied), the control logic unit 17 sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the programmable logic unit 12, so that the programmable logic unit 12 in signal connection performs a digital logic function according to the programming information, and stores the operation result into the register unit 14. Thus, by using the counting unit 18, it is possible to realize a timing of selecting the data processing unit 13 to execute the digital logic operation, and the purpose that both the programmable logic unit 12 and the data processing unit 13 can operate the register unit 14 can be achieved.

In some embodiments, the control logic unit 17 determines the logic of the output signal of the multiple output selection unit 16, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the data processing unit 13, so that the data processing unit 13 connected with the signal invokes a logic control program to execute a digital logic operation, and stores the operation result into the register unit 14; on the contrary, the control logic unit 17 determines the logic of the output signal of the multiple output selection unit 16, and when the other specific state(s) is (are) satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the signal connected programmable logic unit 12 performs a digital logic function according to the programming information, and stores the operation result in the register unit 14.

Furthermore, as shown in fig. 3, in some embodiments, the control logic unit 17 performs comprehensive logic judgment on the input signal received by the multiple input selection unit 11, the logic combination state after the logic combination state stored by the register unit 14 is changed, the count result of the counting unit 18, and the output signal of the multiple output selection unit 16, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the data processing unit 13 connected with the signal invokes the logic control program to perform digital logic operation, and stores the operation result into the register unit 14; on the contrary, the control logic unit 17 performs comprehensive logic judgment on the input signal received by the multiple input selection unit 11, the logic combination state after the logic combination state stored by the register unit 14 is changed, the counting result of the counting unit 18, and the output signal of the multiple output selection unit 16, and when some other specific state(s) are met, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the programmable logic unit 12, so that the programmable logic unit 12 in signal connection performs a digital logic function according to programming information, and stores the operation result into the register unit 14.

The digital logic circuit in the embodiment shown in fig. 3 may further comprise a system clock management unit (not shown in the drawings) connected to the data processing unit 13, the register unit 14 and the control logic unit 17 for generating a system clock signal and transmitting the system clock signal to the data processing unit 13, the register unit 14 and the control logic unit 17.

As in the digital logic circuit in the embodiment shown in fig. 2 and 3, the programmable logic unit 12 and the data processing unit 13 are combined together, and meanwhile, the control logic unit 1 can selectively perform signal connection for the programmable logic unit or the data processing unit in a multi-channel monitoring manner, so that the programmable logic unit or the data processing unit which is in signal connection performs digital logic operation on the register unit, thereby achieving the purpose that the programmable logic unit 12 and the data processing unit 13 can operate the register unit 14, and exerting the advantages of the plane logic control technology based on the programmable logic unit 12 and the time domain logic control technology based on the data processing unit 13, improving the flexibility of the circuit, saving the cost, ensuring the real-time performance and reducing the energy consumption.

Referring to fig. 4, a digital logic circuit according to an embodiment of the present application may include: a multi-input selecting unit 11, a programmable logic unit 12, a data processing unit 13, a registering unit 14, a two-way gating unit 15, a control logic unit 17, a counting unit 18, and a multi-output selecting unit 16.

The programmable logic unit 12 is a programmable logic device (Programmable Logic Device, abbreviated as PLD) having a programmable function. In some embodiments, the programmable logic unit 12 may employ a complex programmable logic device (Complex Programmable Logic Device, abbreviated as CPLD). The CPLD chip mainly comprises programmable interconnection matrix units (MC, macro Cell) surrounding the center, wherein the MC structure is complex and has an I/O unit interconnection structure, and a specific circuit structure can be generated by a user according to the needs to complete certain logic functions. In some embodiments, the programmable logic units 12 may employ a Field programmable gate array (Field-Programmable Gate Array, abbreviated as FPGA). The FPGA chip comprises a large number of Logic units (LE for short), a user can realize different Logic circuit functions by freely combining the Logic units, when digital Logic is realized, corresponding results (such as corresponding relation between input and output and the like) are burnt into a storage unit in advance to form a Look-Up Table (LUT for short), so that different Logic functions are realized under the same circuit condition, and the FPGA based on the LUT has very high integration level, has different device densities from tens of thousands of gates to thousands of gates, can finish extremely complex digital Logic circuit functions, and is suitable for the field of high-speed and high-real-time high-density high-end digital Logic circuit design.

As shown in fig. 4, the data processing unit 13 may further include: the control and calculation module 131, the instruction storage module 133, and the data storage module 135, wherein the control and calculation module 131 is connected with the multi-path input selection unit 11 and the two-path gating unit 15, the instruction storage module 133 is connected with the control and calculation module 131, and the data storage module 135 is connected with the control and calculation module 131. In some embodiments, instruction storage module 133 is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash, and data storage module 135 is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

The register unit 14 is connected to the programmable logic unit 12 and the data processing unit 13 through the two-way strobe unit 15, and is used for storing at least one of the operation result of the programmable logic unit 12 and the operation result of the data processing unit 13. In some embodiments, when the register unit 14 is connected to the programmable logic unit 12 through the two-way strobe unit 15, the operation result of the programmable logic unit 12 performing the digital logic function according to the programming information may be stored into the register unit 14. In some embodiments, when the register unit 14 is connected to the data processing unit 13 through the two-way strobe unit 15, the operation result of the data processing unit 13 calling the logic control program to perform the digital logic operation may be stored in the register unit 14. In practical applications, the register unit 14 may be, for example, a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash. In some embodiments, the register unit 14 may be integrated with the control and computation module 131, the instruction storage module 133, and the data storage module 135 in the data processing unit 13 on the same chip, so as to improve the integration of the device, and in this embodiment, the register unit 14 is an internal register on the integrated chip.

The two-way strobe unit 15 is located between the programmable logic unit 12, the data processing unit 13 and the register unit 14, and is used for outputting a selection signal to selectively signal the programmable logic unit 12 or the data processing unit 13 so that the programmable logic unit 12 or the data processing unit 13 which are in signal connection perform operations on the register unit 14. In this embodiment, the two-way gating unit 15 may include a plurality of two-way multiplexers, where each of the two-way multiplexers includes two input terminals, an output terminal, and a control terminal, where the two input terminals are respectively connected to the programmable logic unit 12 and the control and calculation module 131 in the data processing unit 13, the output terminal is connected to the register unit 14, and the control terminal is connected to the control logic unit 17, and is used to receive the control instruction output by the control logic unit 17.

In some embodiments, the control logic unit 17 determines the logic of the input signal received by the multiple input selecting unit 11, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the data processing unit 13, so that the control and computing module 131 of the signal connection invokes a logic control program in the instruction storage module 133 and data in the data storage module 135 to perform a digital logic operation, and stores the operation result in the register unit 14; on the contrary, the control logic unit 17 determines the logic of the input signal received by the multiple input selection unit 11, and when the other specific state(s) is (are) satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the signal connected programmable logic unit 12 performs a digital logic function according to the programming information, and stores the operation result in the register unit 14.

In some embodiments, the control logic unit 17 determines the logic of the logic combination state after the logic combination state is changed and stored in the register unit 14, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the control and calculation module 131 of the signal connection invokes a logic control program in the instruction storage module 133 and data in the data storage module 135 to perform digital logic operation, and stores the operation result in the register unit 14; the control logic unit 17 determines the logic of the logic combination state after the logic combination state is changed, which is stored in the register unit 14, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the programmable logic unit 12 in signal connection performs a digital logic function according to programming information, and stores an operation result into the register unit 14.

In some embodiments, the control logic unit 17 performs logic judgment on the counting result of the counting unit 18, and when a certain specific state(s) is (are) satisfied (for example, a first timing setting is satisfied), sends a control signal to the two-way gating unit 15, and makes the two-way gating unit 15 output a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the control and calculation module 131 of the signal connection invokes a logic control program in the instruction storage module 133 and data in the data storage module 135 to perform digital logic operation, and stores the operation result in the register unit 14; the control logic unit 17 performs logic judgment on the count result of the counting unit 18, and when a certain (some) other specific state (for example, when the first timing setting is satisfied) is satisfied, the control logic unit 17 sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the programmable logic unit 12, so that the programmable logic unit 12 in signal connection performs a digital logic function according to the programming information, and stores the operation result into the register unit 14. Thus, by using the counting unit 18, it is possible to realize a timing of selecting the data processing unit 13 to execute the digital logic operation, and the purpose that both the programmable logic unit 12 and the data processing unit 13 can operate the register unit 14 can be achieved.

In some embodiments, the control logic unit 17 determines the logic of the output signal of the multiple output selection unit 16, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the data processing unit 13, so that the control and calculation module 131 of the signal connection invokes a logic control program in the instruction storage module 133 and data in the data storage module 135 to perform a digital logic operation, and stores the operation result in the register unit 14; on the contrary, the control logic unit 17 determines the logic of the output signal of the multiple output selection unit 16, and when the other specific state(s) is (are) satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively signal the programmable logic unit 12, so that the signal connected programmable logic unit 12 performs a digital logic function according to the programming information, and stores the operation result in the register unit 14.

Furthermore, in some embodiments, the control logic unit 17 performs comprehensive logic judgment on the input signal received by the multiple input selection unit 11, the logic combination state after the logic combination state stored by the register unit 14 is changed, the counting result of the counting unit 18, and the output signal of the multiple output selection unit 16, and when a certain (some) specific state is satisfied, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the data processing unit 13, so that the data processing unit 13 connected by the signal calls the logic control program to perform digital logic operation, and stores the operation result into the register unit 14; on the contrary, the control logic unit 17 performs comprehensive logic judgment on the input signal received by the multiple input selection unit 11, the logic combination state after the logic combination state stored by the register unit 14 is changed, the counting result of the counting unit 18, and the output signal of the multiple output selection unit 16, and when some other specific state(s) are met, sends a control signal to the two-way gating unit 15, so that the two-way gating unit 15 outputs a selection signal according to the control signal to selectively perform signal connection for the programmable logic unit 12, so that the programmable logic unit 12 in signal connection performs a digital logic function according to programming information, and stores the operation result into the register unit 14.

The application also discloses a microprocessor comprising digital logic as shown in the previous embodiments. The microprocessor provided with the digital logic circuit can realize the purpose that both the programmable logic unit and the data processing unit can execute logic operation on the logic state register unit, is a chip-level technology, greatly improves the integration level of a chip, has reasonable chip design and simple structure, reduces the chip surface body, reduces the development difficulty of the chip and the cost of the chip, and has wide market prospect.

The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims

1. A digital logic circuit, comprising:

the multi-output selection unit is used for generating multi-output signals according to the storage information of the register unit;

the data processing unit includes:

the control and calculation module is connected with the multi-path input selection unit and the two-path gating unit;

The instruction storage module is connected with the control and calculation module; and

and the data storage module is connected with the control and calculation module.

2. The digital logic circuit according to claim 1, wherein the programmable logic unit is a field programmable gate array FPGA or a complex programmable logic device CPLD.

3. The digital logic circuit of claim 1, wherein the two-way strobe unit comprises a plurality of two-way multiplexers, wherein each of the two-way multiplexers of the two-way strobe unit comprises two input terminals, an output terminal, and a control terminal, wherein the two input terminals are respectively connected with the programmable logic unit and the data processing unit, the output terminal is connected with the register unit, and the control terminal is connected with the control logic unit.

4. The digital logic circuit of claim 1, wherein the instruction memory module is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

5. The digital logic circuit of claim 1, wherein the data storage module is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

6. The digital logic circuit of claim 1, wherein the control and computation module, the instruction storage module, the data storage module, and the register unit are integrated on the same chip.

7. The digital logic circuit of claim 1, wherein the register unit is a static random access memory module SRAM, a dynamic random access memory module DRAM, or a Flash memory Flash.

8. The digital logic circuit of claim 1, further comprising a control logic unit coupled to the multiple input select unit and the register unit for generating a control signal for controlling the two-way strobe unit based on at least one of an input signal of the multiple input select unit and stored information of the register unit.

9. The digital logic circuit of claim 8, further comprising a counting unit coupled to the control logic unit, such that the control logic unit generates a control signal for controlling the two-way gating unit based on a count result of the counting unit.

10. The digital logic circuit of claim 9, wherein the counting unit comprises a plurality of counters.

11. The digital logic circuit of claim 8, wherein the control logic unit is coupled to the multiplexing unit for monitoring the output signal of the multiplexing unit.

12. The digital logic circuit of claim 8, further comprising a system clock management unit to generate and transmit a system clock signal to the data processing unit, the register unit, and the control logic unit.

13. A microprocessor, comprising: a digital logic circuit as claimed in any one of claims 1 to 12.