CN105740520A - FPGA (Field Programmable Gate Array) modeling method and device - Google Patents
FPGA (Field Programmable Gate Array) modeling method and device Download PDFInfo
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array) modeling method and device. When FPGA modeling is carried out, after a circuit model is subjected to abstract processing from a top layer to a bottom layer, a layout layer which contains the layout information of each functional module to which the current-time FPGA modeling relates, a functional layer which contains the internal sub functional module structure of each functional module and the attribute information of each functional module, and a component layer which contains components which realizes the internal sub functional module of each functional module and the attribution information of each component are independently created, and then, the created layout function, functional layer and the component layer can be called to obtain a corresponding FPGA model. Through the scheme of the invention, the FGPA modeling can be quickly and simply realized, a technical blank that FPGA does not have system modeling is filled up, the research and development period of the FPGA is greatly shortened, the research and development efficiency of the FPGA is improved, and research and development cost is lowered.
Description
Technical field
The present invention relates to integrated circuit fields, be specifically related to a kind of FPGA (Field-ProgrammableGateArray, i.e. field programmable gate array) modeling method and device.
Background technology
Growth requirement along with information and date science and technology, programmable chip, particularly field programmable gate array (FPGA) is by its flexible in programming, system stability, aboundresources, integrated level advantages of higher, its application has expanded to the field widely such as space flight, consumer electronics, Industry Control, test measurement from the original communications field, and also has the trend constantly expanded.The application of FPGA domestic at present depends primarily on the import of Xilinx, Altera Deng Ji great world FPGA giant company, and the domestic design for FPGA exists that design difficulty is big, R&D cycle length and the technology barriers such as design difficulty is big.Particularly in the hardware architecture modeling of restriction FPGA R&D cycle, domestic FPGA field can be described as blank out, main cause is that external giant company has grasped the advanced technology of this aspect but not external disclosure, simultaneously domestic related data document and corresponding research are less, make the technological accumulation of this aspect very little, causing that the FPGA R&D cycle is long, efficiency is low, the problem that cost is high.
Summary of the invention
The main technical problem to be solved in the present invention is to provide a kind of FPGA modeling method and device, solves existing to cause that the FPGA R&D cycle is long for FPGA without ripe modeling method, and efficiency is low, the problem that cost is high.
For solving above-mentioned technical problem, the present invention provides a kind of FPGA modeling method, including:
Creating layout layer, described layout layer comprises the layout information of each functional module that this FPGA modeling relates to；
Creating functional layer, described functional layer comprises the inside sub-function module structure of described each functional module and the attribute information of each functional module；
Creating component layer, described element layer comprises the attribute information of element and each element realizing the internal sub-function module of described each functional module；
Call described layout layer, functional layer and element layer and obtain FPGA model.
In an embodiment of the present invention, described layout information includes type information and each functional module positional information in described layout layer of described each functional module.
In an embodiment of the present invention, the attribute information of described functional module includes the annexation between module port annexation and the internal sub-function module of the module port of this functional module, module port direction, module port and other functional modules.
In an embodiment of the present invention, the attribute information of described element includes parameter corresponding to element port, element port direction, element port and the signal propagation path under the element port annexation of other elements, configuration information and configuration information, configuration information and call parameters.
In an embodiment of the present invention, described functional module include programmed logical module, programmable storing model, input/output module able to programme, programmable clock management module, programmable phase-locked loop module, programmable digital signal processing module in one or more.
In an embodiment of the present invention, what described element included in multi input functional generator, carry chain element, memory cell device, logic gate component, multi input selector element is one or more.
In an embodiment of the present invention, described layout information, the attribute information of functional module, element attribute information by preset modeling language describe.
In an embodiment of the present invention, described modeling language includes at least two in verilog language, systemverilog language, vhdl language, C language, java language.
In order to solve the problems referred to above, present invention also offers a kind of FPGA model building device, including:
Layout layer creation module, for creating the layout layer of the layout information comprising each functional module that this FPGA modeling relates to；
Functional layer creation module, for creating the functional layer of inside sub-function module structure and each functional module attribute information comprising described each functional module；
Element layer creation module, for creating the element layer comprising element and each component attributes information realizing the internal sub-function module of described each functional module；
Calling module, is used for calling described layout layer, functional layer and element layer and obtains FPGA model.
In an embodiment of the present invention, described layout information includes type information and each functional module positional information in described layout layer of described each functional module.
In an embodiment of the present invention, the attribute information of described functional module includes the annexation between module port annexation and the internal sub-function module of the module port of this functional module, module port direction, module port and other functional modules.
In an embodiment of the present invention, the attribute information of described element includes the signal propagation path under the element port annexation of element port, element port direction, element port and other elements, configuration information and configuration information, parameter.
The invention has the beneficial effects as follows:
FPGA modeling method provided by the invention and device, after circuit model being carried out abstract process from top to bottom when carrying out FPGA modeling, it is respectively created the functional layer comprising the attribute information of the layout layer of each functional module layout information, the inside sub-function module structure comprising each functional module and each functional module that this FPGA modeling relates to and the element layer of attribute information that establishment comprises element and each element realizing the internal sub-function module of each functional module, then calls the layout layer, functional layer and the element layer that create and can obtain the FPGA model of correspondence.Can quickly, simply be realized the modeling of FPGA by the program of the present invention, fill up the technological gap that FPGA is not had system modelling, substantially reduced the R&D cycle of FPGA, improved the efficiency of research and development of FPGA, reduce R&D costs.
Further, the attribute information of the layout information of layout layer, the attribute information of functional layer and element layer is adopted modeling language to be described by the present invention, for instance one or more that specifically can adopt in the more commonly used, general verilog language, systemverilog language, vhdl language, C language, java language are incorporated into line description.By this from describing the language being designed to describe all hardware model information language, the information such as signal propagation path that particularly configuration information is corresponding, parameter, for modeling, the key of signal is flowed through hardware model language to describe realization, overall architecture process can be made apparent, more reliable, and then modeling efficiency can be promoted further.For checking personnel, carrying out test checking based on such model is also be easy to Wrong localization place, and it is more accurate that such validation test flow process is easier to more simplification and test result.Meanwhile, this modeling language also supports that all of inside and outside annexation describes so that signal annexation is brighter and clearer, it is easier to carries out splicing and checking on total figure, is greatly improved the efficiency of Holistic modeling.
Accompanying drawing explanation
The FPGA modeling method schematic flow sheet that Fig. 1 provides for the embodiment of the present invention one；
The Rotating fields schematic diagram that Fig. 2 provides for the embodiment of the present invention one；
The FPGA model building device structural representation that Fig. 3 provides for the embodiment of the present invention two.
Detailed description of the invention
The modeling method that the present invention proposes, by carrying out carrying out abstract to circuit model to bottom from top layer, and can carry out the modeling language of all hardware model information description to each hardware model information (such as port at each level further combined with design definition, port direction, configuration information, parameter, internal annexation, outside port annexation, or even the signal propagation path information etc. under configuration information) state, enable the whole modeling process of FPGA to cover all levels to connect, placement-and-routing, the processes such as the signal propagation under configuration information, the modeling procedure made is more indirect, clear and smooth, make modeling process level higher, modeling efficiency is higher.The present invention is described in further detail in conjunction with accompanying drawing below by detailed description of the invention.
Embodiment one:
Shown in Figure 1, the FPGA modeling method that the present embodiment provides comprises the following steps:
Step 101: create layout layer, the layout layer of establishment comprises the layout information of each functional module that this FPGA modeling relates to；This layout layer is total figure ccf layer；
Step 102: creating functional layer, the functional layer of establishment comprises the inside sub-function module structure of each functional module in step 101 and the attribute information of each functional module；
Step 103: creating component layer, the element layer created comprises the attribute information of element and each element realizing the internal sub-function module of each functional module in step 102；
Step 104: call layout layer, functional layer and element layer and can obtain FPGA model.
Can be completed the foundation of FPGA model by above-mentioned establishment process from top to bottom, process is clear, simple and practicality is good.Therefore can promote the efficiency of setting up of FPGA largely, and then shorten the FPGA R&D cycle, reduce the R&D costs of FPGA.
In above-mentioned steps 101, each functional module layout refers to each functional module concrete layout on layout layer；Therefore the layout information in the present embodiment comprises each functional module positional information in layout layer；This positional information specifically adopts the two-dimensional coordinate representation that array tries, by each functional module correspondence layout to corresponding two-dimensional coordinate position so that the corresponding unique coordinate of each functional module.It addition, in the present embodiment, in order to be more conducive to describe and represent, the layout information in the present embodiment may also include the type information of each functional module, and also can farther include the module id information for uniquely identifying each functional module.Certainly also can farther include to generate the invoked parameter of top layer that model uses.
Functional module in the present embodiment is that each function to circuit carries out dividing the abstract functional module obtained according to certain rule, and a functional module is then likely to be obtained by the combination of one or more sub-function module.Concrete division rule can set flexibly according to concrete application scenarios.Such as, the present embodiment carries out the functional module that abstract division obtains and includes programmed logical module, programmable storing model, input/output module able to programme, programmable clock management module, programmable phase-locked loop module (comprising programmable delay phase-locked loop module and non-delayed phase-locked loop module able to programme), programmable digital signal processing module etc., modeling, what may relate in above-mentioned functions module is one or more every time, concrete selects those modules then to select according to current model circuit demand.
In above-mentioned steps 102, then the inside sub-function module structure for each functional module in step 101 is described, the attribute information of each functional module comprises the module port of this functional module, module port direction, annexation (i.e. the inside annexation of functional module) between module port annexation (i.e. the external connection relation of functional module) and the internal sub-function module of module port and other functional modules, still further comprise the parameter that various modeling needs, include but not limited to the parameter of function information, the parameter called by top layer, the parameter etc. that configuration information is corresponding.It should be appreciated that inside sub-function module herein can be a minimum functional unit, it is also possible to be the big functional unit obtained by the combination of multiple little functional units.Corresponding functional layer, namely the functional layer in the present embodiment can only include one layer, it is also possible to include multiple sublayer and the interbed progressive relationship of each sublayer, for instance the sub-function module in last sublayer is all made up of minimum functional unit.But it should be noted that all sub-function module that functional module comprises have the relation corresponding with this functional module, for instance all there is the unique identification information of this functional module so that subsequent calls.
Element in above-mentioned steps 103 is that correspondence realizes the components and parts of the sub-function module of each functional module in step 102, can be that an element correspondence realizes a sub-function module, can also be that the combination of multiple element realizes a sub-function module, but having one-to-one relationship between element and its sub-function module realized so that subsequent calls, this one-to-one relationship can certainly be passed through to arrange unique identifier and realize.Element in the present embodiment is the components and parts of the circuit bottom, and it can comprise multi input functional generator, carry chain element, memory cell device, logic gate component, multi input selector element etc..Modeling, what may relate in said elements is one or more every time.Corresponding, in the present embodiment, the attribute information of element includes parameter corresponding to element port, element port direction, element port and the signal propagation path under the element port annexation of other elements, configuration information and configuration information, configuration information and call parameters, and this call parameters is the parameter etc. called by functional module.
Personnel find after deliberation, for modeling, the key of signal flow through hardware model language to describe realization, it is possible to make overall architecture process apparent, more reliable, and then can promote modeling efficiency further.For checking personnel, carrying out test checking based on such model is also be easy to Wrong localization place, and it is more accurate that such validation test flow process is easier to more simplification and test result.Therefore, the present embodiment describes for the layout information of layout layer, the attribute information of the functional module of functional layer, modeling language that the attribute information etc. of element of element layer all can pass through to preset.Therefore modeling language template can first be defined before step 101 in the present embodiment, this modeling language template can utilize existing grammatical structure to express the various information that modeling needs, it is also possible to redefines grammatical structure completely and expresses the various information that modeling needs；Namely the modeling language that the present embodiment collects can be a kind of newspeak redefined, it is also possible to utilize one or more language existing, if its all hardware model information that can relate in descriptive modelling process.Therefore, in the present embodiment, before above-mentioned steps 101, in addition it is also necessary to first define FPGA modeling language.When defining this language, as set forth above, it is possible to redefine each grammer completely thus obtaining a kind of brand-new language that can describe all hardware model information.One or more realizations in existing language can also be utilized, for instance specifically can describe all hardware model information in conjunction with at least two in verilog language, systemverilog language, vhdl language, C language, java language etc..
To sum up, at layout layer, it is possible to by modeling language, each functional module positional information in layout layer, the module type of each functional module and relevant parameter thereof are described accurately.In follow-up test process, if it find that description above in violation of rules and regulations or mistake, can carry out checking easily and location of mistake at layout layer.Such as can pass through to check whether the type of functional module corresponding to each coordinate place mates and just can check integrally-built accuracy, modeling efficiency can be greatly promoted, save many loaded down with trivial details checking processes.
In functional layer, then can be described by the annexation (i.e. the inside annexation of functional module) between the modeling language module port annexation (i.e. the external connection relation of functional module) to module port, module port direction, module port and other functional modules and internal sub-function module and the parameter of each sub-function module.So can obtain completely and modular circuit structure clearly, can be easy to call when layout layer module modeling, and error rate is extremely low.Simultaneously, functional module defines the annexation of outside port and other functional module ports, so after the success of layout layout layer, can automatically and easily obtain all interconnection resources of each functional module of layout layer, checking of interconnection resource is carried out checking also dependent on the description of this functional module and positioned so that the accuracy rate of modeling procedure is guaranteed.
At element layer, by modeling language, the signal propagation path under the element port annexation of the element port of each element, element port direction, element port and other elements, configuration information and configuration information, parameter etc. can be described.This step is substantially carried out the modeling of element layer (namely fabric) and describes, owing to each signal of element layer and function are all very clear and definite, and the configuration information of circuit is also contained in this level, therefore this layer describes the information such as the annexation of port, port direction, port and other element port, particularly configuration information, have employed parameterized mode to carry out one_to_one corresponding with physical circuit so that model can mate with side circuit, allows the accuracy of modeling be guaranteed.Simultaneously, the propagation path information of signal under element layer also describes configuration information, the design of software kit after having modeled is more prone to, the information of the placement-and-routing of user is very clear, fit greatly the design of placement-and-routing's instrument of software kit and use, and or even designer is also easy to carry out corresponding user design Time-Series analysis and the power consumption analysis analysis etc. of critical path according to this information interpolation time sequence information or power consumption information.Description example as follows:
As can be seen from above, the port of component structure is provided according to modeling language, port direction, configuration information and annexation etc., give A==xx under configuration information simultaneously | | from IN port to the routing information of OUT terminal mouth when B==xx, based on such bottom modeling method, functionally can be readily available the internal signal trend of user's design, mobility and wire laying mode, so directly give signal routing information from bottom, user can be clear from signal flow on the one hand, on the other hand the design of software kit is easier to, so substantially reduce the R&D cycle.
In order to be better understood from the present invention, it is that the present invention will be further described for example below in conjunction with the Rotating fields shown in Fig. 2.
In Fig. 2, label 1 represents layout layer, and this layout layer is divided into multiple lattice point region, and in some lattice point regions, layout has the functional module 2 of functional layer.In Fig. 2, the position of functional module 2 and number illustrate, it should be appreciated that these are all that designer can adjust flexibly according to real needs.Labelling 3 in Fig. 2 is then used for realizing the element 3 of each sub-function module in functional module 2 for element layer.Figure it is seen that the scheme provided by the present embodiment can obtain the model that level is simple and hierarchical structure is clearly demarcated.
It should be appreciated that layout layer in the present embodiment, functional layer and element layer realize such as through monolayer, but also can adjust flexibly as required, thus obtaining four layers or higher level structure.Such as, as above analyze and functional layer can be subdivided into multilamellar；In like manner layout layer or element layer can also be finely divided as multilamellar.These conversion are all in protection scope of the present invention.
Embodiment two:
Shown in Figure 3, the present embodiment additionally provides a kind of FPGA model building device, comprising:
Layout layer creation module 31, for creating the layout layer of the layout information comprising each functional module that this FPGA modeling relates to；
Functional layer creation module 32, for creating the functional layer of inside sub-function module structure and each functional module attribute information comprising above-mentioned each functional module；
Element layer creation module 33, for creating the element layer comprising element and each component attributes information realizing the internal sub-function module of above-mentioned each functional module；
Calling module 34, is used for calling described layout layer, functional layer and element layer and obtains FPGA model.
Each functional module layout in the present embodiment refers to each functional module concrete layout on layout layer；Therefore the layout information in the present embodiment comprises each functional module positional information in layout layer；It addition, in the present embodiment, in order to be more conducive to describe and represent, the layout information in the present embodiment may also include the type information of each functional module, and also can farther include the module id information for uniquely identifying each functional module.Certainly the parameter of each functional module can also be farther included.
Functional module in the present embodiment is that each function to circuit carries out dividing the abstract functional module obtained according to certain rule, and a functional module is then likely to be obtained by the combination of one or more sub-function module.Concrete division rule can set flexibly according to concrete application scenarios.Such as, the present embodiment carries out the functional module that abstract division obtains and includes programmed logical module, programmable storing model, input/output module able to programme, programmable clock management module, programmable phase-locked loop module (comprising programmable delay phase-locked loop module and non-delayed phase-locked loop module able to programme), programmable digital signal processing module etc., modeling, what may relate in above-mentioned functions module is one or more every time, concrete selects those modules then to select according to current model circuit demand.
In the present embodiment, the attribute information of each functional module comprises the annexation (i.e. the inside annexation of functional module) between module port annexation (i.e. the external connection relation of functional module) and the internal sub-function module of the module port of this functional module, module port direction, module port and other functional modules, still further comprises the parameter of each sub-function module.
Element in the present embodiment is the components and parts that correspondence realizes the sub-function module of each functional module, it is possible to be that an element correspondence realizes a sub-function module, it is also possible to be that the combination of multiple element realizes a sub-function module.Element in the present embodiment is the components and parts of the circuit bottom, and it can comprise multi input functional generator, carry chain element, memory cell device, logic gate component, multi input selector element etc..Modeling, what may relate in said elements is one or more every time.Corresponding, in the present embodiment, the attribute information of element includes the signal propagation path under the element port annexation of element port, element port direction, element port and other elements, configuration information and configuration information, parameter etc..
For modeling, the key of signal is flowed through hardware model language to describe realization, it is possible to make overall architecture process apparent, more reliable, and then modeling efficiency can be promoted further.For checking personnel, carrying out test checking based on such model is also be easy to Wrong localization place, and it is more accurate that such validation test flow process is easier to more simplification and test result.Therefore, in the present embodiment, layout layer creation module 31 all can be described by modeling language for the attribute information etc. of the element of element layer for the attribute information of the functional module of functional layer, element layer creation module 33 for the layout information of layout layer, functional layer creation module 32.The modeling language that the present embodiment collects can be a kind of newspeak redefined, it is also possible to utilize one or more language existing, if its all hardware model information that can relate in descriptive modelling process.Therefore, in the present embodiment, it is necessary to first define FPGA modeling language.When defining this language, as set forth above, it is possible to redefine each grammer completely thus obtaining a kind of brand-new language that can describe all hardware model information.One or more realizations in existing language can also be utilized, for instance specifically can describe all hardware model information in conjunction with at least two in verilog language, systemverilog language, vhdl language, C language, java language.
Obviously, those skilled in the art should be understood that, each module or each step that the present invention is above-mentioned can realize with general calculation element, they can concentrate on single calculation element, or it is distributed on the network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, storage medium (ROM/RAM can be stored in, magnetic disc, CD) in performed by calculation element, and in some cases, shown or described step can be performed with the order being different from herein, or they are fabricated to respectively each integrated circuit modules, or the multiple modules in them or step are fabricated to single integrated circuit module realize.So, the present invention is not restricted to any specific hardware and software and combines.
By scheme provided by the invention, adopt from top layer to the abstract modeling method of bottom so that modeling process is apparent and accurate, take to describe different hardware informations at each layer according to its functional positioning correspondence simultaneously, make that at all levels Each performs its own functions, cooperate, in hgher efficiency.Based on self-defining hardware description language, it is possible to unified use this language to be modeled at all levels, and can all information of covering device, Holistic modeling is accomplished without any letup, flow process is smooth and easy, and the method belongs to pioneering in FPGA circle, so that the whole R&D cycle shortens.Employ the mode in the signal propagation path write information under configuration information at bottom simultaneously, the design making software kit is more simply easier to, the design making placement-and-routing's information, critical path information or even Time-Series analysis and power consumption analysis is simple and clear, substantially increase the efficiency of later stage related work, shorten the R&D cycle of global design flow process.
Above content is in conjunction with specific embodiment further description made for the present invention, it is impossible to assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, it is also possible to make some simple deduction or replace, protection scope of the present invention all should be considered as belonging to.
Claims (12)
1. a FPGA modeling method, it is characterised in that including:
Creating layout layer, described layout layer comprises the layout information of each functional module that this FPGA modeling relates to；
Creating functional layer, described functional layer comprises the inside sub-function module structure of described each functional module and the attribute information of each functional module；
Creating component layer, described element layer comprises the attribute information of element and each element realizing the internal sub-function module of described each functional module；
Call described layout layer, functional layer and element layer and obtain FPGA model.
2. FPGA modeling method as claimed in claim 1, it is characterised in that described layout information includes type information and each functional module positional information in described layout layer of described each functional module.
3. FPGA modeling method as claimed in claim 1, it is characterized in that, the attribute information of described functional module includes the annexation between module port annexation and the internal sub-function module of the module port of this functional module, module port direction, module port and other functional modules.
4. FPGA modeling method as claimed in claim 1, it is characterized in that, the attribute information of described element includes parameter corresponding to element port, element port direction, element port and the signal propagation path under the element port annexation of other elements, configuration information and configuration information, configuration information and call parameters.
5. the FPGA modeling method as described in any one of claim 1-4, it is characterized in that, described functional module include programmed logical module, programmable storing model, input/output module able to programme, programmable clock management module, programmable phase-locked loop module, programmable digital signal processing module in one or more.
6. the FPGA modeling method as described in any one of claim 1-4, it is characterised in that it is one or more that described element includes in multi input functional generator, carry chain element, memory cell device, logic gate component, multi input selector element.
7. the FPGA modeling method as described in any one of claim 1-4, it is characterised in that described layout information, the attribute information of functional module, element attribute information by preset modeling language describe.
8. FPGA modeling method as claimed in claim 7, it is characterised in that described modeling language includes at least two in verilog language, systemverilog language, vhdl language, C language, java language.
9. a FPGA model building device, it is characterised in that including:
Layout layer creation module, for creating the layout layer of the layout information comprising each functional module that this FPGA modeling relates to；
Functional layer creation module, for creating the functional layer of inside sub-function module structure and each functional module attribute information comprising described each functional module；
Element layer creation module, for creating the element layer comprising element and each component attributes information realizing the internal sub-function module of described each functional module；
Calling module, is used for calling described layout layer, functional layer and element layer and obtains FPGA model.
10. FPGA model building device as claimed in claim 9, it is characterised in that described layout information includes type information and each functional module positional information in described layout layer of described each functional module.
11. the FPGA model building device as described in claim 9 or 10, it is characterized in that, the attribute information of described functional module includes the annexation between module port annexation and the internal sub-function module of the module port of this functional module, module port direction, module port and other functional modules.
12. the FPGA model building device as described in claim 9 or 10, it is characterized in that, the attribute information of described element includes the signal propagation path under the element port annexation of element port, element port direction, element port and other elements, configuration information and configuration information, parameter.
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