CN103633138A - Semiconductor wafer of bottom isolation charge compensation structure and preparation method thereof - Google Patents
Semiconductor wafer of bottom isolation charge compensation structure and preparation method thereof Download PDFInfo
- Publication number
- CN103633138A CN103633138A CN201210298991.7A CN201210298991A CN103633138A CN 103633138 A CN103633138 A CN 103633138A CN 201210298991 A CN201210298991 A CN 201210298991A CN 103633138 A CN103633138 A CN 103633138A
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- CN
- China
- Prior art keywords
- type semiconductor
- semiconductor wafer
- conductive type
- substrate layer
- charge compensation
- Prior art date
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- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000002955 isolation Methods 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000011810 insulating material Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 239000002210 silicon-based material Substances 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 125000004437 phosphorous atom Chemical group 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a semiconductor wafer of a bottom isolation charge compensation structure. A thick insulating material is introduced to the bottom of a strip charge compensation semiconductor material in a semiconductor drift layer to improve the reverse bias voltage blocking capability of the semiconductor wafer. The invention further provides a preparation method of the semiconductor wafer of the charge compensation structure.
Description
Technical field
The present invention relates to a kind of bottom isolation charge compensation structural semiconductor wafer, the invention still further relates to a kind of preparation method of bottom isolation charge compensation structural semiconductor wafer.
Background technology
Energy realization height is withstand voltage and semiconductor chip structure low on-resistance is to present the P type semiconductor of column and the structure that N type semiconductor region is alternately arranged side by side, and the P type semiconductor of column and N type semiconductor are perpendicular to wafer surface.By the impurity concentration of P type semiconductor and N type semiconductor and width are set as to desired value, when applying reverse pressure drop, can realize high withstand voltage.This kind of structure is called charge compensation structure.
Charge compensation structural semiconductor wafer for the manufacture of semiconductor device under reverse biased, the peak value electric field of device appears at columnar semiconductor material bottom, affects to a certain extent the reverse blocking voltage of device.
Summary of the invention
The present invention is directed to the problems referred to above and propose, a kind of bottom isolation charge compensation structural semiconductor wafer and preparation method thereof is provided.
A bottom isolation charge compensation structural semiconductor wafer, is characterized in that: comprising: substrate layer is the first conductive type semiconductor material; Drift layer, is the first conductive type semiconductor material, is positioned on substrate layer, and strip the second conductive type semiconductor material that distributes in substrate layer vertical direction in drift layer has insulating material in strip the second conductive type semiconductor material bottom.
A preparation method for bottom isolation charge compensation structural semiconductor wafer, is characterized in that: on substrate layer surface, form the first conductive type semiconductor material epitaxy layer; In epitaxial loayer, form a plurality of grooves; Deposition insulating material in groove, then anti-carves erosion insulating material; By outer layer growth, form the second conductive type semiconductor material epitaxy layer, effects on surface carries out planarizing process.
A kind of bottom isolation charge compensation structural semiconductor wafer of the present invention, in drift semiconductor layer, heavy insulation material is introduced in strip charge compensation semi-conducting material bottom, improves semiconductor wafer reverse biased blocking ability.
Accompanying drawing explanation
Fig. 1 is the first generalized section of a kind of bottom isolation charge compensation structural semiconductor wafer of the present invention;
Fig. 2 is the second generalized section of a kind of bottom isolation charge compensation structural semiconductor wafer of the present invention.
Wherein, 1, substrate layer; 2, N type semiconductor silicon materials; 3, P type semiconductor silicon materials; 4, silicon dioxide.
Embodiment
Embodiment 1
Fig. 1 is the first generalized section of a kind of bottom isolation charge compensation structural semiconductor wafer of the present invention, below in conjunction with Fig. 1, describes semiconductor device of the present invention in detail.
A charge compensation structural semiconductor wafer, comprising: substrate layer 1 is N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E20cm
-3; N type semiconductor silicon materials 2, are positioned on substrate layer 1, are the semiconductor silicon material of N conduction type, and thickness is 40 μ m, and the doping content of phosphorus atoms is 1E16cm
-3; P type semiconductor silicon materials 3, are arranged in N type semiconductor silicon materials 2, are the semiconductor silicon material of P conduction type, and width is 2 μ m, and level interval is 2 μ m, are highly 38 μ m, and the doping content of boron atom is 1E16cm
-3; Silicon dioxide 2, is positioned at P type semiconductor silicon materials 3 bottoms, and thickness is 3 μ m.
Its manufacture craft comprises the steps:
The first step, at substrate layer 1 superficial growth phosphorus atoms doped epitaxial layer, forms N type semiconductor silicon materials 2, then carries out deposit silicon nitride layer, by lithography corrosion process, removes surperficial part silicon nitride layer;
Second step by anisotropic dry etch process, forms a plurality of grooves in N type semiconductor silicon materials 2;
The 3rd step, deposit silicon dioxide 2 in groove, then anti-etching silicon dioxide 2;
The 4th step, forms P type semiconductor silicon materials 3 by directed outer layer growth, and effects on surface carries out planarizing process, as shown in Figure 1.
Embodiment 2
Fig. 2 is the second generalized section of a kind of bottom isolation charge compensation structural semiconductor wafer of the present invention, below in conjunction with Fig. 2, describes semiconductor device of the present invention in detail.
A charge compensation structural semiconductor wafer, comprising: substrate layer 1 is N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E20cm
-3; N type semiconductor silicon materials 2, are positioned on substrate layer 1, are the semiconductor silicon material of N conduction type, and thickness is 40 μ m, and the doping content of phosphorus atoms is 1E16cm
-3; P type semiconductor silicon materials 3, are arranged in N type semiconductor silicon materials 2 and substrate layer 1, are the semiconductor silicon material of P conduction type, and width is 2 μ m, and level interval is 2 μ m, are highly 43 μ m, and the doping content of boron atom is 1E16cm
-3; Silicon dioxide 2, is positioned at P type semiconductor silicon materials 3 bottoms, and thickness is 3 μ m.
Its manufacture craft comprises the steps:
The first step, at substrate layer 1 superficial growth phosphorus atoms doped epitaxial layer, forms N type semiconductor silicon materials 2, then carries out deposit silicon nitride layer, by lithography corrosion process, removes surperficial part silicon nitride layer;
Second step by anisotropic dry etch process, forms a plurality of grooves in N type semiconductor silicon materials 2;
The 3rd step, deposit silicon dioxide 2 in groove, then anti-etching silicon dioxide 2;
The 4th step, forms P type semiconductor silicon materials 3 by directed outer layer growth, and effects on surface carries out planarizing process, as shown in Figure 2.
By above-mentioned example, set forth the present invention, also can adopt other example to realize the present invention, the present invention is not limited to above-mentioned instantiation, so the present invention is by claims circumscription simultaneously.
Claims (10)
1. bottom isolates a charge compensation structural semiconductor wafer, it is characterized in that: comprising:
Substrate layer is semi-conducting material;
Drift layer, is the first conductive type semiconductor material, is positioned on substrate layer, and strip the second conductive type semiconductor material that distributes in substrate layer vertical direction in drift layer has insulating material in strip the second conductive type semiconductor material bottom.
2. semiconductor wafer as claimed in claim 1, is characterized in that: described substrate layer impurity doping content is more than or equal to 1E17cm
-3.
3. semiconductor wafer as claimed in claim 1, is characterized in that: described drift layer the first conductive type semiconductor impurities of materials doping content is less than or equal to 1E17cm
-3.
4. semiconductor wafer as claimed in claim 1, is characterized in that: the second described conductive type semiconductor impurities of materials doping content is less than or equal to 1E17cm
-3.
5. semiconductor wafer as claimed in claim 1, is characterized in that: in described strip the second conductive type semiconductor material bottom and drift layer, between the first conductive type semiconductor material, have insulating material to isolate.
6. semiconductor wafer as claimed in claim 1, is characterized in that: described strip the second conductive type semiconductor material depth-width ratio is more than or equal to 5.
7. semiconductor wafer as claimed in claim 1, is characterized in that: described strip the second conductive type semiconductor material can be arranged in substrate layer.
8. semiconductor wafer as claimed in claim 1, is characterized in that: the thickness of described insulating material is more than or equal to 1 micron.
9. semiconductor wafer as claimed in claim 1, is characterized in that: described insulating material can be arranged in substrate layer.
10. the preparation method of a kind of bottom isolation charge compensation structural semiconductor wafer as claimed in claim 1, is characterized in that: comprise the steps:
1) on substrate layer surface, form the first conductive type semiconductor material epitaxy layer;
2) in epitaxial loayer, form a plurality of grooves;
3) deposition insulating material in groove, then anti-carves erosion insulating material;
4) in groove, form the second conductive type semiconductor material, effects on surface carries out planarizing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210298991.7A CN103633138A (en) | 2012-08-21 | 2012-08-21 | Semiconductor wafer of bottom isolation charge compensation structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210298991.7A CN103633138A (en) | 2012-08-21 | 2012-08-21 | Semiconductor wafer of bottom isolation charge compensation structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103633138A true CN103633138A (en) | 2014-03-12 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210298991.7A Pending CN103633138A (en) | 2012-08-21 | 2012-08-21 | Semiconductor wafer of bottom isolation charge compensation structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103633138A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060006458A1 (en) * | 2004-07-08 | 2006-01-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| CN1823424A (en) * | 2003-12-26 | 2006-08-23 | 罗姆股份有限公司 | Semiconductor device manufacturing method and semiconductor device |
| US20090159969A1 (en) * | 2006-04-11 | 2009-06-25 | Stmicroelectronics S.R.L. | Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device |
| US20100155831A1 (en) * | 2008-12-20 | 2010-06-24 | Power Integrations, Inc. | Deep trench insulated gate bipolar transistor |
| CN102347215A (en) * | 2010-07-26 | 2012-02-08 | 英飞凌科技奥地利有限公司 | Method for protecting a semiconductor device against degradation, a semiconductor device and a manufacturing method therefor |
-
2012
- 2012-08-21 CN CN201210298991.7A patent/CN103633138A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1823424A (en) * | 2003-12-26 | 2006-08-23 | 罗姆股份有限公司 | Semiconductor device manufacturing method and semiconductor device |
| US20060006458A1 (en) * | 2004-07-08 | 2006-01-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US20090159969A1 (en) * | 2006-04-11 | 2009-06-25 | Stmicroelectronics S.R.L. | Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device |
| US20100155831A1 (en) * | 2008-12-20 | 2010-06-24 | Power Integrations, Inc. | Deep trench insulated gate bipolar transistor |
| CN102347215A (en) * | 2010-07-26 | 2012-02-08 | 英飞凌科技奥地利有限公司 | Method for protecting a semiconductor device against degradation, a semiconductor device and a manufacturing method therefor |
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Application publication date: 20140312 |