CN103633122B - Semiconductor structure and manufacture method thereof - Google Patents
Semiconductor structure and manufacture method thereof Download PDFInfo
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- CN103633122B CN103633122B CN201210305283.1A CN201210305283A CN103633122B CN 103633122 B CN103633122 B CN 103633122B CN 201210305283 A CN201210305283 A CN 201210305283A CN 103633122 B CN103633122 B CN 103633122B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 description 21
- 230000005611 electricity Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 238000000137 annealing Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000000003 hoof Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of semiconductor structure and manufacture method thereof, this semiconductor structure includes substrate, device district, the first doped region and grid structure；First doped region is formed in the substrate in apparatus adjacent district；Grid structure is positioned on the first doped region；First doped region and grid structure overlap each other.
Description
Technical field
The invention relates to semiconductor structure and manufacture method thereof, in particular to the semiconductor junction with isolation area
Structure and manufacture method thereof.
Background technology
Between recent decades, semiconductor industry persistently reduces the size of semiconductor structure, and improve simultaneously speed, usefulness,
Density and the unit cost of integrated circuit.
Reduce device area and would generally seriously sacrifice the electrical property efficiency of semiconductor structure.In order to maintain the electricity of semiconductor structure
Property usefulness, especially in the case of semiconductor structure is high tension unit, it is necessary to use big device area, but, this can hinder
The development of semiconductor structure micro.
Summary of the invention
The invention relates to a kind of semiconductor structure and manufacture method thereof, this semiconductor structure has the usefulness of enhancement.
The invention provides a kind of semiconductor structure, this semiconductor structure includes substrate, device district, the first doped region and grid
Structure；First doped region is formed in the substrate in apparatus adjacent district；Grid structure is positioned on the first doped region；First doped region and grid
Structure overlaps each other.
The invention provides a kind of semiconductor structure, this semiconductor structure includes substrate, device district, the first doped region and grid
Structure；First doped region is formed in the substrate and apparatus adjacent district；Grid structure is positioned on the first doped region；First doped region and grid
Structure at least one of which has the shape of symmetry.
Present invention also offers the manufacture method of a kind of semiconductor structure, the method comprises the following steps: forms first and mixes
Miscellaneous district is in the substrate in apparatus adjacent district；Form grid structure on the first doped region；First doped region and grid structure are the heaviest
Fold.
Preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, it is described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the top view of the semiconductor structure according to an embodiment.
Fig. 2 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 3 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 4 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 5 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 6 A to Fig. 6 D illustrates the manufacture method of the semiconductor structure according to an embodiment.
Fig. 7 A to Fig. 7 C illustrates the manufacture method of the semiconductor structure according to an embodiment.
Fig. 8 A to Fig. 8 D illustrates the manufacture method of the semiconductor structure according to an embodiment.
Fig. 9 A to Fig. 9 C illustrates the manufacture method of the semiconductor structure according to an embodiment.
Figure 10 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 11 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 12 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 13 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 14 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 15 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 16 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 17 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 18 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 19 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 20 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 21 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 22 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 23 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 24 illustrates the profile of the semiconductor structure according to an embodiment.
[main element symbol description]
102,1302～substrate；104,304A, 304B, 604～first doped region；106,606～second doped region；108、
608～the 3rd doped region；110～the 4th doped region；112～first device district；114～the second device district；116～the 3rd device
District；118～isolation area；120,820～dielectric structure；122～lower doped region；124,524,1324,1424～upper doped region；
126～doping buried horizon；128～doped well region；130,230A, 230B, 430A, 430B, 430C, 430D, 430E～top doping
District；132,134,136～doping contact area；138,738A, 738B, 738C, 838～dielectric structure；140～grid；142～mix
Miscellaneous buried horizon；144,146,148,648～doped well region；150,152,154,156～doping contact area；158～dielectric layer；
160,162～conductive plunger；164、166、964、1064A、1064B、1164、1166A、1166B 1264A、1264B、1264C
～conductive layer；168～doped region；170～doping buried horizon；172～doped well region；174～doping contact area；176～dielectric
Structure；178～grid structure；180～first grid side；182～second gate side；184～first doping side；186～second
Doping side；188,190～doping contact area；92～doping buried horizon；94～doped well region；196～doped region；198～be situated between
Electricity structure；900A, 1000B, 1100B, 1200B～ground floor dielectric layer；D1, D2, K1, K2, M1, M2, W1, W2～spacing.
Detailed description of the invention
Fig. 1 illustrates the top view of the semiconductor structure according to an embodiment, its only illustrate semiconductor structure substrate 102,
First doped region the 104, second doped region the 106, the 3rd doped region the 108, the 4th doped region 110 and device district.In embodiment, shape
First doped region the 104, second doped region the 106, the 3rd doped region 108 in substrate 102 is become to have phase with the 4th doped region 110
The first same conductivity type, such as P conductivity type.
Refer to Fig. 1, device district includes the 112, second device district of first device district 114 and the 3rd device district 116.In enforcement
In example, the 112, second device district of first device district 114 and the 3rd device district 116 are to be respectively used for setting different types of device.
For example, first device district 112 is ultra-high pressure apparatus district, suitably fills in order to arrange such as supertension (UHV) MOS or other
Put.Second device district 114 can be used as high-pressure side (high side) district's (being greater than 650V), such as in order to arrange LVMOS,
BJT, electric capacity (capacitor), resistance or other suitable devices.3rd device district 116 can be used as low-voltage device district, in order to set
Put such as LVMOS or other suitable devices.
Refer to Fig. 1, for example, the first doped region 104 and the 3rd doped region 108 are positioned at outside first device district 112
Edge, in other words, first device district 112 may utilize the first doped region 104 and defines with the 3rd doped region 108.First doped region 104
With the outer rim that the 4th doped region 110 is positioned at the second device district 114, in other words, the second device district 114 may utilize the first doped region
104 define with the 4th doped region 110.Second doped region 106 is positioned in first device district 112.Second doped region 106 is segregated from
First doped region 104 and the 3rd doped region 108.4th doped region 110 is segregated from the first doped region 104 and the 3rd doped region
108.In embodiment, the first doped region 104 is used as isolation, such as in order to isolate first device district 112 and the second device district
114。
Refer to Fig. 1, in embodiment, the first doped region 104 substantially has the shape (profile) symmetrical in mirror, example
Such as the shape of a hoof (U shape).3rd doped region 108 substantially has the shape (profile) symmetrical in mirror.4th doped region 110
Substantially there is the shape (profile) symmetrical in mirror.The shape of above symmetry is with the central point through the second doped region 106
Virtual, such as along virtual of AB line as symmetrical centre in.The symmetrical cloth of the semiconductor structure according to embodiment
Office, can promote the uniformity (BVD uniformity) of breakdown voltage.
Fig. 2 illustrates the profile along the AB line of Fig. 1 of the semiconductor structure according to an embodiment.Semiconductor structure includes being positioned at
Isolation area 118 between first device district 112 and the second device district 114.In an embodiment, the first doped region 104 is formed in
In the substrate 102 of isolation area 118.First doped region 104 can be used as isolation and oneself's shielding (self-shielding).Dielectric is tied
Structure 120 is formed on the first doped region 104.
Refer to Fig. 2, substrate 102 includes lower doped region 122 and upper doped region 124.Upper doped region 124 is positioned at lower doped region
On 122.For example, lower doped region 122 can include doped well region that silicon-on-insulator (SOI), wafers doped formed or
Other suitable materials.Upper doped region 124 can be the thin film being epitaxially formed from lower doped region 122.In this embodiment, lower doping
District 122 and upper doped region 124 have identical the first conductivity type such as P conductivity type.
Refer to Fig. 2, first device district 112 include adulterate buried horizon 126, its may be formed at lower doped region 122 with on mix
In miscellaneous district 124.Doping buried horizon 126 can have the second conductivity type relative to the first conductivity type, such as N-conductivity.Dopant well
District 128 may be formed at lower doped region 122, upper doped region 124 and adulterates in buried horizon 126.Doped well region 128 can have second and lead
Electricity type such as N-conductivity.In embodiment, the degree of depth of doped well region 128 is to be enough to make device can bear operation with high pressure.Second mixes
Miscellaneous district 106 may be formed at doped well region 128 and adulterates in buried horizon 126.Second doped region 106 can have the first conductivity type such as
P conductivity type.Top doped region 130 may be formed in doped well region 128.Top doped region 130 can have the first conductivity type such as P conduction
Type.Top doped region 130 may be used to realize RESURF concept.Doping contact area 132,134 may be formed in the second doped region 106.
Doping contact area 136 may be formed in doped well region 128.Doping contact area 132,134,136 can be heavily doped.Doping contact
District 132 can have the first conductivity type such as P conductivity type.Doping contact area 134,136 can have the second conductivity type such as N conduction
Type.Doping contact area 134 can be used as source electrode, and doping contact area 136 can be used as drain electrode, and doping contact area 132 can be used as base stage.It is situated between
Electricity structure 138 may be formed on top doped region 130 and doped well region 128.Grid 140 may be formed at the second doped region 106 and is situated between
In electricity structure 138.In an embodiment, it is formed at the device in first device district 112 and can include MOS such as NMOS, or puncture
Voltage is more than supertension (UHV) NMOS of 650V.Doping buried horizon 126 can be at doping contact area 134 (such as source electrode) and substrate
Isolation effect is provided between the lower doped region 122 of 102.
Refer to Fig. 2, the second device district 114 include adulterate buried horizon 142, its may be formed at lower doped region 122 with on mix
In miscellaneous district 124.Doping buried horizon 142 can have the second conductivity type relative to the first conductivity type, such as N-conductivity.Dopant well
District 144 may be formed at lower doped region 122, upper doped region 124 and adulterates in buried horizon 142.Doped well region 144 can have second and lead
Electricity type such as N-conductivity.Doped well region 146 may be formed in doped well region 144.Doped well region 146 can have the second conductivity type
Such as N-conductivity.Doped well region 148 may be formed at doped well region 144 and adulterates in buried horizon 142.Doped well region 148 can have
First conductivity type such as P conductivity type.Doping contact area 150 may be formed in doped well region 146.Doping contact area 152,154 can
It is formed in doped well region 148.Doping contact area 150,152,154 can be heavily doped.Doping contact area 152 can have first
Conductivity type such as P conductivity type.Doping contact area 150,154 can have the second conductivity type such as N-conductivity.In embodiment, mix
The degree of depth of miscellaneous well region 144 is to be enough to make device can bear operation with high pressure.The doping buried horizon 142 in the second device district 114 can be kept away
The phenomenon (punch through) that punches through exempting from the lower doped region 122 (ground connection) from higher-pressure region to substrate 102 occurs.
Refer to Fig. 2, doping contact area 156 is formed in the 3rd doped region 108.Multilayer dielectric layer 158 can be formed at lining
At at the end 102.The conductive plunger 160,162 being formed in dielectric layer 158 can be electrically connected with conductive layer 164,166 such as M1, M2
To doping contact area 132,134,136,150,152,154,156.In embodiment, stride across isolation area 118 and be positioned at first and mix
Conductive layer 164,166 above miscellaneous district 104 is used as connecting (interconnection), and such as high pressure connects (HV
interconnection)。
Fig. 3 illustrates the profile along the CD line of Fig. 1 of the semiconductor structure according to an embodiment.Fig. 3 shows that grid 140 is positioned at
On the second doped region 106 in first device district 112.Doped region 168 may be formed at the second doped region 106 below grid 140
In.Doped region 168 can have the second conductivity type such as N-conductivity.Doped region 168 can be heavily doped.For example, doped region
168 can be the doping contact area 134 shown in Fig. 2.Doping buried horizon 170 may be formed at the lower doped region 122 outside isolation area 118
With in upper doped region 124.Doped well region 172 may be formed at lower doped region 122, upper doped region 124 and adulterates in buried horizon 170.
Doped well region 172 can have the second conductivity type such as N-conductivity.4th doped region 110 may be formed at doped well region 172 and doping
In buried horizon 170.4th doped region 110 can have the first conductivity type such as P conductivity type.Doping contact area 174 may be formed at the
In four doped regions 110.Doping contact area 174 can be heavily doped.Doping contact area 174 can have the second conductivity type such as N leads
Electricity type.
Refer to Fig. 3, in embodiment, dielectric structure 176 be formed in first doped region the 104, second doped region 106,
On 4th doped region 110.Grid structure 178 is formed on dielectric structure 176.Furthermore, the first doped region 104, dielectric structure 176
Overlap each other with grid structure 178.In embodiment, dielectric structure 176 can have the shape of a symmetry, or, grid structure
178 shapes can with a symmetry, the shape of above symmetry is with virtual of the central point through the second doped region 106, example
In along virtual of AB line (Fig. 1) as symmetrical centre.Grid structure 178 can be located on doping contact area 174.Refer to figure
3, in an embodiment, grid 140 has relative first grid side 180 and second gate side 182.First doped region 104 with
Minimum spacing D1 between the first grid side 180 of grid 140 is substantially equal to the first doped region 104 and the second of grid 140
Minimum spacing D2 between grid side 182.Or, between the minimum between the first grid side 180 of grid structure 178 and grid 140
Minimum spacing K2 between the second gate side 182 of grid structure 178 and grid 140 it is substantially equal to away from K1.In an embodiment,
Second doped region 106 has the first relative doping side 184 and the second doping side 186.First doped region 104 is mixed with second
Minimum spacing M1 between the first doping side 184 in miscellaneous district 106 is substantially equal to the first doped region 104 and the second doped region
Minimum spacing M2 between the second doping side 186 of 106.Or, grid structure 178 and the first doping of the second doped region 106
Minimum spacing W1 between side 184 be substantially equal to grid structure 178 and the second doped region 106 the second doping side 186 it
Between minimum spacing W2.The symmetrical layout of the semiconductor structure according to embodiment, can promote the uniformity of breakdown voltage
(BVD uniformity).Grid structure 178 is overlapping with the first doped region 104, and in other words, grid structure 178 is to cover (cover)
In the first doped region 104, coupling effect (coupling effect) so can be avoided.In an embodiment, for example,
Grid structure 178 ground connection.First doped region 104 may be used to provide supertension MOS isolation (isolation) and oneself shielding (self-
Shielding) effect.
Fig. 4 illustrates the profile along the EF line of Fig. 1 of the semiconductor structure according to an embodiment.Fig. 4 shows doping contact area
188 may be formed in the 4th doped region 110 and neighbouring doping contact area 190.Doping contact area 188 can with doping contact area 190
For heavily doped.Doping contact area 188 can have the first conductivity type such as P conductivity type.Doping contact area 190 can have second leads
Electricity type such as N-conductivity.Doping contact area 190 can be the doping contact area 174 in Fig. 3.Grid structure 178 can be located at the 4th doping
In district 110.Doping buried horizon 170 may be formed in lower doped region 122 and upper doped region 124.
Fig. 5 illustrates the profile along the GH line of Fig. 1 of the semiconductor structure according to an embodiment.Fig. 5 shows the first doped region
104 and the 3rd doped region 108 be adjacent to each other, in other words, the first doped region 104 and the 3rd doped region 108 be one share
Doped region.Doping contact area 156 may be formed in the 3rd doped region 108.Doping contact area 156 can be heavily doped.Doping
Contact area 156 can have the first conductivity type such as P conductivity type.Grid structure 178 is positioned on dielectric structure 176.
The layout of the semiconductor structure according to embodiment, can promote the uniformity (BVD of breakdown voltage
uniformity).In embodiment, the leakage current of high-pressure side to low-pressure side is less than 1 μ A.Furthermore, through HTRB and HTRB
Reliability test after, ultra-high pressure apparatus unit (UHV cell) be by checking.The layout of semiconductor structure can't increase
Add usable floor area.It is not required to extra technique.The concept of the semiconductor structure of embodiment can be applied to mixed design (mix-
Or Analog Circuit Design mode), or other suitably design, such as LED luminous (LED lighting) device, energy-saving bulb
(Energy saving lamp), stabilizer (ballast), motor body move device (motor driver) etc..
Fig. 6 A to Fig. 6 D illustrates according in an embodiment, the manufacture method of the semiconductor structure shown in Fig. 2.Refer to figure
6A, is doped step to the lower doped region 122 with the first conductivity type such as P conductivity type, has the second conductivity type to be formed
The doping buried horizon 126,142 of such as N-conductivity.Each doping step in embodiment is that the mask of available patterning enters
OK, or, after being doped step, annealing steps can be carried out at reasonable time point and come diffusion impurity, similar concept
It is no longer repeated below.
Refer to Fig. 6 B, on lower doped region 122, form upper doped region 124.Upper doped region 124 can in the way of extension shape
Become.Upper doped region 124 can have the first conductivity type such as P conductivity type.In an embodiment, an annealing steps can be carried out and make doping
Buried horizon 126,142 diffuses in doped region 124.To upper doped region 124, lower doped region 122 and doping buried horizon 126,142
It is doped step, to form the doped well region 128,144 with the second conductivity type such as N-conductivity.To doped well region 128 with
Doping buried horizon 126 is doped step, to form second doped region 106 with the first conductivity type such as P conductivity type.To upper
Doped region 124 and lower doped region 122 are doped step, to form first doping with the first conductivity type such as P conductivity type
District 104.Upper doped region 124 is doped step with lower doped region 122, to be formed, there is the first conductivity type such as P conductivity type
The 3rd doped region 108.Doped well region 144 is doped step with doping buried horizon 142, to be formed, there is the first conductivity type
The doped well region 148 of such as P conductivity type.Doped well region 144 is doped step with doping buried horizon 142, has to be formed
The doped well region 146 of the second conductivity type such as N-conductivity.
Refer to Fig. 6 C, doped well region 128 is doped step, to be formed, there is the first conductivity type such as P conductivity type
Top doped region 130.Refer to Fig. 6 D, on substrate 102, form dielectric structure 120,138.Dielectric structure 120,138 does not limit
In field oxide as shown in Figure 6 C, in other embodiments, dielectric structure 120,138 can include other knots that suitably insulate
Structure, such as shallow trench isolation (STI).Grid 140 is formed on substrate 102.Grid 140 can include gate dielectric layer and gate electrode
Layer, wherein gate electrode layer is positioned on gate dielectric layer.Gate electrode layer can include polysilicon, metal or other suitable materials.Grid are situated between
Electric layer can include oxide, nitride, silicon oxynitride or other suitable materials.To doped well region the 148, second doped region 106
Be doped with the 3rd doped region 108, with formed have the doping contact area 152 of the first conductivity type such as P conductivity type, 132,
156.Doped well region 128,146,148 is doped with the second doped region 106, with formation, there is the second conductivity type such as N and lead
The doping contact area 134,136,150,154 of electricity type.Then, follow-up element can be formed in the structure shown in Fig. 6 D to be such as situated between
Electric layer 158, conductive layer 164,166 and conductive plunger 160,162, to form semiconductor structure as shown in Figure 2.
Fig. 7 A to Fig. 7 C illustrates according in an embodiment, the manufacture method of the semiconductor structure shown in Fig. 3.Refer to figure
7A, is doped step to the lower doped region 122 with the first conductivity type such as P conductivity type, has the second conductivity type to be formed
The doping buried horizon 126,170 of such as N-conductivity.
Refer to Fig. 7 B, on lower doped region 122, form upper doped region 124.Upper doped region 124 can in the way of extension shape
Become.Upper doped region 124 can have the first conductivity type such as P conductivity type.In an embodiment, an annealing steps can be carried out and make doping
Buried horizon 126,170 diffuses in doped region 124.To upper doped region 124, lower doped region 122 and doping buried horizon 126,170
It is doped step, to form the doped well region 128,172 with the second conductivity type such as N-conductivity.To lower doped region 122 with
Upper doped region 124 is doped step, to form first doped region 104 with the first conductivity type such as P conductivity type.To doping
Well region 128 is doped step with doping buried horizon 126, to form second doping with the first conductivity type such as P conductivity type
District 106.Lower doped region 122 is doped step with upper doped region 124, to be formed, there is the first conductivity type such as P conductivity type
The 3rd doped region 108.Doped well region 172 is doped step with doping buried horizon 170, to be formed, there is the first conductivity type
4th doped region 110 of such as P conductivity type.
Refer to Fig. 7 C, the second doped region 106 is doped step, to be formed, there is the second conductivity type such as N conduction
The doped region 168 of type.3rd doped region 108 is doped step, to be formed, there is mixing of the first conductivity type such as P conductivity type
Miscellaneous contact area 156.4th doped region 110 is doped step, to form the doping with the second conductivity type such as N-conductivity
Contact area 174.Dielectric structure 176 is formed on the first doped region 104.Dielectric structure 176 is not limited to field as seen in figure 7 c
Oxide, in other embodiments, dielectric structure 176 can include other suitable insulation systems, such as shallow trench isolation
(STI)。
Then, refer to Fig. 3, on substrate 102 with dielectric structure 176, form grid 140 and grid structure 178.Grid 140
Can include gate dielectric layer and gate electrode layer, wherein gate electrode layer is positioned on gate dielectric layer.Gate electrode layer can include polysilicon, metal
Or other suitable materials.Gate dielectric layer 158 can include oxide, nitride, silicon oxynitride or other suitable materials.Grid are tied
Structure 178 can include gate dielectric layer and gate electrode layer, and wherein gate electrode layer is positioned on gate dielectric layer.Gate electrode layer can include polycrystalline
Silicon, metal or other suitable materials.Gate dielectric layer can include oxide, nitride, silicon oxynitride or other suitable materials.
Then, follow-up element such as dielectric layer 158, conductive layer 164,166 and conductive plunger 160,162 can be formed.
Fig. 8 A to Fig. 8 D illustrates according in an embodiment, the manufacture method of the semiconductor structure shown in Fig. 4.Refer to figure
8A, is doped step to the lower doped region 122 with the first conductivity type such as P conductivity type, has the second conductivity type to be formed
The doping buried horizon 170,192 of such as N-conductivity.
Refer to Fig. 8 B, on lower doped region 122, form upper doped region 124.Upper doped region 124 can in the way of extension shape
Become.Upper doped region 124 can have the first conductivity type such as P conductivity type.In an embodiment, an annealing steps can be carried out and make doping
Buried horizon 170,192 diffuses in doped region 124.To upper doped region 124, lower doped region 122 and doping buried horizon 170,192
It is doped step, to form the doped well region 194 with the second conductivity type such as N-conductivity.To upper doped region 124 with under mix
Miscellaneous district 122 is doped step, to form the 3rd doped region 108 with the first conductivity type such as P conductivity type.To doped well region
194 are doped step with doping buried horizon 170, to form the 4th doped region with the first conductivity type such as P conductivity type
110。
Refer to Fig. 8 C, doped well region 194 is doped step, to be formed, there is the first conductivity type such as P conductivity type
Doped region 196.Refer to Fig. 8 D, form dielectric structure 198 in doped well region 194 on the doped region 196 of top.Dielectric structure
198 are not limited to field oxide as in fig. 8d, and in other embodiments, dielectric structure 198 can include that other are the most exhausted
Edge structure, such as shallow trench isolation (STI).Grid structure 178 is formed on substrate 102 with dielectric structure 198.Grid structure 178 can
Including gate dielectric layer and gate electrode layer, wherein gate electrode layer is positioned on gate dielectric layer.3rd doped region 108 is doped step
Suddenly, to form the doping contact area 156 with the first conductivity type such as P conductivity type.4th doped region 110 is doped step
Suddenly, to form the doping contact area 188 with the first conductivity type such as P conductivity type.4th doped region 110 is doped step
Suddenly, to form the doping contact area 190 with the second conductivity type such as N-conductivity.Then, follow-up element can be formed such as to be situated between
Electric layer 158, conductive layer 164,166 and conductive plunger 160,162, to form semiconductor structure as shown in Figure 4.
Fig. 9 A to Fig. 9 C illustrates according in an embodiment, the manufacture method of the semiconductor structure shown in Fig. 5.Refer to figure
9A, is doped step to the lower doped region 122 with the first conductivity type such as P conductivity type, has the second conductivity type to be formed
The doping buried horizon 142 of such as N-conductivity.
Refer to Fig. 9 B, on lower doped region 122, form upper doped region 124.Upper doped region 124 can in the way of extension shape
Become.Upper doped region 124 can have the first conductivity type such as P conductivity type.In an embodiment, an annealing steps can be carried out and make doping
Buried horizon 142 diffuses in doped region 124.Upper doped region 124, lower doped region 122 are doped with doping buried horizon 142
Step, to form the doped well region 144 with the second conductivity type such as N-conductivity.To upper doped region 124 and lower doped region 122
It is doped step, to form the 3rd doped region 108 and first doped region 104 with the first conductivity type such as P conductivity type.
Refer to Fig. 9 C, on substrate 102, form dielectric structure 176.Dielectric structure 176 is not limited to as shown in Figure 9 C
Field oxide, in other embodiments, dielectric structure 176 can include other suitable insulation systems, such as shallow trench isolation
(STI).Grid structure 178 is formed on dielectric structure 176.Grid structure 178 can include gate dielectric layer and gate electrode layer, wherein grid electricity
Pole layer is positioned on gate dielectric layer.3rd doped region 108 is doped, to be formed, there is the first conductivity type such as P conductivity type
Doping contact area 156.Then, can be formed in the structure shown in Fig. 9 C follow-up element such as dielectric layer 158, conductive layer 164,
166 with conductive plunger 160,162, to form semiconductor structure as shown in Figure 5.
Figure 10 to Figure 24 illustrates the profile of the semiconductor structure according to different embodiments, and it also can be applied has symmetrical cloth
The concept of office.
Semiconductor structure shown in Figure 10 is with the semiconductor structure difference shown in Fig. 2, is the top doping using multilamellar
District 230A, 230B.For example, all there is upper top doped region 230A and the lower top doped region of the first conductivity type such as P conductivity type
230B is separated from each other by doped well region 128.
Semiconductor structure shown in Figure 11 is with the semiconductor structure difference shown in Fig. 2, is that the top eliminated in Fig. 2 is mixed
Miscellaneous district 130.
Semiconductor structure shown in Figure 12 is with the semiconductor structure difference shown in Fig. 2, is to use plurality of rows of first to mix
Miscellaneous district 304A, 304B.First doped region 304A, 304B can be separated from each other with upper doped region 124 by lower doped region 122.Implement
Example is not limited to use as shown in figure 12 first doped region 304A, 304B of two rows.In other embodiments, can use more than two
The first doped region (not shown) of row.
Semiconductor structure shown in Figure 13 is with the semiconductor structure difference shown in Fig. 2, is to use the doping of plurality of rows of top
District 430A, 430B, 430C, 430D, 430E.Doped region 430A, 430B, 430C, 430D, 430E can pass through doped well region 128 on top
Separated from each other.
Semiconductor structure shown in Figure 14 is have the first conduction in use with the semiconductor structure difference shown in Fig. 2
In the example of the upper doped region 524 of type such as P conductivity type, it is to omit in Fig. 2 there is the first of the first conductivity type such as P conductivity type
Doped region (104).
Semiconductor structure shown in Figure 15 is with the semiconductor structure difference shown in Fig. 2, is to omit in Fig. 2 to have second
The doping buried horizon 126,142 of conductivity type such as N-conductivity.Additionally, first doped region the 604, second doped region in Figure 15
606, the degree of depth of the 3rd doped region 608 and doped well region 648 be shallower than in Fig. 2 first doped region the 104, second doped region 106,
3rd doped region 108 and the degree of depth of doped well region 148.For example, the second doped region 606 in Figure 15 is substantially shallower than doping
Well region 128.Doped well region 648 in Figure 15 is substantially shallower than doped well region 144.Compared to the semiconductor structure shown in Fig. 2, figure
The technique of the semiconductor structure shown in 15 is compared with simple and cost is relatively low.
Semiconductor structure shown in Figure 16 is with the semiconductor structure difference shown in Fig. 2, and top doped region 130 is to arrange
There are several dielectric structure 738A, 738B, 738C separated from each other.This embodiment can reduce the opening resistor (Rds-on) of device.
Semiconductor structure shown in Figure 17 is with the semiconductor structure difference shown in Fig. 2, is to eliminate dielectric layer 158 relatively
The part of top, conductive layer 166 (such as M2) and conductive plunger 162.Compared to the semiconductor structure shown in Fig. 2, shown in Figure 17
The technique of semiconductor structure compared with simple and cost is relatively low.
Semiconductor structure shown in Figure 18 is with the semiconductor structure difference shown in Fig. 2, and dielectric structure 820,838 is to make
With shallow trench isolation (STI).
Semiconductor structure shown in Figure 19 is with the semiconductor structure difference shown in Fig. 2, is to eliminate the grid in Fig. 2
140, and use the conductive layer 964 being formed on ground floor dielectric layer 900A to perform polysilicon gate in grid 140 as shown in Figure 2
Effect of electrode layer.Conductive layer 964 can include metal.
Semiconductor structure shown in Figure 20 is with the semiconductor structure difference shown in Fig. 2, the first doping in isolation area 118
Second layer dielectric layer 1000B above district 104 is by conductive layer 1064A, 1064B (M1) separately.In embodiment, neighbouring isolation
Conductive layer 1064A, 1064B substantial portion ground in district 118 is overlapping with the first doped region 104.
Semiconductor structure shown in Figure 21 is with the semiconductor structure difference shown in Fig. 2, the first doping in isolation area 118
Conductive layer 1166A, 1166B (M2) on second layer dielectric layer 1100B above district 104 are separated from each other.In embodiment, lead
Electric layer 1164 (M1) is overlapping with the first doped region 104.
Semiconductor structure shown in Figure 22 is with the semiconductor structure difference shown in Fig. 2, the first doping in isolation area 118
Second layer dielectric layer 1200B above district 104 is by conductive layer 1264A, 1264B, 1264C (M1) separately.In embodiment, adjacent
Conductive layer 1264A, 1264C substantial portion ground of nearly isolation area 118 is overlapping with the first doped region 104.Conductive layer 1264B essence
Upper overlapping with the first doped region 104.
Semiconductor structure shown in Figure 23 is with the semiconductor structure difference shown in Fig. 2, is formed at and has the first conduction
Upper doped region 1324 on the lower doped region 122 of type such as P conductivity type has contrary the second conductivity type such as N-conductivity.In
In this embodiment, the voltage of (boost) substrate 1302 can be promoted.
Semiconductor structure shown in Figure 24 is with the semiconductor structure difference shown in Fig. 2, is formed at and has the first conduction
Upper doped region 1424 on the lower doped region 122 of type such as P conductivity type has contrary the second conductivity type such as N-conductivity.Again
Person, is the doped well region 128,144 eliminating and having the second conductivity type such as N-conductivity in Fig. 2.
Embodiment is disclosed above, and so it is not limited to the present invention, and any those who are familiar with this art, without departing from this
In bright spirit and scope, when doing a little change and retouching, therefore protection scope of the present invention is when regarding appended claims
What scope was defined is as the criterion.
Claims (8)
1. a semiconductor structure, including:
One substrate；
One first device district；
One second device district；
One first doped region, is formed in this substrate in this first device district neighbouring, and this first doped region be between this first
Between device district and this second device district；
One second doped region, is positioned in this first device district；
One grid, is positioned in this first device district；
One first grid structure, is positioned on this first doped region, and wherein this first doped region is to overlap each other with this first grid structure
's；And
One second gate structure, is positioned on this second doped region, and wherein this second gate structure is overlapping with this second doped region；
Wherein, this first grid structure is positioned at this second gate structure.
2. a semiconductor structure, including:
One substrate；
One first device district；
One second device district；
One first doped region, is formed in this substrate and this first device district neighbouring, and this first doped region be between this first
Between device district and this second device district；
One second doped region, is positioned in this first device district；
One grid, is positioned in this first device district；
One first grid structure, is positioned on this first doped region, wherein this first doped region and this first grid structure at least a part of which it
One shape with symmetry；And
One second gate structure, is positioned on this second doped region, and wherein this second gate structure is overlapping with this second doped region；
Wherein, this first grid structure is positioned at this second gate structure.
Semiconductor structure the most according to claim 1 and 2, wherein this first doped region is to isolate this first device district
With this second device district.
Semiconductor structure the most according to claim 3, wherein this first doped region has the shape of a symmetry and is positioned at this
The outer rim in first device district.
Semiconductor structure the most according to claim 1 and 2, wherein this grid has a relative first grid side and one
Two grid sides, the minimum spacing between this first doped region and this first grid side is equal to this first doped region and this second gate
A minimum spacing between side, or, the minimum spacing between this grid structure and this first grid side is equal to this grid structure
And the minimum spacing between this second gate side.
Semiconductor structure the most according to claim 1 and 2, this first doped region be between this first device district with this second
Device district, this second doped region is positioned in this substrate in this first device district, this first doped region separated from each other with this
Two doped regions have identical conductivity type.
Semiconductor structure the most according to claim 6, wherein this second doped region has one first relative doping side
With one second doping side, the minimum spacing between this first doped region and this first doping side is equal to this first doped region
And the minimum spacing between this second doping side.
Semiconductor structure the most according to claim 6, wherein this second doped region has one first relative doping side
With one second doping side, or, this grid structure and this first doping side between a minimum spacing equal to this grid structure with
A minimum spacing between this second doping side.
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| TW201227961A (en) * | 2010-12-17 | 2012-07-01 | Macronix Int Co Ltd | A high voltage semiconductor device |
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| TW201214667A (en) * | 2010-09-16 | 2012-04-01 | Macronix Int Co Ltd | Low-voltage structure for high-voltage Electrostatic Discharge protection |
| TW201227961A (en) * | 2010-12-17 | 2012-07-01 | Macronix Int Co Ltd | A high voltage semiconductor device |
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