TWI396180B - A cellular transistor and an integrated circuit - Google Patents

Description

Unit transistor and integrated circuit

The present invention relates to a power transistor, and more particularly to a unit transistor, a unit cell crystal body circuit, and a display system.

In the past few decades, power metal oxide semiconductor field effect transistor (MOSFET) technology has become a hot technology in high voltage (HV) applications requiring power devices.

In conventional HV applications, the power MOSFET as a switch is usually placed outside the integrated circuit of the controller (eg, the inverter controller) due to some obstacles in the integration technique of the power MOSFET and its controller circuit. The controller controls the power MOSFET on/off (ON/OFF). For example, integrating a power MOSFET and controller on the same wafer requires a larger die size, which increases cost.

In order to solve the above technical problems, the present invention provides a unit transistor. The unit transistor includes an N-type highly doped (N+) buried layer (NBL), an N-well connected to the NBL, a first N+ layer connected to the N-well, and a multi-connected N-hole and the first N+ layer connected to the NBL. Bungee jumping. The N well is formed after the formation of the NBL. The first N+ layer is formed after the formation of the N well.

The present invention also provides an integrated circuit. The integrated circuit includes a switch including a unit transistor and a controller circuit connected to the switch and controlling the switch. The unit transistor includes an N-type highly doped (N+) buried layer (NBL), The N well connected to the NBL, the first N+ layer connected to the N well, and the plurality of drains connected to the NBL through the N well and the first N+ layer. The N well is formed after the formation of the NBL. The first N+ layer is formed after the formation of the N well.

The invention also provides a display system. The display system includes a plurality of light sources and a inverter circuit coupled to the light source. The inverter circuit converts the DC voltage into an AC voltage to power the light source. The inverter circuit includes a switch including a unit transistor and a controller circuit connected to the switch and controlling the switch. The unit transistor includes an N-type highly doped (N+) buried layer (NBL), an N-well connected to the NBL, a first N+ layer connected to the N-well, and a multi-connected N-hole and the first N+ layer connected to the NBL. Bungee jumping. The N well is formed after the formation of the NBL. The first N+ layer is formed after the formation of the N well.

The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments to make the features and advantages of the present invention more obvious.

A detailed description of the embodiments of the present invention will be given below. While the invention will be described in conjunction with the embodiments, it should be understood that the invention is not limited to the embodiments. Rather, the invention is intended to cover various alternatives, modifications, and equivalents as defined by the scope of the invention. The detailed description below provides a number of specific details for the purpose of providing a complete understanding of the invention. However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without the details or the equivalents. In other instances, well-known methods, procedures, components, and circuits are not described in detail to highlight the features of the invention.

Some portions of the following detailed implementation modes are presented in terms of procedures, logic blocks, processing processes, and other symbolic representations of the operation of the fabricated semiconductor device. These descriptions and representations are a method of familiarizing those skilled in the art of semiconductor device fabrication with the most effective way of communicating the substance of their work to others in the field. In the present application, a program, a logical block, a processing process, or the like, is conceived as a sequence of steps or instructions consistent with each other to achieve a desired result. These steps are steps that require physical manipulation of physical quantities. However, it should be understood that these terms and their similar expressions are to be associated with the appropriate physical quantities and are merely convenient labels for the application. Unless specifically stated in the discussion that follows, throughout the application, the use of "form", "perform", "produce", "deposit", "etch" (etch) "," "fabricate", "connected", "implanted", "integrate" or the like, refers to the operation and process of semiconductor device fabrication.

It is understood that the drawings are not to scale, and only a

In addition, other processes and steps may be combined with the processes and steps discussed herein, that is, there may be multiple processes and steps before, during, and/or after the steps shown and described herein. Importantly, embodiments of the present invention can be implemented in conjunction with other processes and steps without significant impact. In general, the various embodiments of the present invention may replace portions of the conventional process without significantly affecting its peripheral processes and steps.

1 is a block diagram of an integrated circuit (IC) 100 in accordance with one embodiment of the present invention. Applications for IC 100 may include, but are not limited to, need High voltage (HV) electronic circuits of one or more power semiconductor devices (eg, operating voltages above 5V), such as cold cathode fluorescent lamp inverters, light emitting diode lighting devices, battery chargers, DC/DC (DC) /DC) converter, backlight inverter, battery charger controller, etc. The IC 100 can include a switch (eg, a current switch or voltage switch) 120 and a controller circuit 110 that controls the switch 120. Advantageously, in one embodiment, switch 120 and controller circuit 110 are integrated on a single wafer. Switch 120 can be a power metal oxide semiconductor field effect transistor (MOSFET).

In an embodiment, the IC 100 including the controller circuit 110 and the switch 120 can be fabricated using metal oxide semiconductor (MOS) technology. In an embodiment, controller circuit 110 includes one or more MOS transistors. In an embodiment, the MOS transistor in the controller circuit 110 can be fabricated, but not limited to, a laterally diffused metal oxide semiconductor (LDMOS) transistor. Switch 120 can be fabricated, but is not limited to, a double diffused drain metal oxide semiconductor (DDDMOS) transistor.

In an embodiment, controller circuit 110 includes one or more LDMOS transistors. Advantageously, in one embodiment, controller circuit 110 employs an LDMOS transistor. Controller circuit 110 has enhanced reliability as compared to other types of transistors, such as DDDMOS transistors. Since the LDMOS transistor can operate at a high operating voltage (for example, 30-40 V), the controller circuit 110 employing the LDMOS transistor has enhanced reliability. For example, controller circuit 110 employing LDMOS transistors has sufficient tolerance to withstand undesired electrical/voltage stress conditions, such as hot carrier placement (HCI) testing.

Switch 120 employs a unit DDDMOS transistor. And adopting other classes The size of the switch 120 is smaller and the reaction speed is faster than that of a type of transistor such as an LDMOS transistor. In an embodiment, the drain of switch 120 (eg, a power MOSFET) can be selectively coupled to a maximum operating voltage or a lower voltage. More specifically, when the switch (cell DDDMOS transistor) 120 is turned on, the drain voltage can be lowered to a lower voltage, such as 0.5 volts, and when the switch (cell DDDMOS transistor) 120 is turned off, the drain voltage can be restored. Maximum operating voltage (can vary depending on the application). Moreover, in an embodiment, the conduction time (e.g., conduction time) of the switch 120 is relatively short under the control of the controller circuit 110. Therefore, the HCI effect will not be induced in such an operation, and the switch (cell DDDMOS transistor) 120 can be used in a high voltage state.

Accordingly, IC 100 includes switch 120 and controller circuit 110, switch 120 is a unit DDDMOS transistor, and controller circuit 110 controls switch 120 and includes one or more LDMOS transistors. Advantageously, the IC 100 has enhanced reliability and a smaller wafer size. In one embodiment, according to the process shown in FIG. 2, the LDMOS transistor and the cell DDDMOS transistor can be integrated on the same wafer. Using the process shown in Figure 2, the penetration capability of the unit DDDMOS transistor can be enhanced by adding N-type grade (NGRD) cloth plants to the process. Therefore, the reliability of the IC 100 including LDMOS and DDDMOS transistors can be further enhanced in high voltage applications.

2 is a flow diagram 200 of a process for integrating a switch and controller circuit on a single wafer in accordance with one embodiment of the present invention. Flowchart 200 is described in conjunction with Table 1.

Table 1

In step 1, a wafer is fabricated. Subsequently, different photoresists are deposited on the semiconductor substrate and then selectively patterned through exposure and development processes. In step 2, the first photoresist is deposited as an N-type heavily doped buried layer (NBL) mask. In step 3-4, implanted N-type highly doped (N+) impurity ions are implanted into the selected wafer region of the patterned NBL mask reticle and implanted at a suitable depth. In step 5, a P-type epitaxial (P-epi) layer is formed by P-type epitaxial (P-epi) deposition. Therefore, in step 201, NBL is formed according to steps 1-5. In some high pressure applications, the formation of NBL is optional.

The first photoresist is then removed from the surface of the wafer. In step 6, the second photoresist is deposited as an N-well mask. In step 7-8, the N well shimming is performed using the patterned N well reticle described above, and the appropriate depth is implanted. Similarly, the implantation of the P well is performed at step 9. Therefore, at step In step 203, an N-well is formed in steps 6-8, and a P-well is formed in step 9.

Then, the second photoresist is removed. In step 10, a third photoresist is deposited as an optical density (OD) mask to define active areas. Then, the third photoresist is selectively etched through tantalum nitride (SiN), for example, a tantalum nitride etch is performed in step 11. After removing the third photoresist, in step 12, the fourth photoresist is deposited as a P-field mask. After the P-field is implanted in step 13, field oxidation is performed in step 14. Thus, in step 205, a field oxide layer/region is formed in accordance with steps 10-14.

Then, gate oxidation is performed in step 15. After removing the fourth photoresist, in step 16, the fifth photoresist is deposited as a HV gate oxide mask. Wet etching is performed in step 17. Then, a second gate oxidation is performed in step 18. Therefore, in step 207, a gate oxide layer is formed in accordance with steps 15-18.

Then, the fifth photoresist is removed. In step 19, Vt is implanted for adjusting the threshold voltage value of the MOS transistor. In step 20, the polysilicon is doped. N+ polymorphic doping is performed in step 21. The sixth photoresist is deposited as a polycrystalline reticle in step 22, after which polysilicon etch is performed in step 23. Therefore, in step 209, polysilicon is formed according to steps 19-23.

After removing the sixth photoresist, in step 24, the seventh photoresist is deposited as an N-type slope (NGRD) mask. After the NGRD reticle is deposited, the NGRD is implanted in step 25. In an embodiment, the NGRD photoresist can be omitted to form an NGRD layer. In contrast, in one embodiment, if the device is properly designed (eg, a single wafer 100), only NGRD is performed. The empty layout can also achieve the device characteristics required for the unit DDDMOS transistor without affecting other device characteristics. In one embodiment, the NGRD is implanted between about 1.0E12 atoms/cm2 and 9.0E13 atoms/cm2. The amount of NGRD implanted may vary, but needs to be within a certain range, thereby making the concentration of the NGRD layer smaller than the concentration of the N+ layer formed in step 31 and the depth of the NGRD layer slightly larger than the N+ layer formed in step 31. depth. Therefore, in step 211, an NGRD region (e.g., an NGRD layer) is formed according to steps 24-25.

After removing the seventh photoresist, in step 26, the eighth photoresist is deposited as an N-type lateral double drain (NLDD) reticle. In step 27, the implantation of the NLDD is performed using a patterned NLDD mask. Therefore, in step 213, the NLDD is formed according to steps 26-27.

In step 28, after deposition of tetraethyl orthosilicate (TEOS), dry etching of the spacer is performed in step 29. Thus, in step 215, an isolation layer is formed in accordance with steps 28-29.

After removing the eighth photoresist, in step 30, the ninth photoresist is deposited as an N+ mask. Subsequently, implantation of N+ source/drain (S/D) is performed in step 31. Again, a P-type highly doped (P+) reticle is used in step 32, and a P+ source/drain (S/D) implant is performed in step 33. Thus, in step 217, the source/drain is formed in accordance with steps 30-33.

After the borophosphorus bismuth glass (BPSG) deposition is performed in step 34, a borophosphonium glass stream is achieved in step 35 to smooth the surface of each of the layers and/or regions described above. In steps 36-37, etching is performed using a photomask to form different contacts. Backend metallization is performed in step 38. Therefore, in step 219, the backend process is performed in accordance with steps 34-38.

Thus, in one embodiment, the LDMOS transistor and the cell DDDMOS transistor can be integrated into the same IC 100 by adding an NGRD cloth plant to the process. In an embodiment, the NGRD cloth plant may be added after the polycrystalline germanium is formed and before the isolation layer is formed. In another embodiment, an isolation layer can be formed prior to the NGRD reticle and NGRD implantation process (step 211, steps 24-25) (step 215, steps 28-29). The process shown in Table 1 is for illustrative purposes and is not limited to this particular process.

3 is a block diagram of an MOS transistor having a laterally diffused (LD) architecture, such as LDMOS transistor 300, in accordance with an embodiment of the present invention. The LDMOS transistor 300 is fabricated in accordance with the process illustrated in FIG. 2 and/or Table 1, and can be used as the HV transistor in the controller circuit 110 of FIG. In an embodiment, the LDMOS transistor 300 may include a P-well (P-well) 301, an N-well (N-well) 303, an N-type highly doped (N+) layer/zone 311, and a P-type high doping (N+). Layer/Zone 313, N+ layer/Zone 315, and polysilicon gate 321 . The poly gate 321 includes an isolation layer 341. The LDMOS transistor 300 can also include field oxide layers/regions 331, 333, and 335.

In an embodiment, the N-well 303 is formed in steps 6-8. A P-well 301 is formed in step 9. Field oxide layers/regions 331, 333 and 335 are formed in steps 10-14. A poly gate 321 is formed in steps 15-23. The isolation layer 341 is formed in steps 28-29. N+ layers 311 and 315 are formed in step 31. A P+ layer 313 is formed in steps 32-33.

In an embodiment, the P-well 301 is adjacent to the N-well 303. The N+ layer 311 is adjacent to the P+ layer 313. The N+ layer 311 and the P+ layer 313 are at a predetermined depth in the P well 301 to constitute a source region. N+ layer 315 is pre-formed in N-well 303 At a given depth to form a bungee zone. The poly gate 321 is on the P well 301 and the N well 303 to form a gate region. Advantageously, in an embodiment, the LDMOS transistor 300 has enhanced reliability and is capable of having sufficient tolerance to undesired electrical/voltage stress conditions.

4 is a block diagram of an MOS transistor having a double diffused drain (DDD) architecture, such as an asymmetric DDDMOS transistor 400, in accordance with an embodiment of the present invention. The DDDMOS transistor 400 is fabricated in accordance with the process of FIG. 2 and/or Table 1, and can be used as the power MOSFET (eg, current switch or voltage switch) 120 of FIG. The DDDMOS transistor 400 has a high breakdown voltage, and thus the DDDMOS transistor 400 has a high withstand voltage capability. In an embodiment, DDDMOS transistor 400 may include P-well 401, N+ layer/region 411, N-type slope (NGRD) layer/region 413, N+ layer/region 415, P+ layer/region 417, and polysilicon gate 421. . The poly gate 421 includes an isolation layer 441. DDDMOS transistor 400 also includes field oxide layers/regions 431 and 433.

Elements in FIG. 4 that are similar to those in FIG. 3 are formed by the steps in Table 1/FIG. 2 as described in FIG. 2, and are not described herein again. Additionally, an NGRD layer 413 is formed in steps 24-25.

In an embodiment, the NGRD layer 413 is between the poly gate 421 and the N+ layer 415. Since the NGRD layer 413 surrounds the N+ layer 415, and the depth of the N+ layer 415 is less than the depth of the NGRD layer 413, the breakdown capability of the DDDMOS transistor 400 can be enhanced. In addition, the distance between the poly gate 421 and the N+ layer 415 can reduce the electric field strength and thus also enhance the breakdown capability of the DDDMOS transistor 400. Therefore, the breakdown voltage of the DDDMOS transistor 400 (for example, the voltage between the drain and the source) can be increased.

In an embodiment, the N+ layer 411, the NGRD layer 413, and the P+ layer 417 are formed in the P well 401. In an embodiment, the N+ layer 415 is formed in the NGRD layer 413 and may be formed of phosphorus or arsenic or the like. The NGRD layer 413 surrounds the N+ layer 415. In an embodiment, the concentration of the N+ layer 415 is greater than the concentration of the NGRD layer 413. The N+ layer 411 constitutes the source region of the DDDMOS transistor 400. The NGRD layer 413 and the N+ layer 415 constitute the drain region of the DDDMOS transistor 400. The poly gate 421 is located on a predetermined area of the P well 401 and the NGRD layer 413 to constitute a gate region of the DDDMOS transistor 400. Advantageously, in one embodiment, the DDDMOS transistor 400 has a smaller size and a faster reaction rate. In addition, by incorporating the NGRD layer 413 in the N+ layer 415 of the drain region, the breakdown breakdown characteristics of the DDDDMOS transistor 400 can be improved.

Accordingly, in an embodiment, a method for integrating a switch (power MOSFET) 120 and a controller circuit 110 that controls the switch is provided. In one embodiment, the method includes forming the NGRD layer 413 at an implant between about 1.0E12 atoms/cm2 to 9.0E13 atoms/cm2, and the plurality of transistors and switches 120 of the controller circuit 110 are fabricated in a single On the wafer. Among the plurality of transistors and switches 120 of the controller circuit 110 is a high voltage transistor. The method further includes forming the isolation layer 411 after forming the NGRD layer 413 or before forming the NGRD layer 413. The method also includes forming an N-type highly doped (N+) layer 415 surrounded by the NGRD layer 413. In an embodiment, the depth of the N+ layer 415 is slightly less than the depth of the NGRD layer 413. In an embodiment, the concentration of the N+ layer 415 is greater than the concentration of the NGRD layer 413. The plurality of transistors in the controller circuit 110 can be, but are not limited to, laterally diffused metal oxide semiconductor (LDMOS) transistors. Switch 120 It may be, but is not limited to, a unit double diffused drain metal oxide semiconductor (DDDMOS) transistor.

In one embodiment, a single integrated circuit 100 includes a switch 120 and a controller circuit 110 that controls the switch, wherein the switch 120 includes an N-type slope (NGRD) layer 413. The switch 120 also includes an N-type highly doped (N+) layer 415 and an NGRD layer 413 surrounding the N+ layer 415. The NGRD layer 415 and the N+ layer 413 form the drain region of the switch 120. Advantageously, fabrication techniques in accordance with one embodiment of the present invention can integrate switch 120 and controller circuit 110 on a single wafer, thereby reducing wafer size, enhancing reliability tolerance in high voltage applications, and reducing cost.

Advantageously, the controller circuit 110 in the IC 100 employs a plurality of LDMOS transistors, and the switch 120 employs a unit DDDMOS transistor (e.g., DDDMOS transistor 400), so the IC 100 has enhanced reliability and a smaller wafer size. Controller circuit 110 and switch 120 may employ other types of transistors without departing from the spirit and scope of the present invention. The IC 100 also enhances the breakdown capability of the DDDMOS transistor 400 by implanting the NGRD layer 413 in the DDDMOS transistor 400, thereby enhancing its reliability.

5 is a block diagram of an MOS transistor having a double diffused drain (DDD) architecture, such as an asymmetric DDDMOS transistor 500, in accordance with an embodiment of the present invention. The DDDMOS transistor 500 is fabricated in accordance with the process of FIG. 2 and/or Table 1, and the power MOSFET (eg, current switch or voltage switch) of FIG. 1 may employ the architecture of the DDDMOS transistor 500. The DDDMOS transistor 500 has a high breakdown voltage and, therefore, can enhance the high voltage withstand capability of the DDDMOS transistor 500. in In one embodiment, DDDMOS transistor 500 includes a P-type substrate 501, an N+ buried layer (NBL) 511, P-wells 521, 523, and 525, N-wells 522 and 524, a P+ layer/region 531, and an N+ layer/region 532, 533. , 534 and 535, NGRD layer 537 and polysilicon gate 541. The poly gate 541 includes an isolation layer 561. DDDMOS transistor 500 also includes field oxide layers/regions 551, 553, 555, and 557.

In an embodiment, the NGRD layer 537 is formed between the poly gate 541 and the N+ layer 535. Since the NGRD layer 537 surrounds the N+ layer 535, the breakdown capability of the DDDMOS transistor 500 is enhanced. In addition, the distance between the poly gate 541 and the N+ layer 535 can reduce the electric field strength, thereby enhancing the breakdown capability of the DDDMOS transistor 500. Thereby, the breakdown voltage of the DDDMOS transistor 500 (for example, the voltage between the drain and the source) can be increased.

Elements in FIG. 5 that are similar to those in FIG. 3/FIG. 4 are formed in the steps in Table 1/FIG. 2 as described in FIG. 3/FIG. 4, and are not described herein again. In addition, NBL 511 is formed in steps 2-5 in Table 1. In an embodiment, the NBL 511 isolates the P-wells 523 and 525 from the P-type substrate 501. Therefore, the potential of the P well 523 or 525 has a different potential than the P type substrate 501. A P+ layer 531, N+ layers 533 and 535, and an NGRD layer 537 are formed in the P well 521. In one embodiment, the concentration of the N+ layer 535 is greater than the concentration of the NFRD layer 537, and the depth of the N+ layer 535 is less than the depth of the NGRD layer. The P+ layer 531 and the N+ layer 533 constitute the source region of the DDDMOS transistor 500. A poly gate 541 is formed on a predetermined region of the P well 521 and the NGRD layer 537 to constitute a gate region of the DDDMOS transistor 500. The N+ layer 535 and the NGRD layer 537 constitute the drain region of the DDDMOS transistor 500. Advantageously, In an embodiment, the DDDMOS transistor 500 has a smaller size and a faster reaction rate. In addition, by incorporating the NGRD layer 537 into the N+ layer 535 of the drain region, the breakdown breakdown capability of the DDDMOS transistor 500 can be enhanced.

6 is a block diagram of an MOS transistor having a double diffused drain (DDD) architecture, such as an asymmetric DDDMOS transistor 600, in accordance with another embodiment of the present invention. Elements in FIG. 6 that are the same as those in FIG. 5 have similar functions and will not be described again.

In an embodiment, DDDMOS transistor 600 includes a field oxide layer/region 650 formed between poly gate 541 and NGRD layer 537. Field oxide layer 650 is adjacent to N+ layer 535. Advantageously, the implantation of the field oxide layer 650 can further enhance the breakdown voltage of the high voltage transistor (eg, DDDMOS transistor 600), thereby enhancing the high voltage withstand capability of the DDDMOS transistor 600. In an embodiment, the process of DDDMOS transistor 600 may be slightly different from Table 1. The implantation step of the NGRD (eg, steps 24-25) can be performed prior to the field oxidation step (eg, steps 10-14). Thus, the NGRD layer 537 can be formed under the field oxide layer 650, while the field oxide layers 551, 553, 555, 557, and 650 can be formed simultaneously in steps 10-14. In one embodiment, the NGRD implantation step can be performed before or after the field oxidation step, but an independent field oxide layer, such as field oxide layer 650 (which can be thicker or thinner), can be formed after the NGRD implantation step. An NGRD layer, such as NGRD layer 537, is located below separate field oxide layer 650.

7 is a cross-sectional view of the architecture of a unit cell, such as a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor 700, in accordance with an embodiment of the present invention. The same elements in Figure 7 as those in Figure 5/Figure 6 The parts are formed using steps similar to those in Table 1/Fig. 2 as shown in Fig. 5/Fig.

The unit DDDMOS transistor 700 can be fabricated according to the processes of Table 1, Figure 2, and/or Figures 4-6. The unit DDDMOS transistor 700 forms a plurality of gates in steps 15-18 of Table 1 as compared to the DDDMOS transistor 500/600, and forms a plurality of drains and sources in steps 30-33 of Table 1. .

7A is a top plan view of the architecture of a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor, such as cell DDDMOS transistor 700, in accordance with an embodiment of the present invention. The same elements in Fig. 7A as those in Fig. 7 are formed in the steps shown in Table 1/Fig. 2 as shown in Fig. 7. N Well 522 is the same as Well N 524, both formed in steps 6-8 of Table 1. Similarly, P-well 523 is identical to P-well 525, both formed in step 9 of Table 1.

8 is a block diagram of a unit cell, such as a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor 800, in accordance with another embodiment of the present invention. Figure 8 is described in conjunction with Figures 5-7. The unit DDDMOS transistor 800 is fabricated according to the process shown in Table 1, Figure 2, and/or Figures 4-7.

In an embodiment, the N-well 522/524 is coupled to the NBL 511 and formed after the NBL 511 is formed. N+ layer 532/534 is connected to N well 522/524 and formed after formation of N well 522/524. The unit DDDMOS transistor 800 can include a plurality of gates formed in steps 15-18 of Table 1 and a plurality of drains and sources formed in steps 30-33 of Table 1.

In one embodiment, all of the drains of cell DDDMOS transistor 800 are coupled to N-wells 522 and 524 via N+ layers 532 and 534, respectively. because Thus, all of the drains of the unit DDDMOS transistor 800 are connected to the NBL 511 via the N+ layer 532/534 and the N well 522/524. Therefore, the voltage values of all the drains of the unit DDDMOS transistor 800 are substantially equal to the voltage values of the NBL 511. Other methods of connecting all of the drains of the unit DDDMOS transistor 800 to the NBL 511 may be employed without departing from the spirit and scope of the present invention. For example, all of the drains of the unit DDDMOS transistor 800 can be connected to the NBL 511 by external wiring. Thus, cell DDDMOS transistor 800 forms an insulated power MOSFET that acts as a current switch. In an embodiment, all of the sources are connected together. In one embodiment, all of the poly gates are connected together. When all of the poly gates are set to logic 0, the cell DDDMOS transistor 800 is turned off. When all of the poly gates are set to logic 1, the cell DDDMOS transistor 800 is turned on and current flows from the drain to the source. Advantageously, the breakdown voltage (BV) of the cell DDDMOS transistor 800 can be increased to a higher value (eg, from 35 volts to 46 volts) while the on resistance can be kept low. The electrostatic discharge (ESD) characteristics of the unit DDDMOS transistor 800 can also be enhanced.

9 is a diagram showing an example of a potential gradient of a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor, such as cell DDDMOS transistor 700, in accordance with an embodiment of the present invention. Figure 9 is described in conjunction with Figures 7 and 7A.

In the breakdown voltage test, when the drain region is biased, the potential gradients 901-907 are as shown in FIG. In this case, all the drains of the cell DDDMOS transistor 700 are not connected to the NBL 511. At position 911 or 913, for example, the N+ bottom of gate 911 or drain 913 may collapse.

Figure 10 shows cell double diffusion in accordance with one embodiment of the present invention. An exemplary diagram 1000 of a potential gradient of a germanium metal oxide semiconductor (DDDMOS) transistor, such as cell DDDMOS transistor 800. Figure 10 is described in conjunction with Figure 8.

The drain regions, such as all of the drains of the cell DDDMOS transistor 800, are connected to the NBL 511 via an N-well 522/524 and an N+ layer 532/534. Therefore, the NBL 511 has substantially the same bias voltage as all the drains. In the breakdown voltage test, when the NBL 511 is biased via the bias voltages of all the drains of the cell DDDMOS transistor 800, the potential gradients 1001-1007 are as shown in FIG. The NBL 511 can deplete the P-well 521 below the bungee zone. A well P in the bungee area can produce a high breakdown voltage. Therefore, the higher the bias voltage of the drain region, the more easily the P well around the drain region is depleted, which can generate a higher breakdown voltage.

If the concentration of the NGRD layer 537 is relatively low (e.g., between about 1.0E12 atoms/cm2 to 9.0E13 atoms/cm2), the NGRD layer 537 provides a finite charge and the electric field in the gate region is relatively low. The N+ layer 535 of the drain region has more charge, and the electric field under the N+ layer 535 can reach a maximum value, thereby causing the N+ layer 535 to collapse. Advantageously, when the concentration of the NGRD layer 537 is relatively low, biasing the NBL 511 via the N-well 522/524 can facilitate boosting the breakdown voltage. The electrostatic discharge (ESD) characteristics of the unit DDDMOS transistor 800 can also be enhanced.

In addition, when the unit DDDMOS transistor 800 is biased to collapse, for example, when the bias voltage of the drain region is increased to a breakdown voltage, the cell DDDMOS transistor 800 is not damaged. In one embodiment, when the breakdown voltage is reset to zero, the cell DDDMOS transistor 800 is still intact. In an embodiment, all of the drains of the unit DDDMOS transistor 800 are via N Well 522/524 and N+ layer 532/534 are connected to NBL 511, and the voltage values of all the drains are substantially the same as those of NBL 511, N well 522/524, and N+ layer 532/534. Thus, in one embodiment, when an overshot noise voltage strikes the drain of the unit DDDMOS transistor 800 during normal operation, the N well to the P well (eg, N well 522/524 to P well 533/) 525) may collapse first, rather than the cell DDDMOS transistor 800 (eg, the drain region and the source region) itself collapsing, thus avoiding the induction of triggering the built-in NPN bipolar and avoiding damage to the cell DDDMOS transistor 800. When an unexpected overshooting noise voltage strikes the unit DDDMOS transistor 800, the N-to-P-well can act as an intrinsic diode to protect the unit DDDMOS transistor 800.

Figure 11 is a block diagram of a display system 1100 in accordance with one embodiment of the present invention. In an embodiment, display system 1100 includes a liquid crystal display (LCD) panel 1110. The inverter circuit 1111 can be used to convert a DC voltage DC from a power source (not shown) into an AC voltage AC, and power the plurality of light sources 1113 to illuminate the LCD panel 1110. The inverter circuit 1111 includes a inverter controller and one or more switches. In an embodiment, the inverter circuit 1111 can be integrated into an integrated circuit, similar to the architecture including the controller circuit 110 and one or more switches 120 shown in FIG.

In an embodiment, the switch 120 can employ, but is not limited to, any one of the above-described transistors. For example, switch 120 can employ a unit DDDMOS transistor (such as DDDDMOS transistor 800 in FIG. 8), including, for example, the architecture of DDDMOS transistor 500 in FIG. 5 or DDDMOS transistor 600 in FIG.

Thus, in an embodiment, the switch 120 and the controller circuit 110 that controls the switch 120 can be integrated on a single IC 100. A unit transistor (e.g., unit DDDMOS transistor 800) employing a DDDMOS transistor 400/500/600 architecture can be used as the switch 120. The unit DDDMOS transistor 800 includes an NBL 511, an N-well 522/524 connected to the NBL 511, and an N+ layer 532/534 connected to the N-well 522/524. The unit DDDMOS transistor 800 also includes a plurality of drains, a plurality of sources, and a plurality of poly gates. In one embodiment, all of the drains of cell DDDMOS transistor 800 are coupled to NBL 511 via N+ layer 532/534 and N well 522/524. Therefore, the unit DDDMOS transistor 800 can function as an insulating MOS transistor. Advantageously, the breakdown voltage of the cell DDDMOS transistor 800 can be increased to a higher voltage value while maintaining a lower on-resistance. The electrostatic discharge (ESD) characteristics of the unit DDDMOS transistor 800 can also be enhanced. The type of transistor employed by the controller circuit 110 and the switch 120 is not limited to the above-described transistors, and other types of transistors may be employed without departing from the spirit and scope of the present invention.

The above detailed implementation modes and drawings are merely common embodiments of the present invention. It is apparent that various additions, modifications, and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood by those of ordinary skill in the art that the present invention can be applied in the form of the form, the structure, the arrangement, the ratio, the materials, the elements, the components, and the like in the actual application and the specific requirements. Changed. Therefore, the embodiments disclosed herein are intended to be illustrative and not limiting, and the scope of the invention is defined by the scope of the appended claims

100‧‧‧Integrated Circuit (IC) / Wafer

110‧‧‧Controller Circuit

120‧‧‧ switch

200‧‧‧flow chart

201-219‧‧‧Steps

300‧‧‧Transverse Diffusion Transistor (LDMOS)

301‧‧‧P type well (P well)

303‧‧‧N type well (N well)

311‧‧‧N-type highly doped (N+) layer/zone

313‧‧‧P-type highly doped (N+) layer/zone

315‧‧‧N+ floor/zone

321‧‧‧ polycrystalline gate

341‧‧‧Isolation

331, 333, 335‧ ‧ field oxide layer / zone

400, 500, 600‧ ‧ double diffused drain (DDDMOS) transistors

401‧‧‧P well

411‧‧‧N+ floor/zone

413‧‧‧N grade slope (NGRD) layer/zone

415‧‧‧N+ floor/zone

417‧‧‧P+ floor/zone

421‧‧‧ polycrystalline gate

441‧‧‧Isolation

431, 433‧‧‧ field oxide layer/zone

501‧‧‧P type substrate

511‧‧‧N+ buried layer (NBL)

521, 523, 525‧‧‧P well

522, 524‧‧‧N well

531‧‧‧P+ floor/zone

532, 533, 534, 535‧‧‧N+ layers/districts

537‧‧‧NGRD layer

541‧‧‧ polycrystalline gate

561‧‧‧Isolation

551, 553, 555, 557‧‧‧ field oxide layer/zone

650‧‧‧ field oxide layer/zone

700, 800‧‧‧ unit double diffused drain (DDDMOS) transistor

901-907, 1001-1007‧‧‧ potential gradient

911‧‧‧ position/gate

913‧‧‧Location/Bungee

1100‧‧‧Display system

1110‧‧‧Liquid Crystal Display (LCD) Panel

1111‧‧‧inverter circuit

1113‧‧‧Light source

1 is a block diagram of an integrated circuit in accordance with an embodiment of the present invention.

2 is a flow diagram of a process for integrating a switch and controller circuit on a single wafer in accordance with one embodiment of the present invention.

3 is a block diagram of a laterally diffused metal oxide semiconductor (LDMOS) transistor in accordance with an embodiment of the present invention.

4 is a block diagram of an asymmetric double diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with an embodiment of the present invention.

Figure 5 is a block diagram of a dual diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with one embodiment of the present invention.

6 is a block diagram of a double diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with another embodiment of the present invention.

7 is a cross-sectional view showing the architecture of a unit double diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with an embodiment of the present invention.

7A is a top plan view of the architecture of a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with an embodiment of the present invention.

Figure 8 is a block diagram of a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with another embodiment of the present invention.

Figure 9 is a diagram showing an example of a potential gradient of a cell double diffused drain metal oxide semiconductor (DDDMOS) transistor in accordance with one embodiment of the present invention.

Figure 10 shows cell double diffusion in accordance with one embodiment of the present invention. An example plot of the potential gradient of a drain metal oxide semiconductor (DDDMOS) transistor.

Figure 11 is a block diagram of a display system in accordance with one embodiment of the present invention.

100‧‧‧Integrated Circuit (IC) / Wafer

110‧‧‧Controller Circuit

120‧‧‧ switch

Claims (25)

A cellular transistor comprising: an N-type highly doped (N+) buried layer (NBL); an N-well connected to the NBL, the N-well formed after the NBL is formed; connected to the N-well a first N+ layer formed after the formation of the N well; a P well, a portion of the P well surrounded by the NBL and the N well; and a plurality of drains adjacent to the P well, wherein Each of the drains includes a second N+ layer connected to the NBL via the N well and the first N+ layer; and a source formed on the P well, wherein the source includes a third N+ a layer, a channel is formed between the second N+ layer of each of the drains and the third N+ layer of the source; wherein when one of the drain electrodes increases in voltage, one of the unit transistors collapses The voltage increases. The unit cell of claim 1, wherein each of the plurality of drains further comprises an N-type slope (NGRD) layer surrounding the second N+ layer. The unit cell of claim 2, wherein the depth of the second N+ layer is less than the depth of the NGRD layer, and wherein the concentration of the second N+ layer is greater than the concentration of the NGRD layer. The unit cell of claim 2, wherein the NGRD layer is formed at a planting amount of between about 1.0E12 atoms/cm2 and 9.0E13 atoms/cm2. The unit transistor of claim 1, further comprising: a plurality of sources, wherein the plurality of sources are connected together. The unit cell of claim 1, further comprising: a plurality of polysilicon gates, wherein the plurality of polysilicon gates are connected together. A cell transistor according to claim 6 wherein a field oxide layer is formed between each of the polysilicon gates and each of the drain electrodes. The unit cell of claim 7, wherein each of the drains further comprises an N-type slope (NGRD) layer surrounding the second N+ layer, and wherein the field oxide layer and the second N+ layer Adjacent. The unit cell of claim 1, wherein the breakdown voltage comprises a 汲-source breakdown voltage between each of the drain electrodes and a source of the unit transistor. The unit cell of claim 1, wherein when the drain voltage is increased, the NBL depletes the P well below the drain. The unit cell of claim 1, wherein the P well is formed above the NBL and adjacent to the N well. An integrated circuit comprising: a switch comprising a cellular transistor, wherein the unit transistor comprises: an N-type highly doped (N+) buried layer (NBL); and an N well connected to the NBL The N well is formed after the NBL is formed; a first N+ layer connected to the N well, the first N+ layer being formed after the N well is formed; a P well, a portion of the P well being surrounded by the NBL and the N well; a plurality of drains adjacent to the P well, wherein each of the drains includes a second N+ layer, via the N well and the first An N+ layer is coupled to the NBL; a source is formed on the P well, wherein the source includes a third N+ layer, the second N+ layer of each of the drains, and the third of the source A channel is formed between the N+ layers; and a controller circuit coupled to the switch and controlling the switch; wherein when one of the drain electrodes increases in voltage, a breakdown voltage of one of the unit transistors increases. The integrated circuit of claim 12, wherein each of the drains includes an N-type slope (NGRD) layer surrounding the second N+ layer. The integrated circuit of claim 13, wherein the depth of the second N+ layer is less than the depth of the NGRD layer, and wherein the concentration of the second N+ layer is greater than the concentration of the NGRD layer. The integrated circuit of claim 13, wherein the NGRD layer is formed at a planting amount of between about 1.0E12 atoms/cm2 and 9.0E13 atoms/cm2. The integrated circuit of claim 12, wherein the unit transistor further comprises: a plurality of sources, wherein the plurality of sources are connected together. The integrated circuit of claim 12, wherein the unit transistor further comprises: a plurality of polysilicon gates, wherein the plurality of polysilicon gates are connected together. For example, in the integrated circuit of claim 17, a field oxide layer is formed between each of the poly gates and each of the drain electrodes. The integrated circuit of claim 18, wherein each of the drains further includes an N-type slope (NGRD) layer surrounding the second N+ layer, and wherein the field oxide layer and the second N+ layer Adjacent. The integrated circuit of claim 12, wherein the unit transistor comprises a double diffused drain metal oxide semiconductor (DDDMOS) transistor. The integrated circuit of claim 12, wherein the controller circuit comprises a plurality of laterally diffused metal oxide semiconductor (LDMOS) transistors. The integrated circuit of claim 12, wherein the breakdown voltage comprises a 汲-source breakdown voltage between each of the drains and a source of the unit transistor. The integrated circuit of claim 12, wherein when the drain voltage is increased, the NBL depletes the P well below the drain. The integrated circuit of claim 12, wherein the controller circuit sets a poly gate of the unit transistor to logic 1, and a current flows from one of the drains to the unit transistor. A source. The integrated circuit of claim 12, wherein the P well is formed above the NBL and adjacent to the N well.