CN103632941A - Semiconductor device comprising metal gate, and preparation method thereof - Google Patents
Semiconductor device comprising metal gate, and preparation method thereof Download PDFInfo
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- CN103632941A CN103632941A CN201210303576.6A CN201210303576A CN103632941A CN 103632941 A CN103632941 A CN 103632941A CN 201210303576 A CN201210303576 A CN 201210303576A CN 103632941 A CN103632941 A CN 103632941A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 52
- 239000002184 metal Substances 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000007769 metal material Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 23
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 23
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005868 electrolysis reaction Methods 0.000 claims abstract description 14
- 239000003792 electrolyte Substances 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 184
- 230000004888 barrier function Effects 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 14
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000000428 dust Substances 0.000 claims description 6
- 239000011780 sodium chloride Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000354 decomposition reaction Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 235000006408 oxalic acid Nutrition 0.000 claims description 3
- XEEVLJKYYUVTRC-UHFFFAOYSA-N oxomalonic acid Chemical compound OC(=O)C(=O)C(O)=O XEEVLJKYYUVTRC-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 6
- 235000010210 aluminium Nutrition 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000010405 anode material Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000036647 reaction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention relates to a semiconductor device comprising a metal gate, and a preparation method thereof. The method comprises: providing a semiconductor substrate comprising the metal gate, the top layer of the metal gate being a metal material layer; performing electrolysis in an electrolyte by taking the metal material layer as an anode, and forming a metal oxide material layer provided with micropores on the surface of the metal material layer so as to enhance the adherence performance between the metal material layer and a contract hole etching stop layer formed above the metal material layer. According to the invention, electrolysis is performed on the metal material layer, the metal oxide layer is generated on the surface of the metal material layer, and since the metal oxide layer is provided with the uniformly distributed micropores and has a rougher surface so that the adhesive force between the metal oxide layer and the contract hole etching stop layer formed on the metal oxide layer is stronger, the two layers are not separated during an etching or flattening process, and no shedding occurs any more.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to semiconductor device of a kind of containing metal grid and preparation method thereof.
Background technology
At integrated circuit, manufacture field, along with constantly dwindling of MOS transistor, especially in the technique below 32nm, it is various because the second-order effect that the physics limit of device is brought is inevitable, the scaled difficulty that becomes of characteristic size of device, easily there is the electric leakage problem from grid to substrate in MOS transistor device and circuit thereof the field of manufacturing wherein.
The solution of current technique is the method that adopts high-K gate material and metal gate, first the forming process of metal current grid for forming gate dielectric 101 in Semiconductor substrate 100, on gate dielectric 101, form the TiN cover layer 102 of stack structure, deposit and spread barrier layer 103 on TiN layer 102.Etching forms metal gates, and described metal gates comprises function metal level, barrier layer and metal material layer.Then described grid and source are leaked to formation electrical connection, be in particular: at described metal material layer 107(metallic aluminium) upper deposition contact etch stop layer 104, on described contact etch stop layer, form oxide skin(coating) 106, oxide skin(coating) 106 and contact etch stop layer described in etching, with above described grid and source, both sides leak to form contact hole, and then formation contact plug 105, but because the adhesion between described metal material layer 107 metallic aluminiums and described contact etch stop layer SiN layer is very little, be easy to cause coming off of described metal material layer 107 and cracked in forming contact hole and described metal gate being carried out to the process of wet-cleaned carrying out etching, make described device failure.
In the preparation process of metal current grid, mostly select metallic aluminium as conductive layer, have easy coming off and cracked problem described above, current preparation method can not solve described problem, therefore need to improve technology or technical process.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device of containing metal grid, comprising:
One Semiconductor substrate that comprises metal gates is provided, and the superiors of described metal gates are metal material layer;
Take described metal material layer as anode, in electrolyte, carry out electrolysis, on described metal material layer surface, form the layers of metal oxide materials with micropore, to strengthen described metal material layer and its top by the adhesion property between the contact etch stop layer forming.
As preferably, described metal material layer is the aluminium bed of material.
As preferably, described contact etch stop layer is silicon nitride layer.
As preferably, described electrolyte is the mixed solution of oxalic acid and NaCl.
As preferably, the concentration of described electrolyte mesoxalic acid is 0.5-3mol/L.
As preferably, in described electrolyte, the concentration of NaCl is 0.1-1mol/L.
As preferably, described decomposition voltage is 1-30 volt.
As preferably, the current density of described electrolysis is 1-100A/m
2.
As preferably, described electrolysis time is 1-10 minute.
As preferably, described micropore is uniformly distributed in described layers of metal oxide materials, and the diameter of described micropore is 100nm-200nm.
As preferably, between described micropore, be spaced apart 300nm-500nm.
As preferably, the formation method of described metal gates is:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid stack layer, comprise the high k dielectric layer, TiN cover layer, the polysilicon layer that stack gradually, and the barrier layer between described TiN cover layer and polysilicon layer;
Described in etching, grid stack layer to form dummy gate electrode structure on described substrate;
Remove the described polysilicon layer of described dummy gate electrode structure;
On described barrier layer, form metal gates.
As preferably, described barrier layer is TaN or AlN layer, and the thickness on described barrier layer is 10-50 dust.
As preferably, described metal gates is comprised of the workfunction layers stacking gradually, barrier layer and metal material layer.
As preferably, described in forming, have after microporous aluminum oxide material layer, further comprise following steps:
On described alumina material layer, form contact etch stop layer;
On described contact etch stop layer, form interlayer dielectric layer;
Described in etching, interlayer dielectric layer and described contact etch stop layer form contact hole, expose described layers of metal oxide materials;
Adopt metallic conduction material to fill described contact hole, form contact plug, to form electrical connection.
As preferably, described contact etch stop layer is metal nitride layer.
As preferably, described interlayer dielectric layer is oxide skin(coating).
The semiconductor device that the present invention also provides a kind of said method to prepare.
In the present invention described metal material layer is carried out to electrolysis, Surface Creation layers of metal oxide materials at metal material layer, owing to thering is equally distributed micropore in described layers of metal oxide materials, surface is more coarse, adhesion between the formed contact etch stop layer in described layers of metal oxide materials and top is stronger, therefore in the process of etching or planarization, both can be not separated, no longer comes off; And owing to thering is equally distributed micropore in described layers of metal oxide materials, the machining property of described layers of metal oxide materials strengthens, brittleness reduces, in stress situation, more easily suffered power is passed through to described micropore dispersion, toughness is better, has solved the easy chipping problem of this metal level in prior art.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is metal gate structure schematic diagram in prior art;
Fig. 2 A-K is that the semiconductor device that the present invention contains metal gates is prepared schematic diagram;
Fig. 3 is the semiconductor device preparation flow figure that the present invention contains metal gates.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that semiconductor and the manufacture method thereof of the containing metal grid that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, do not exist or add one or more other features, integral body, step, operation, element, assembly and/or their combination next, in connection with accompanying drawing, more intactly describing the present invention.
Fig. 3 is the process chart of a kind of embodiment of the present invention, and in conjunction with Fig. 2 A-K, the method for being prepared by the present invention to described semiconductor device is described further.
Particularly, described Semiconductor substrate 200 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In described substrate, can be formed with doped region and/or isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In an embodiment of the present invention, described substrate can be Si substrate, and it can also be included in the SiO on Si
2boundary layer 210, forms SiO by rapid thermal oxidation process (RTO) or atom layer deposition process (ALD)
2boundary layer.
Particularly, on this substrate, form gate dielectric 201, can select hafnium to form described gate dielectric, for example, be used in Hfo
2middlely introduce the elements such as Si, Al, N, La, Ta and optimize hafnium that the ratio of each element obtains etc.The method of described formation gate dielectric can be physical gas-phase deposition or atom layer deposition process.In an embodiment of the present invention, at described SiO
2on boundary layer, form gate dielectric, its thickness is 15 to 60 dusts.Afterwards, form the TiN cover layer 202 of stack structure on gate dielectric 201, then deposit and spread barrier layer 203 on TiN layer 202, can be TaN layer or AlN layer.On diffusion impervious layer 203, deposit afterwards the grid electrode layer 204 that comprises polycrystalline silicon material.
Described in step 303 etching, grid stack layer to form dummy gate electrode structure on described substrate;
Particularly, as shown in Figure 2 B, can use photoetching process to the formed SiO of above step
2boundary layer 210, gate dielectric 201, TiN layer 202 and TaN layer or AlN layer 203, grid electrode layer 204 carry out patterned process, obtain described dummy gate structure, and formed grid has the structure of storehouse.
Then, as shown in Figure 2 C, form the step of offset side wall (offset spacer) 211.The material of offset side wall can be the insulating material such as silicon nitride, silica or silicon oxynitride.Offset side wall can improve the transistorized channel length of formation, the hot carrier's effect that reduces short-channel effect and cause due to short-channel effect.
As preferably, in this step, can also comprise following steps:
Form light dope source electrode/drain electrode (LDD) in the substrate of grid structure either side.The method of described formation LDD can be ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will form, and the device forming is nmos device, and the foreign ion mixing in LDD injection technology is a kind of or combination in phosphorus, arsenic, antimony, bismuth; If the device forming is PMOS device, the foreign ion injecting is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.
On substrate 200 and the formed offset side wall of above-mentioned steps, form clearance wall (Spacer) 212, can use the material of silicon nitride, carborundum, silicon oxynitride or its combination.Can on substrate, deposit the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer, then adopt engraving method to form clearance wall, described clearance wall can have the thickness of 10-30NM.Then, with ion implantation technology or diffusion technology heavy doping source electrode and drain electrode (S/D), be formed in the substrate of grid gap wall either side.Can also comprise annealing steps, form the steps such as bag shape injection region, NiSi deposition.
At device surface, form metal silicide (SAB) barrier layer, can use TEOS and oxygen to form oxide-film as SAB film, then by photoetching and dry quarter, form SAB district.Preferably, can also before the SAB film forming, first deposit SiN film to eliminate the impact in the photoetching of SAB film and etching, meeting side wall being etched away.
At surface deposition etching stopping layer 221, as shown in Figure 2 D, etching stopping layer can be used the formation such as SiCN, SiN, SiC, SiOF, SiON.Then deposit interlayer dielectric layer (ILD) 220 on grid structure.Can adopt the methods such as chemical vapour deposition technique, high density plasma CVD method, method of spin coating, sputter to form.Described interlayer dielectric layer can adopt the materials such as silica, silicon oxynitride, silicon nitride.
The interlayer dielectric layer depositing in interlayer dielectric layer 220 and above step is carried out to planarization, as shown in Figure 2 E.The limiting examples of described planarization comprises mechanical planarization method and chemico-mechanical polishing flattening method.To expose the upper surface of grid structure and it be roughly positioned in a plane with interlayer dielectric layer 220.
Particularly, remove the dummy gate electrode of PMOS, form groove 300.The method of described removal can be chemical etching.Gas used in etching process comprises HBr, and it is as main etching gas; Also comprise as 0 of etching make-up gas
2or Ar, it can improve the quality of etching.After this step, the final thickness of the TaN in PMOS or AlN layer 203 is between 10-30 dust.
Particularly, as shown in Figure 2 F, form the step of PMOS metal gates 301.Described metal gates forms by depositing a plurality of film storehouses.Described film comprises workfunction layers, barrier layer and metal material layer.Described barrier layer comprises TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or above-mentioned combination.Described deposited barrier layer method limiting examples comprises chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD).
The method of using in one embodiment of the invention ald (ALD), sputter and physical vapour deposition (PVD) (PVD), the thickness on formed barrier layer is between 10-100 dust.Described workfunction layers comprises one or more layers metal level.Described metal level can be TiN, TaN, TiN and TaN, above-mentioned combination.Described metal level can use the method for ALD, PVD or CVD to form.Preferably, the thickness of described workfunction layers is between 10-200 dust.
Described metal material layer can deposit by the method for CVD or PVD.After this conductive layer forms, under 300-500 degree celsius temperature, anneal.It is 10-60 minute in the time containing reacting in nitrogen environment.Finally carry out the planarization of conductive layer, to remove the conductive layer beyond groove 300, form PMOS metal gates 301.
Then, can select the method for above-mentioned formation PMOS metal gate to form NMOS metal gate, with reference to figure 2F, the removal of carrying out the dummy gate electrode of NMOS with photoetching and etching method forms groove 400.After this step, the final thickness of the TaN in NMOS or AlN layer 203 is between 5-20 dust.Then, with reference to Fig. 2 G, form the step of NMOS metal gates 401.
Step 306 be take metal material layer in described metal gates and, as anode carries out electrolysis in electrolyte, on described metal material layer surface, is formed and have micropore metal layer of oxide material,
Particularly, as shown in Fig. 2 H, the described metal material layer of usining carries out electrolysis as anode in electrolyte, at metal material layer of the present invention, is preferably metallic aluminum material layer, in said case, following reaction occurs on negative electrode, emits H
2: 2H++2e → H
2, on anode, there is following reaction, 4OH-4e → 2H
2o+O
2, the oxygen of separating out is not only the oxygen (O of molecular state
2), also comprise elemental oxygen (O), and ion-oxygen (O
-2), conventionally in reaction, with molecular oxygen, representing, the oxygen that anode material metallic aluminum material layer is separated out on it is simultaneously oxidized, and forms anhydrous Al
2o
3film: 2Al+3[O]=AI
2o
3+ 1675.7KJ, it should be noted that, the oxygen of described generation be not in the present invention all with aluminium effect, a part with the form of gaseous state, separate out.
As preferably, in an embodiment of the present invention, described electrolyte is the mixed solution of oxalic acid and NaCl, wherein, the concentration of described electrolyte mesoxalic acid is 0.5-3mol/L, and in described electrolyte, the concentration of NaCl is 0.1-1mol/L, in this cell reaction, described decomposition voltage is 1-30 volt, and the current density of described electrolysis is 1-100A/m
2, described electrolysis time is 1-10 minute.
By the operation of this step, at the tip position of described metal material layer, form one deck and there is micropore metal layer of oxide material, as shown in Fig. 2 I, described micropore is evenly distributed, the diameter of described micropore is 100nm-200nm, between described micropore, there is certain interval, between described micropore, be spaced apart 300nm-500nm.
In the present invention described metal material layer is carried out to electrolysis, Surface Creation layers of metal oxide materials at metal material layer, owing to thering is equally distributed micropore in described layers of metal oxide materials, surface is more coarse, adhesion between the formed contact etch stop layer in described layers of metal oxide materials and top is stronger, therefore in the process of etching or planarization, both can be not separated, no longer comes off; And owing to thering is equally distributed micropore in described layers of metal oxide materials, the machining property of described layers of metal oxide materials strengthens, brittleness reduces, in stress situation, more easily suffered power is passed through to described micropore dispersion, toughness is better, has solved the easy chipping problem of this metal level in prior art.
Step 307 forms contact etch stop layer in described layers of metal oxide materials, and it can be metal nitride layer, in described metal nitride layer, forms interlayer dielectric layer, and it can be oxide skin(coating);
Particularly, first carry out a planarisation step, remove described layers of metal oxide materials, for example alumina material layer, itself and described interlayer dielectric layer 220 are positioned in a plane, as shown in Fig. 2 J, then deposit contact etch stop layer, described contact etch stop layer is preferably metal nitride layer, further preferred silicon nitride layer 212, on described metal nitride, deposit interlayer dielectric layer 213, be preferably oxide skin(coating), described oxide skin(coating) can be SiOF, SiON or SiO
2, as shown in Fig. 2 K.
Contact etch stop layer and interlayer dielectric layer described in step 308 etching, form contact hole; Expose described metal material layer, adopt metallic conduction material to fill described contact hole, form contact plug, to form electrical connection;
Particularly, at described contact etch stop layer (metal nitride) and the upper mask that forms of interlayer dielectric layer (oxide skin(coating)), then carry out etching, on described NMOS and PMOS grid, form contact hole respectively, then filled conductive material in described contact hole, finally carries out planarization, on described grid, forms contact plug, for being electrically connected to, as shown in Fig. 2 K.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. a preparation method for the semiconductor device of containing metal grid, comprising:
One Semiconductor substrate that comprises metal gates is provided, and the superiors of described metal gates are metal material layer;
Take described metal material layer as anode, in electrolyte, carry out electrolysis, on described metal material layer surface, form the layers of metal oxide materials with micropore, to strengthen described metal material layer and its top by the adhesion property between the contact etch stop layer forming.
2. method according to claim 1, is characterized in that, described metal material layer is the aluminium bed of material.
3. method according to claim 1, is characterized in that, described contact etch stop layer is silicon nitride layer.
4. method according to claim 1, is characterized in that, described electrolyte is the mixed solution of oxalic acid and NaCl.
5. method according to claim 4, is characterized in that, the concentration of described electrolyte mesoxalic acid is 0.5-3mol/L.
6. method according to claim 4, is characterized in that, in described electrolyte, the concentration of NaCl is 0.1-1mol/L.
7. method according to claim 1, is characterized in that, described decomposition voltage is 1-30 volt.
8. method according to claim 1, is characterized in that, the current density of described electrolysis is 1-100A/m
2.
9. method according to claim 1, is characterized in that, described electrolysis time is 1-10 minute.
10. method according to claim 1, is characterized in that, described micropore is uniformly distributed in described layers of metal oxide materials, and the diameter of described micropore is 100nm-200nm.
11. methods according to claim 1, is characterized in that, between described micropore, are spaced apart 300nm-500nm.
12. methods according to claim 1, is characterized in that, the formation method of described metal gates is:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid stack layer, comprise the high k dielectric layer, TiN cover layer, the polysilicon layer that stack gradually, and the barrier layer between described TiN cover layer and polysilicon layer;
Described in etching, grid stack layer to form dummy gate electrode structure on described substrate;
Remove the described polysilicon layer of described dummy gate electrode structure;
On described barrier layer, form metal gates.
13. methods according to claim 12, is characterized in that, described barrier layer is TaN or AlN layer, and the thickness on described barrier layer is 10-50 dust.
14. methods according to claim 12, is characterized in that, described metal gates is comprised of the workfunction layers stacking gradually, barrier layer and metal material layer.
15. methods according to claim 1, is characterized in that, described in forming, have after microporous aluminum oxide material layer, further comprise following steps:
On described alumina material layer, form contact etch stop layer;
On described contact etch stop layer, form interlayer dielectric layer;
Described in etching, interlayer dielectric layer and described contact etch stop layer form contact hole, expose described layers of metal oxide materials;
Adopt metallic conduction material to fill described contact hole, form contact plug, to form electrical connection.
16. methods according to claim 15, is characterized in that, described contact etch stop layer is metal nitride layer.
17. methods according to claim 15, is characterized in that, described interlayer dielectric layer is oxide skin(coating).
18. 1 kinds of semiconductor device that prepared by the described method of one of claim 1 to 17.
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