CN104979181B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN104979181B CN104979181B CN201410141701.7A CN201410141701A CN104979181B CN 104979181 B CN104979181 B CN 104979181B CN 201410141701 A CN201410141701 A CN 201410141701A CN 104979181 B CN104979181 B CN 104979181B
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Abstract
The present invention provides a kind of manufacturing methods of semiconductor devices, including step：Gate groove is formed on substrate；Gate dielectric layer and metal gate layers thereon are formed in gate groove；Diffusion impervious layer is formed in metal gates layer surface；Using ALD process filling tungsten layers, the specific steps are：Pass through the alternately first reaction and the second reaction-filling tungsten layer, wherein the reaction gas of the first reaction includes siliceous reaction gas, and the reaction gas of the second reaction includes borine.The present invention forms tungsten layer by being alternately passed through silicon-containing gas and borane gases being reacted, while the filling perforation performance that ensure that tungsten, it avoids in gate dielectric layer and grid of the boron element under the interface of diffusion impervious layer is enriched with and is penetrated into, the integrated reliability of rear road CMP process is improved, while also reducing resistance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of manufacturing method of semiconductor devices.
Background technology
Currently, the research in CMOSFET (complementary metal oxide semiconductor field effect transistor) manufacturing process can be general
It is divided into both direction, i.e., preceding grid technique and rear grid technique.
Grid technique is now widely used in advanced integrated circuit technology manufacture afterwards, is typically to be initially formed pseudo- grid and source
Drain region then removes pseudo- grid and refills the replacement gate of high-k/metal gate stacking in gate groove.Since grid is formed in source
After drain electrode, grid need not bear very high annealing temperature in this technique, to grid layer material selection more extensively and more can body
The intrinsic characteristic of existing material.
It prepares the metals such as Al, Mo the prior art mainly adopts conventional methods such as CVD, PVD and is filled out as the metal of replacement gate
Layer is filled, however its step coverage is poor, subsequent CMP process is difficult to realize the control to the ultra-thin metal layer of small size device
System, the quality of the metal layer of preparation cannot be satisfied 40nm technological requirements below.
ALD (atomic layer deposition) technique is the surface limited reactions based on chemical absorbing, and it is heavy to be capable of providing intrinsic single layer
Product, with 100% step coverage in high-aspect-ratio gap.Currently, generally use ALD techniques carry out in rear grid technique
Filling to form the top-level metallic of replacement gate for tungsten (W), has good step coverage rate and gap filling energy to provide
The high-test metal layer of power, meets the requirement of the device of 40nm or less sizes.
However, when ALD prepares W, borine (B is mostly used2H6) and WF6It is used as predecessor, wherein B can diffuse into metal
In the gate insulating layer of grid and high-g value, this can influence the Performance And Reliability of device.
Invention content
The purpose of the present invention aims to solve at least above-mentioned technological deficiency, provides a kind of manufacturing method of semiconductor devices, keeps away
The diffusion for exempting from boron when ALD prepares W, improves the performance of device.
The present invention provides a kind of manufacturing methods of semiconductor devices, are applied in rear grid technique, including：
Gate groove is formed on substrate；
Gate dielectric layer and metal gate layers thereon are formed in gate groove；
Diffusion impervious layer is formed in metal gates layer surface, diffusion impervious layer forming step includes：Chip is sent into CVD
Reaction equation is heated to 300 DEG C to be preheated to chip；It is passed through silane gas, deposit forms thin silicone layer, to be spread
Barrier layer, thin silicone layer are monoatomic silicon layer；
Using ALD process filling tungsten layers, the specific steps are：Pass through the alternately first reaction and the second reaction-filling tungsten
Layer, wherein the reaction gas of the first reaction includes silicon-containing gas, and the reaction gas of the second reaction includes borine.
Optionally, the silicon-containing gas is silane or silicon ethane.
Optionally, the step of formation diffusion impervious layer is specially：
It is preheated；
By the way that silicon-containing gas to be carried out to the diffusion impervious layer for being decomposed to form silicon.
Optionally, the step of forming diffusion impervious layer is：Using ALD techniques, NH is carried out to metal gate layers3Surface
Pretreatment；It is passed through tungsten fluoride, forms the diffusion impervious layer of tungsten nitride on the surface of metal gate layers.
Optionally, further include step being formed between gate dielectric layer and metal gate layers：Cap layer is formed, to stop upper layer
Metal ion diffuses in gate dielectric layer.
Optionally, the cap layer is Ti, Ta, TaN, TiN, WN and combinations thereof.
Optionally, the temperature range in ALD techniques is 250-350 °.
Optionally, the deposition rate of the second reaction is less than the deposition rate of the first reaction.
Optionally, the deposition rate of the first reaction is
Optionally, the deposition rate of the second reaction is
Semiconductor devices provided in an embodiment of the present invention and its manufacturing method pass through friendship when using ALD process filling tungsten
Tungsten layer is formed for being passed through silicon-containing gas and borane gases being reacted, while the filling perforation performance that ensure that tungsten, is avoided
In gate dielectric layer and grid of the boron element under the interface of diffusion impervious layer is enriched with and is penetrated into, grid electricity is reduced
Resistance, meanwhile, the adhesiveness with barrier layer is improved, the window of tungsten flatening process is increased, improves the reliability of device.
Description of the drawings
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, wherein：
Fig. 1 shows the flow chart of the manufacturing method of semiconductor devices according to the ... of the embodiment of the present invention；
Fig. 2-14 shows that manufacturing method according to the ... of the embodiment of the present invention forms each manufacturing process of semiconductor devices
Schematic cross-section.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not construed as limiting the claims.
In order to reduce the diffusion of boron when ALD prepares W, the performance of device is improved, the present invention proposes a kind of semiconductor devices
Manufacturing method, as shown in Figure 1, include step：Gate groove is formed on substrate；
Gate dielectric layer and metal gate layers thereon are formed in gate groove；
Diffusion impervious layer is formed in metal gates layer surface；
Using ALD process filling tungsten layers, the specific steps are：Pass through the alternately first reaction and the second reaction-filling tungsten
Layer, wherein the reaction gas of the first reaction includes siliceous reaction gas, and the reaction gas of the second reaction includes borine.
In the present invention, it when using ALD process filling tungsten, is carried out instead by being alternately passed through silicon-containing gas and borane gases
Tungsten layer should be formed, the filling perforation performance that ensure that tungsten while, avoid boron element the interface of diffusion impervious layer be enriched with
And in the gate dielectric layer and grid under being penetrated into, resistance is reduced, meanwhile, the adhesiveness with barrier layer is improved,
The window for increasing tungsten flatening process improves the reliability of device.
In order to better understand the present invention, it is described in detail below with reference to specific embodiment and attached drawing.
First, pseudo- grid structure is formed, as shown in Figure 1.
Specifically, first, substrate 1 is provided, with reference to shown in figure 1.
Substrate 1 can be body silicon, the common semiconductor silicon-based substrate such as silicon (SOI) or body Ge, insulator on insulating layer
Upper Ge (GeOI), can also be the compound semiconductor substrates such as SiGe, GaAs, GaN, InSb, InAs, the selection gist of substrate its
On the specific semiconductor devices to be made electric property need and set.In the present invention, the semiconductor device that embodiment is lifted
Part is, for example, field-effect transistor (MOSFET), thus from from the point of view of other process compatibles and cost control, preferably
The material of body silicon or SOI as substrate 1.In addition, substrate 1 can have doping to form well region (not shown), such as PMOS devices
P-well area in part in n-substrate.In the present embodiment, substrate 1 is body silicon substrate.
Then, laying 2 is deposited on substrate 1, with reference to shown in figure 2.
The laying 2 can be nitride, oxide or nitrogen oxides, such as silicon nitride, silica and silicon oxynitride
Deng can deposit to form laying 2 by common process such as LPCVD, PECVD, HDPCVD, RTO, laying 2 for carving later
The stop-layer of erosion, to protect substrate 1, thickness to need and set according to etching technics.In the present embodiment, laying 2 is oxygen
SiClx.
Then, dummy grid 3 is deposited on laying 2, with reference to shown in figure 2.
It deposits to form dummy grid 3 by common process such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputterings,
Material includes polysilicon, non-crystalline silicon, microcrystal silicon, amorphous carbon, amorphous germanium etc. and combinations thereof, is used in rear grid technique so as to control gate
Pole shape.In the present embodiment, dummy grid 3 is polysilicon.
Then, etch patterning laying 2 and dummy grid 3, to form pseudo- grid structure, as shown in Figure 2.
Then, the other structures of the semiconductor devices other than gate structure are further formed, with reference to shown in figure 2-4.
Specifically, first, first time source and drain ion implanting is carried out, using pseudo- grid structure as mask, in dummy gate structure both sides
Substrate 1 in formed be lightly doped, source and drain extension 4L namely the LDD structure of shallow pn-junction, as shown in Figure 2.
Then, it deposits insulative separator material in entire device surface and etches, on the substrate 1 only around dummy gate structure
Form grid curb wall 5.The material of grid curb wall 5 includes nitride, oxide, nitrogen oxides, DLC and combinations thereof, can be selected
The material different from laying 2 and dummy grid 3, in order to selective etch.Particularly, grid curb wall 5 may include multilayer
Structure (not shown), such as the section with vertical component and horizontal component are L-shaped first grid side wall, and positioned at the
Heavily stressed second grid side wall on one grid curb wall horizontal component, the material of second grid side wall may include SiN or eka-gold
Hard rock amorphous carbon (DLC), stress is preferably greater than 2GPa.
Then, it is mask with grid curb wall 5, carries out second of source and drain ion implanting, the substrate in 5 both sides of dummy grid side wall
Formed in 1 heavy doping, deep pn-junction source and drain heavily doped region 4H.Source and drain extension 4L is collectively formed with source and drain heavily doped region 4H
Depending on the source-drain area 4 of MOSFET, doping type and concentration, depth are needed according to MOSFET element electrology characteristic.
Then, it is preferable that with reference to Fig. 3, stress liner 6 can be formed on entire device.By LPCVD, PECVD,
The common process such as HDPCVD, MBE, ALD, magnetron sputtering, Magnetic filter pulsed cathode vacuum arc discharge (FCVA) technology form stress
Lining 6 covers source-drain area, grid curb wall 5 and dummy grid 3.The material of stress liner 6 can be silica, silicon nitride, nitrogen
Silica, DLC and combinations thereof.In the present embodiment, the material of stress liner 6 is silicon nitride, and more preferably has stress,
Absolute value is greater than 1GPa.For PMOS, stress liner 6 can have compression, absolute value to be greater than 3GPa；It is right
For NMOS, stress liner 6 can have tensile stress, absolute value to be greater than 2GPa.The thickness of stress liner 6 is, for example,
10~1000nm.In addition, stress liner 6 can also be the combination of DLC and silicon nitride, or the nitridation doped with other elements
Silicon, such as the other elements such as C, F, S, P are adulterated to improve silicon nitride stress.
Then, it forms interlayer dielectric layer and performs etching exposing dummy grid.Pass through spin coating, spraying, silk-screen printing, CVD
Etc. conventional methods form the ILD 7 of low-k materials, material includes but not limited to organic low-k materials (such as containing aryl or polynary
The organic polymer of ring), inorganic low-k material (such as silica, amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silicon glass
Glass, BSG, PSG, BPSG), porous low k material it is (such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials, porous silica, more
Hole SiOCH, it mixes C silica, mix the porous amorphous carbon of F, porous diamond, porous organic polymer).(wet method is carved using returning
And/or dry etching), the technologies such as CMP planarization ILD 7 and stress liner 6, until exposing dummy grid 3, as shown in Figure 4.
Then, it is formed shown in gate groove 3T, as shown in Figure 5.
For the dummy grid 3 of the Si base material matter such as polysilicon, non-crystalline silicon, microcrystal silicon, TMAH wet etchings may be used, or
Carbon fluorine base gas plasma dry etch removes dummy grid 3, until exposing laying 2.
Then, it is possible to further re-forming boundary layer.Specifically, it such as can be removed by HF wet etching liquid
The laying 2 of silica, and clean, dry 1 surface of substrate exposed, to reduce channel region surface defect.Then, in substrate
Boundary layer 8 is formed on 1 in gate trench 3T, as shown in Figure 6.In the present embodiment, boundary layer 8 is silica, and forming method can
To be the conventional methods such as PECVD, HDPCVD, MBE, ALD, chemical oxidation method can also be, such as smelly containing a certain concentration
20s is impregnated in the deionized water of oxygen so that 1 surface of substrate of silicon material is oxidized to form the boundary layer 8 of silica.Thin layer circle
Face layer is for reducing the interface state density between substrate 1 and the gate insulating layer of the high-g value formed later.
Then, the gate dielectric layer 9, metal barrier 10 and metal gate layers 11 for depositing replacement successively, such as Fig. 7-9 institutes
Show.
Gate dielectric layer 9 can be high K medium material (having high dielectric constant relative to silica), including but unlimited
In nitride (such as SiN, AlN, TiN), metal oxide (predominantly subgroup and lanthanide element oxide, such as Al2O3、
Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3), Perovskite Phase oxide (such as PbZrxTi1-xO3(PZT)、
BaxSr1-xTiO3(BST)).Forming method can be the conventional methods such as CVD, PVD, ALD.Then, using deposition after annealing
(PDA), such as at 450 DEG C anneal 15s, to improve the quality of high K medium material.
The material of the metal barrier 10 is, for example, Ti, Ta, TiN, TaN and combinations thereof, which can stop
The metal (Al etc. in metal gates) on upper layer is diffused into gate dielectric layer 9, and the barrier layer can also be tungsten nitride (WN) in addition
B diffuses into downwards gate dielectric layer 9 during to further prevent being subsequently formed W, and can improve the viscous of ALD W films
Attached property.
In the present embodiment, metal gate layers 11 are that the functional layer of work function is adjusted in metal gates, for NMOS,
Al, TiAl can be selected, Ti, TiN, Ta, TaN can be selected for PMOS.Deposition method is, for example, CVD, PVD, ALD
Deng.In other embodiments, appointing before metal gate layers can also be the metallic filler layers for forming top layer during metal gate stacks
Meaning grid layer.
Then, diffusion impervious layer 12 is formed in metal gate layers 11, as shown in Figure 10.
The diffusion impervious layer 12 can be used for adjusting the work function of grid and be used for potential barrier barrier layer, meanwhile, in follow-up ALD
During technique deposits tungsten layer, it can effectively stop that the ion in its predecessor, such as B diffuse to downwards grid and gate medium
In layer, and increase the process window and reliability of the adhesiveness and the planarization of follow-up tungsten layer of tungsten layer.Diffusion impervious layer can be
Si, WN or TiN etc..
In the present embodiment, using ALD techniques, NH is used to the surface of metal gate layers 11 in advance3It is handled；And
Afterwards, the precursor containing tungsten, such as WF are passed through6, reacted with the surface of metal gate layers, nitrogen formed on the surface of metal gate layers
Change the diffusion impervious layer of tungsten.
In other examples, the diffusion impervious layer of formation thin silicon can also be passed through.It is first in a specific implementation
First, chip can be sent into CVD reaction equations, be heated to 300 DEG C by pre- thermal bimorph, and the heat to improve entire chip promotes molecule
Movement, be conducive to subsequent reaction and deposition.Then, the silicon-containing gas such as silane are passed through, after silicon-containing gas decomposes, deposit forms thin
Silicon layer, the thin silicone layer are monoatomic silicon layer, ion when equally can form tungsten layer to avoid follow-up ALD in predecessor, such as
F is diffused to downwards in grid and gate dielectric layer.
Then, using ALD process fillings tungsten 13, as shown in figure 11.
In the present invention, pass through the alternately first reaction and the second reaction-filling tungsten layer, wherein the reaction of the first reaction
Gas includes siliceous reaction gas, and the reaction gas of the second reaction includes borine.Wherein, siliceous reaction gas can be in ALD
Arbitrary siliceous forerunner's reaction gas of tungsten, such as silane (SiH are used to form in technique4) or silicon ethane (Si2H6) etc..In this reality
It applies in example, silane and silicon fluoride (WF is used in the first reaction6) it is used as reaction gas, use borine (B in the second reaction2H6) and
Tungsten fluoride is as reaction gas, specifically, being surface-treated first using silane gas, then carries out reaction and generates tungsten layer,
It is then passed through borine in the tungsten that the reaction is formed and not comprising boron and is reacted, be further formed tungsten layer, so far complete one
The deposit of the tungsten in a period then repeats the above steps, and alternating is passed through silane and borine, forms silane tungsten and borine tungsten alternating
The tungsten layer of stacking.In this embodiment, the deposition rate of silane tungsten is, for example,/ the period is extremely/ the period, preferably/ week
The deposition rate of phase, borine tungsten is, for example,/ the period is extremely/ the period, preferably/ period, final deposition obtain
The thickness of tungsten layer 13 be, for example,Preferably
Then, it is planarized, to form replacement gate, as shown in figure 12.
The method that CMP may be used is planarized, until exposure interlayer dielectric layer 7, is replaced to be formed in gate groove
For grid.
Then, as needed, the subsequent machining technology of device is completed.Such as form metal silicide layer 14 and source and drain contact
Deng as shown in Figure 13,14.
In the present embodiment, first, etching forms source and drain contact hole 7C in interlayer dielectric layer 7, until exposure source-drain area
4H.Ni, Pt, Co, Ti etc. are deposited in source and drain contact hole 7C and forms thin metal layer, carry out annealing so that thin metal layer and source-drain area
In pasc reaction form metal silicide layer 14, subsequent wet etching removes unreacted thin metal layer, as shown in figure 13.And
Afterwards, the barrier layer 15 of TiN, TaN of 1~7nm thickness are deposited in source and drain contact hole 7C, then using CVD or ALD method deposition gold
Belong to W, Al, Mo, Cu and combinations thereof, form source and drain contact 16, finally carries out CMP or return to carve, until exposure interlayer dielectric layer 7,
To form source and drain contact, as shown in figure 14.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention is made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (8)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that including step：
Gate groove is formed on substrate；
Gate dielectric layer and metal gate layers thereon are formed in gate groove；
Diffusion impervious layer is formed in metal gates layer surface, diffusion impervious layer forming step includes：Chip is sent into CVD reactions
Formula is heated to 300 DEG C to be preheated to chip；It is passed through silane gas, deposit forms thin silicone layer, to obtain diffusion barrier
Layer, thin silicone layer are monoatomic silicon layer；
Using ALD process filling tungsten layers, the specific steps are：By alternately first reaction and the second reaction-filling tungsten layer,
In, the reaction gas of the first reaction includes siliceous reaction gas, and the reaction gas of the second reaction includes borine, and the second reaction is sunk
Product rate is less than the deposition rate of the first reaction.
2. according to the method described in claim 1, it is characterized in that, the silicon-containing gas is silane or silicon ethane.
3. according to the method described in claim 1, it is characterized in that, the step of forming diffusion impervious layer is specially：
It is preheated；
By the way that silicon-containing gas to be carried out to the diffusion impervious layer for being decomposed to form silicon.
4. according to the method described in claim 1, it is characterized in that, further including being formed between gate dielectric layer and metal gate layers
Step：Cap layer is formed, to stop that upper layer metal ion diffuses in gate dielectric layer.
5. according to the method described in claim 4, it is characterized in that, the cap layer is Ti, Ta, TaN, TiN, WN and its group
It closes.
6. according to the method described in claim 1, it is characterized in that, the temperature range in ALD techniques is 250-350 °.
7. according to the method described in claim 1, it is characterized in that, the deposition rate of the first reaction is
8. according to the method described in claim 1, it is characterized in that, the deposition rate of the second reaction is
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| CN117238848B (en) * | 2023-11-15 | 2024-02-02 | 合肥晶合集成电路股份有限公司 | Contact hole structure and forming method thereof |
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| CN101211987A (en) * | 2006-12-29 | 2008-07-02 | 海力士半导体有限公司 | Non-volatile memory device having charge trapping layer and method for fabricating the same |
| CN102969347A (en) * | 2011-09-01 | 2013-03-13 | 台湾积体电路制造股份有限公司 | Techniques providing metal gate devices with multiple barrier layers |
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| US8564072B2 (en) * | 2010-04-02 | 2013-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a blocking structure and method of manufacturing the same |
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| CN101211987A (en) * | 2006-12-29 | 2008-07-02 | 海力士半导体有限公司 | Non-volatile memory device having charge trapping layer and method for fabricating the same |
| CN102969347A (en) * | 2011-09-01 | 2013-03-13 | 台湾积体电路制造股份有限公司 | Techniques providing metal gate devices with multiple barrier layers |
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