CN103618523A - Two-channel checking circuit and method based on discrete magnitude signal - Google Patents
Two-channel checking circuit and method based on discrete magnitude signal Download PDFInfo
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- CN103618523A CN103618523A CN201310625221.3A CN201310625221A CN103618523A CN 103618523 A CN103618523 A CN 103618523A CN 201310625221 A CN201310625221 A CN 201310625221A CN 103618523 A CN103618523 A CN 103618523A
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Abstract
The invention relates to a two-channel checking circuit and method based on a discrete magnitude signal. The two-channel checking circuit comprises a first channel, a second channel, a corresponding position comparing unit and a redundant register, wherein the first channel and the second channel are parallel. The first channel comprises a first discrete magnitude processing circuit and a second data register, wherein the first discrete magnitude processing circuit and the second data register are sequentially connected. The second channel comprises a second discrete magnitude processing circuit and a second data register, wherein the second discrete magnitude processing circuit and the second data register are sequentially connected. The discrete magnitude signal simultaneously enter the first discrete magnitude processing circuit and the second discrete magnitude processing circuit, the output end of the first data register and the output end of the second data register are both connected with the input end of the corresponding position comparing unit, and the output end of the corresponding position comparing unit is connected with the redundant register. The technical problems that an existing discrete magnitude signal processing method cannot really reflect the state of a signal and credibility of a data output result is not high are solved, and the aim of improving signal credibility through two-channel processing of the discrete magnitude signal is achieved.
Description
Technical field
The invention belongs to method of calibration, relate in particular to a kind of binary channels method of calibration based on discrete magnitude signal.
Background technology
In the various systems of discrete magnitude signal ubiquity, for a circuit of processing discrete magnitude signal, conventionally use single path, discrete magnitude signal directly stores to data register after being treated to Transistor-Transistor Logic level, by the mode of access register address, can realize data output.In above process, if there is the situations such as passage infringement, cause erroneous results, data register result can not reflect real signal input state, data Output rusults confidence level is not high.
Summary of the invention
In order to solve existing discrete magnitude signal processing method, there is truly reflected signal state, the not high technical problem of data Output rusults confidence level, the invention provides a kind of binary channels checking circuit and method based on discrete magnitude signal, the present invention is processed and is reached the object that strengthens signal confidence level by the binary channels of discrete magnitude signal.
Technical solution of the present invention is:
A kind of binary channels checking circuit based on discrete magnitude signal, its special character is: comprise two parallel first passages and second channel, corresponding bit comparison unit and redundancy register, described first passage comprises the first discrete magnitude treatment circuit and the first data register connecting successively, described second channel comprises the second discrete magnitude treatment circuit and the second data register connecting successively
Discrete magnitude signal enters first, second discrete magnitude treatment circuit simultaneously, and the output of described first, second data register all connects with the input of corresponding bit comparison unit, and the output of described corresponding bit comparison unit is connected with redundancy register.
Above-mentioned the first data register and the second data register to deposit address corresponding one by one.
A binary channels method of calibration based on discrete magnitude signal, its special character is: comprise the following steps:
Step 1n road discrete magnitude signal enters first, second discrete magnitude treatment circuit of first, second passage simultaneously, by first, second discrete magnitude, respectively n road discrete magnitude signal is processed, n road discrete magnitude signal is treated as to Transistor-Transistor Logic level signal, result is stored in respectively in first, second data register simultaneously;
Step 2 redundancy ratio is: corresponding bit comparison unit compares the Transistor-Transistor Logic level signal of storing in first, second data register according to the principle comparing by turn;
The n position of step 3 the first data register is identical with the n bit level signal of the second data register, by Transistor-Transistor Logic level signal storage to redundancy register; If result is different, send " fault " signal.
Advantage that the present invention has is:
Binary channels method of calibration based on discrete magnitude signal provided by the invention, is used binary channels to process same signal, by signal, compares by turn, gets rid of the mistake causing due to passage, strengthens signal reliability.
Accompanying drawing explanation
Fig. 1 is the circuit diagram that the present invention is based on the binary channels checking circuit of discrete magnitude signal.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is explained clearly and completely.
As shown in Figure 1, a kind of binary channels checking circuit based on discrete magnitude signal, comprise two parallel first passages and second channel, corresponding bit comparison unit and redundancy register, first passage comprises the first discrete magnitude treatment circuit and the first data register connecting successively, second channel comprises the second discrete magnitude treatment circuit and the second data register connecting successively
N road discrete magnitude signal enters first, second discrete magnitude treatment circuit simultaneously, and the output of first, second data register all connects with the input of corresponding bit comparison unit, and the output of corresponding bit comparison unit is connected with redundancy register.The first data register and the second data register to deposit address corresponding one by one.The invention provides a kind of binary channels method of calibration based on discrete magnitude signal, the method comprises the following steps:
Step 1n road discrete magnitude signal is processed, the first discrete magnitude processing unit of first passage and the second discrete magnitude processing unit of second channel are processed n road discrete magnitude signal respectively, discrete magnitude signal is treated as to Transistor-Transistor Logic level signal, Transistor-Transistor Logic level signal is stored in respectively to the first data register and the second data register simultaneously, it should be noted that the 0th of the 0th correspondence the second data register of the first data register, first corresponding the second data register n position, data register 1 n position;
, corresponding bit comparison unit carries out discrete magnitude result respectively for first passage and second channel respectively step 2 redundancy ratio, and manner of comparison is for comparing by turn.
Step 3, according to the result of step 2, if the first data register n position and the second data register n position come to the same thing, is deposited result to redundancy register; If result is different, send " fault " signal.
The discrete magnitude of the present embodiment is processed for changing discrete magnitude signal into Transistor-Transistor Logic level, data register is used for storing data, corresponding bit comparison unit is for the result of data register is compared by turn, redundancy register for by binary channels the correct data after relatively store to redundancy register.
The principle of the invention and the course of work are: n road discrete magnitude signal is processed through first passage and second channel simultaneously, and the discrete magnitude signal that first passage is connected with second channel need align one by one, realize thus the redundancy of discrete magnitude signal and process.
Be specially, the Transistor-Transistor Logic level that discrete magnitude treatment circuit produces stores respectively to the first data register and the second data register, and alignment by turn.By more corresponding bit location, the reliability of data is judged, coordination data coordination " 1 " or be all " 0 " and represent that signal reliability is high for example, redundant channel coordination comparative result is identical, and this result storage is to redundancy register; If the coordination result of the first data register and the second data register is different, represent that signal reliability is not high, redundant channel coordination comparative result is different, passage is processed and is had mistake, output " fault " signal, sends alarm to system, indicates redundant channel and makes a mistake.
Binary channels method of calibration based on discrete magnitude signal provided by the invention, is used binary channels to process same signal, by the signal reliability of comparison criterion data by turn, gets rid of the mistake causing due to passage, and then has strengthened the reliability of signal.
Claims (3)
1. the binary channels checking circuit based on discrete magnitude signal, it is characterized in that: comprise two parallel first passages and second channel, corresponding bit comparison unit and redundancy register, described first passage comprises the first discrete magnitude treatment circuit and the first data register connecting successively, described second channel comprises the second discrete magnitude treatment circuit and the second data register connecting successively
Discrete magnitude signal enters first, second discrete magnitude treatment circuit simultaneously, and the output of described first, second data register all connects with the input of corresponding bit comparison unit, and the output of described corresponding bit comparison unit is connected with redundancy register.
2. the binary channels checking circuit based on discrete magnitude signal according to claim 1, is characterized in that: described the first data register and the second data register to deposit address corresponding one by one.
3. the binary channels method of calibration based on discrete magnitude signal, is characterized in that: comprise the following steps:
Step 1n road discrete magnitude signal enters first, second discrete magnitude treatment circuit of first, second passage simultaneously, by first, second discrete magnitude, respectively n road discrete magnitude signal is processed, n road discrete magnitude signal is treated as to Transistor-Transistor Logic level signal, result is stored in respectively in first, second data register simultaneously;
Step 2 redundancy ratio is: corresponding bit comparison unit compares the Transistor-Transistor Logic level signal of storing in first, second data register according to the principle comparing by turn;
The n position of step 3 the first data register is identical with the n bit level signal of the second data register, by Transistor-Transistor Logic level signal storage to redundancy register; If result is different, send " fault " signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310625221.3A CN103618523A (en) | 2013-11-27 | 2013-11-27 | Two-channel checking circuit and method based on discrete magnitude signal |
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| CN201310625221.3A CN103618523A (en) | 2013-11-27 | 2013-11-27 | Two-channel checking circuit and method based on discrete magnitude signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109144937A (en) * | 2018-10-30 | 2019-01-04 | 天津津航计算技术研究所 | A kind of multi-channel serial port high reliability transport method |
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| US4255809A (en) * | 1979-11-02 | 1981-03-10 | Hillman Dale A | Dual redundant error detection system for counters |
| US5490155A (en) * | 1992-10-02 | 1996-02-06 | Compaq Computer Corp. | Error correction system for n bits using error correcting code designed for fewer than n bits |
| CN1158484A (en) * | 1995-12-20 | 1997-09-03 | 国际商业机器公司 | Programmable parity checking and comparison circuit |
| CN1229999A (en) * | 1998-03-19 | 1999-09-29 | 日本电气株式会社 | Semiconductor memory device, and method of checking the semiconductor device and method of using the same |
| CN1507609A (en) * | 2001-05-10 | 2004-06-23 | 1 | Method for protecting a computer from the manipulation of register contents and a corresponding computer for carrying out this method |
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- 2013-11-27 CN CN201310625221.3A patent/CN103618523A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4183463A (en) * | 1978-07-31 | 1980-01-15 | Sperry Rand Corporation | RAM error correction using two dimensional parity checking |
| US4255809A (en) * | 1979-11-02 | 1981-03-10 | Hillman Dale A | Dual redundant error detection system for counters |
| US5490155A (en) * | 1992-10-02 | 1996-02-06 | Compaq Computer Corp. | Error correction system for n bits using error correcting code designed for fewer than n bits |
| CN1158484A (en) * | 1995-12-20 | 1997-09-03 | 国际商业机器公司 | Programmable parity checking and comparison circuit |
| CN1229999A (en) * | 1998-03-19 | 1999-09-29 | 日本电气株式会社 | Semiconductor memory device, and method of checking the semiconductor device and method of using the same |
| CN1507609A (en) * | 2001-05-10 | 2004-06-23 | 1 | Method for protecting a computer from the manipulation of register contents and a corresponding computer for carrying out this method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109144937A (en) * | 2018-10-30 | 2019-01-04 | 天津津航计算技术研究所 | A kind of multi-channel serial port high reliability transport method |
| CN109144937B (en) * | 2018-10-30 | 2021-08-17 | 天津津航计算技术研究所 | High-reliability transmission method for multi-path serial port |
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Application publication date: 20140305 |