CN103617949A - Method of using nitrogen trifluoride to inhibit interface layer growth between high dielectric constant gate medium layer and silicon substrate - Google Patents
Method of using nitrogen trifluoride to inhibit interface layer growth between high dielectric constant gate medium layer and silicon substrate Download PDFInfo
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- CN103617949A CN103617949A CN201310416064.5A CN201310416064A CN103617949A CN 103617949 A CN103617949 A CN 103617949A CN 201310416064 A CN201310416064 A CN 201310416064A CN 103617949 A CN103617949 A CN 103617949A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 57
- 239000010703 silicon Substances 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 37
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 title claims description 27
- 239000007789 gas Substances 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 230000005527 interface trap Effects 0.000 abstract description 3
- 125000004433 nitrogen atom Chemical group N* 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 10
- 239000012528 membrane Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- IJJMASPNDCLGHG-UHFFFAOYSA-N CC[Hf](CC)(CC)(CC)NC Chemical compound CC[Hf](CC)(CC)(CC)NC IJJMASPNDCLGHG-UHFFFAOYSA-N 0.000 description 1
- 108091006146 Channels Proteins 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention belongs to the field of the semiconductor integrated circuit technology, and in particular relates to a method of using NF3 to inhibit interface layer growth between a high k gate medium layer and a silicon substrate. According to the invention, before deposition of high k gate medium layer, the silicon substrate is pretreated with use of the NF3 plasma to effectively prevent diffusion of oxygen in the silicon substrate, so that the interface layer growth between the high k gate medium layer and the silicon substrate is inhibited; and the equivalent oxide layer thickness of the high k gate medium layer is reduced, so that the breakdown and other characteristics of a device are improved. In addition, the nitrogen atom has a good passivation effect on a defect of the high k gate medium layer and on an interface trap of the high k gate medium layer and the silicon substrate, so that the electrical characteristic and other characteristics of the device are also improved.
Description
Technical field
The invention belongs to semiconductor integrated circuit technique technical field, be specifically related to a kind of method that suppresses boundary layer growth between high-dielectric-coefficient grid medium layer and silicon substrate.
Background technology
Along with constantly dwindling of MOS (Metal-oxide-semicondutor, MOS is the abbreviation of Metal-Oxide-Semiconductor) device feature size, silicon dioxide (SiO
2) gate dielectric layer also thins down according to the principle of scaled down, works as SiO
2after gate dielectric layer is thinned to a certain degree, its integrity problem, especially with time correlation puncture and gate electrode in impurity to the problems such as diffusion of substrate, will have a strong impact on stability and the reliability of device.Now, in MOS integrated circuit technology, extensively adopt high-k gate dielectric layer to replace SiO
2gate dielectric layer, to increase capacitance density and to reduce gate leakage current.High k material is because having large dielectric constant values, can realize with SiO
2there is in the situation of same equivalent gate oxide thickness (Equivalent Oxide Thichness, EOT) its actual Thickness Ratio SiO
2large is many, thereby has solved SiO
2the problem producing because approaching the physical thickness limit.
Yet replace SiO with high k material
2as the gate dielectric layer of MOS device, having more than is simple substitution problem.With high k material substitution SiO
2during as gate dielectric layer, all high k material film growth techniques all can be introduced the boundary layer between high k material layer and silicon substrate in the annealing process during film growth or after deposit substantially.The appearance of boundary layer is owing to there being unnecessary oxygen in thin film growth process, and first these oxygen are oxidized the surface of silicon substrate through high k material layer, and then silicon diffuses into high k film and forms silicate layer.Therefore some silicate layer is unsettled in the deposit after annealing of high temperature, PHASE SEPARATION occurs and has produced boundary layer.For the film with sputtering method deposit, this phenomenon is especially obvious, because can produce many active groups in thin film deposition process, these groups will react with silicon substrate, generate very thick boundary layer.The existence of the boundary layer between high-k gate dielectric layer and silicon substrate has hindered further reducing of equivalent oxide thickness.
Summary of the invention
The object of the invention is to propose a kind of method that suppresses boundary layer growth between high-k gate dielectric layer and silicon substrate, to reduce the performance of equivalent oxide thickness, raising device.
The present invention proposes to suppress the method for boundary layer growth between high-k (high k) gate dielectric layer and silicon substrate, utilizes Nitrogen trifluoride (NF
3), concrete steps are:
Clean silicon substrate and silicon substrate is dried to processing;
With Nitrogen trifluoride plasma, dried surface of silicon is processed;
At the surface of silicon growth one deck high-dielectric-coefficient grid medium layer after Nitrogen trifluoride plasma treatment.
The NF that utilizes as above
3the method that suppresses boundary layer growth between high-dielectric-coefficient grid medium layer and silicon substrate, described processes surface of silicon with Nitrogen trifluoride plasma, specifically silicon substrate is put into consersion unit, then in consersion unit, pass into gas of nitrogen trifluoride, and by the method generation Nitrogen trifluoride plasma of direct-current discharge or alternating current discharge, surface of silicon is processed.Consersion unit is such as being plasma enhanced chemical vapor deposition (PECVD) equipment, magnetron sputtering apparatus, plasma etching equipment etc.
The NF that utilizes as above
3the method that suppresses boundary layer growth between high-dielectric-coefficient grid medium layer and silicon substrate, the described time of surface of silicon being processed with Nitrogen trifluoride plasma is 1-30 minute.
The present invention first uses NF before deposit high-k gate dielectric layer
3plasma carries out preliminary treatment to silicon substrate, can effectively prevent the diffusion of oxygen in silicon substrate, thereby suppressed the growth of boundary layer between high-k gate dielectric layer and silicon substrate, reduced the equivalent oxide thickness of high-k gate dielectric layer, the performances such as breakdown characteristics of device are improved.In addition, nitrogen-atoms also has good passivation to the interface trap of the defect in high-k gate dielectric layer and high-k gate dielectric layer and silicon substrate, and this is also improved the performance of the aspects such as electrical characteristics of device.
Accompanying drawing explanation
Fig. 1 is the proposed by the invention schematic diagram that utilizes Nitrogen trifluoride plasma to process surface of silicon.
Fig. 2-Fig. 9 is that the use Nitrogen trifluoride plasma that the present invention proposes is processed the process chart of an embodiment of the capable channel MOS transistor of rear preparation p to surface of silicon.
Embodiment
The present invention is further detailed explanation with embodiment by reference to the accompanying drawings for face.Fig. 1 is the proposed by the invention schematic diagram that utilizes Nitrogen trifluoride plasma to process surface of silicon.To cleaning and be dried the surface of the silicon substrate 200 after processing, use Nitrogen trifluoride plasma dignity to process 1-30 minute, because the group of fluorine-containing (F) is unsettled, be easy to and water (H
20) react and generate hydrogen-oxygen key (OH
-) and hydrogen fluoride (HF), and OH
-not only can corrode the boundary layer generating with HF, and can effectively prevent O
2diffusion in silicon substrate reacts with it, thereby has suppressed the growth of boundary layer, has reduced the equivalent oxide thickness of high-k gate dielectric layer, and the performance of device is improved.In addition, OH
-can also increase the dielectric constant of deielectric-coating, this also makes the performance of device be improved.Meanwhile, nitrogen-atoms also has good passivation to the interface trap of the defect in high-k gate dielectric layer and high-k gate dielectric layer and silicon substrate, and this is also improved the performance of the aspects such as electrical characteristics of device.
The proposed by the invention NF that first utilizes before deposit high-k gate dielectric layer
3the method that plasma processes to suppress boundary layer growth between high-k gate dielectric layer and silicon substrate to surface of silicon can be applied in the preparation of high-k gate dielectric layer of MOS device of different structure, in the preparation of the high-k gate dielectric layer of the devices such as MOS transistor, tunneling transistor.Following narrated be to utilize Nitrogen trifluoride plasma to process rear regrowth high-k gate dielectric layer with the technological process of an embodiment of the MOS transistor of preparation p-type raceway groove to surface of silicon.
Fig. 2 to Fig. 9 has described a part of operation of preparation p-type channel MOS transistor, in the drawings, for convenience of description, has zoomed in or out the thickness in layer and region, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, they or complete reflection region and form the mutual alignment between structure, particularly form the upper and lower and neighbouring relations between structure.
First, with the known standard RCA(of the industry Radio Corporation of America) cleaning cleans the silicon substrate with N-shaped doping type providing, then with high pure nitrogen, silicon substrate dried up or in baking oven, silicon substrate dried.Then the silicon substrate after dry processing is put into consersion unit, and pass into gas of nitrogen trifluoride in consersion unit, then utilize the method generation Nitrogen trifluoride plasma of direct-current discharge or alternating current discharge surface of silicon to be carried out to the processing of 5 minutes.Consersion unit can be plasma enhanced chemical vapor deposition (PECVD) equipment, magnetron sputtering apparatus, plasma etching equipment etc.
Next, as shown in Figure 2, at the superficial growth one floor height k material layer 201 of the silicon substrate 200 after Nitrogen trifluoride plasma treatment.
High k material layer 201, such as being aluminium oxide or being hafnium oxide, can be also other high k material layer, and its growth technique is all that industry is known.To adopt the method growth hafnium oxide (HfO of atomic layer deposition
2) gate dielectric layer is example: the silicon substrate after Nitrogen trifluoride plasma treatment is put into atomic layer deposition apparatus, adopt tetraethyl methylamino hafnium (TEMAH) and water respectively as source metal and oxygen source, before reacting, first reaction chamber is heated to 300 ℃, presoma TEMAH is heated to 70 ℃, and keeps temperature-resistant in whole growth course.Reaction is carried out 100 cycles and can be obtained the HfO of about 8 nanometer thickness
2gate dielectric layer.
Next, adopt the technique of low-pressure chemical vapor deposition (LPCVD) at HfO
2on gate dielectric layer 202, deposit obtains the polysilicon membrane 202 that a layer thickness is about 0.5 micron, and polysilicon membrane 202 is used as sacrifice layer.Then on polysilicon membrane 202, spin coating one deck photoresist 301 mask, exposure, development define the position in device source region and drain region; and etch away the polysilicon membrane 202 do not protected by photoresist to expose the position in described source region and drain region, as shown in Figure 3.
Divest after photoresist 301, adopt the method for PECVD, with silane (SiH
4) and laughing gas (N
2o) be reacting gas, cover formed device deposit growth a layer thickness and be about the SiO of 0.5 micron
2cover layer, the way etching SiO of recycling anisotropic etching
2cover layer exposes the position in source region and drain region, only leaves one deck SiO on polysilicon membrane 202 sides
2as abutment wall 203, structure as shown in Figure 4.
Next, by primary ions injection technology, carry out boron Implantation, in the both sides of the interior polysilicon membrane 202 of silicon substrate 200, form respectively the 204He drain region, source region 205 of MOS transistor, as shown in Figure 5.
Next, continue to adopt the method for PECVD to cover the thicker SiO of formed device deposit growth one deck
2layer 206, thickness is advisable to be greater than 0.5 micron.Then utilize chemico-mechanical polishing (CMP) technology by the thick SiO of glue of growth
2layer 206 is thrown flat to expose polysilicon membrane 202, as shown in Figure 6.
Next, the polysilicon membrane as sacrifice layer 202 is etched away, and device is annealed 1 minute in the nitrogen atmosphere of 700 ℃, the structure obtaining as shown in Figure 7.
Next, adopt the method for physical vapor deposition (PVD) to cover the polysilicon membrane of formed device deposit growth one deck doping, and it is flat to form grid conducting layer 207, as shown in Figure 8 to utilize CMP technology that the polysilicon membrane of growth is thrown.
Finally, use the SiO of the method deposit thick layer of PECVD
2film 208 is as passivation layer, then at SiO
2on film 208, spin coating photoresist lithographic definition go out the position in device contacts hole, and etch away the SiO exposing
2film 208 is to form contact hole.Divest after photoresist, the formed metal level of deposit one metal level etching forms source electrode 209, gate electrode 210 and drain electrode 211, as shown in Figure 9.The material of source electrode 209, gate electrode 210 and drain electrode 211 is such as being the metals such as silver, platinum, aluminium, gold, titanium, palladium or being the alloy between them, and its manufacture craft can adopt a kind of in the kinds of processes such as vacuum evaporation, magnetron sputtering, electron beam evaporation.
As mentioned above, in the situation that not departing from spirit and scope of the invention, can also form many embodiment that have very big difference.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in specification.
Claims (3)
1. utilize Nitrogen trifluoride to suppress a method for boundary layer growth between high-dielectric-coefficient grid medium layer and silicon substrate, it is characterized in that concrete steps are:
Clean silicon substrate and silicon substrate is dried to processing;
With Nitrogen trifluoride plasma, dried surface of silicon is processed;
At the surface of silicon growth one deck high-dielectric-coefficient grid medium layer after Nitrogen trifluoride plasma treatment.
2. the Nitrogen trifluoride that utilizes as claimed in claim 1 suppresses the method that between high-dielectric-coefficient grid medium layer and silicon substrate, boundary layer is grown, it is characterized in that, described processes surface of silicon with Nitrogen trifluoride plasma, that silicon substrate is put into consersion unit, then in consersion unit, pass into gas of nitrogen trifluoride, and by the method generation Nitrogen trifluoride plasma of direct-current discharge or alternating current discharge, surface of silicon is processed.
3. the method for utilizing Nitrogen trifluoride to suppress boundary layer growth between high-dielectric-coefficient grid medium layer and silicon substrate as claimed in claim 1 or 2, is characterized in that, the described time of surface of silicon being processed with Nitrogen trifluoride plasma is 1-30 minute.
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|---|---|---|---|
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769043A (en) * | 2019-04-02 | 2020-10-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of gate dielectric layer, semiconductor structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200903642A (en) * | 2007-07-09 | 2009-01-16 | Nanya Technology Corp | Method of fabricating a semiconductor device |
| CN101958341A (en) * | 2009-07-15 | 2011-01-26 | 台湾积体电路制造股份有限公司 | Dwindle EOT by removing boundary layer from the high K/ metal gates of MOS device |
| CN102306625A (en) * | 2011-09-05 | 2012-01-04 | 北京大学 | Germanium-based MOS device substrate surface passivation method |
| CN102891084A (en) * | 2011-07-19 | 2013-01-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing P-channel metal oxide semiconductor (PMOS) transistor |
| CN103151302A (en) * | 2013-02-26 | 2013-06-12 | 复旦大学 | Method for preparing low-resistance tantalum and tantalum nitride double-layer barrier layer by utilizing nitrogen-containing plasma |
-
2013
- 2013-09-13 CN CN201310416064.5A patent/CN103617949A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200903642A (en) * | 2007-07-09 | 2009-01-16 | Nanya Technology Corp | Method of fabricating a semiconductor device |
| CN101958341A (en) * | 2009-07-15 | 2011-01-26 | 台湾积体电路制造股份有限公司 | Dwindle EOT by removing boundary layer from the high K/ metal gates of MOS device |
| CN102891084A (en) * | 2011-07-19 | 2013-01-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing P-channel metal oxide semiconductor (PMOS) transistor |
| CN102306625A (en) * | 2011-09-05 | 2012-01-04 | 北京大学 | Germanium-based MOS device substrate surface passivation method |
| CN103151302A (en) * | 2013-02-26 | 2013-06-12 | 复旦大学 | Method for preparing low-resistance tantalum and tantalum nitride double-layer barrier layer by utilizing nitrogen-containing plasma |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769043A (en) * | 2019-04-02 | 2020-10-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of gate dielectric layer, semiconductor structure and forming method thereof |
| CN111769043B (en) * | 2019-04-02 | 2023-02-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of gate dielectric layer, semiconductor structure and forming method thereof |
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