CN103605028B - A kind of PWM test macro based on monocycle multi-point sampling - Google Patents

Abstract

The present invention provides a PWM test system based on single-cycle multi-point sampling. The system includes a PWM converter valve control board module, a communication management board module and a wave recording device; the PWM converter valve control board module communicates The management board module communicates with the wave recording device. The present invention provides a PWM test system based on single-cycle multi-point sampling, which samples PWM waveforms at multiple points within a single sampling cycle, increasing the actual sampling frequency of PWM signals several times; it can be flexibly configured, and can be set according to requirements. Sampling at 16 points, 32 points, and 48 points in a single cycle to further increase the sampling frequency and make the test recording waveform more accurate, and can be used for static synchronous var generator SVG, static synchronous var compensation device STATCOM, and unified power flow control In the valve control device of UPFC and HVDC transmission device.

Description

A PWM test system based on single-period multi-point sampling

technical field

The invention relates to a test system, in particular to a PWM test system based on single-period multi-point sampling.

Background technique

At present, power electronic PWM converters are widely used in the field of power system power quality control, such as active power filters APF, SVG, STATCOM, etc. The overall structure of the corresponding controller of the converter generally adopts the composition form of control protection (responsible for regulating control and protection), valve control (power module trigger detection), and unit controller (power module interface).

In order to monitor the working status of the converter device in real time, the upper computer of the device generally has functions such as telemetry, remote signaling, and wave recording. Among them, the wave recording function can store the analog quantity and switch signal of the device in the host computer for a period of time before and after the start of wave recording when the device is in a steady state or in a transient state of device failure. The signal sampling frequency of the converter generally chooses 128 points (sampling frequency 6.4kHz, sampling period 156us) or 256 points ((sampling frequency 12.8kHz, sampling period 78us) per power frequency cycle.

For analog quantities such as current and voltage, due to the change of power frequency, a relatively complete recording waveform can be obtained when the sampling period is 156us or 78us. However, for the test of the PWM waveform output in the PWM converter, since the switching frequency ranges from several hundred Hz to several KHz, and the minimum pulse width is tens of us, if the sampling period is 156us or 78us, it is impossible to obtain an accurate PWM recording waveform .

At present, in the upper computer of PWM converter and the dedicated power system fault recording device, there are only recording channels for analog quantities, binary input and output quantities, and there is no special recording function for PWM waveforms. Power system RTDS (Real-Time Digital Simulator, real-time digital simulation system) device users can use RTDS to sample the PWM output of the unit controller in small steps to obtain PWM wave recording signals, but RTDS devices are expensive and complicated to use.

Contents of the invention

In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a PWM test system based on single-cycle multi-point sampling, which is used for static synchronous var generator SVG, STATCOM STATCOM, unified power flow controller UPFC, high voltage In the valve control device of the direct current transmission device.

In order to realize the above-mentioned purpose of the invention, the present invention takes the following technical solutions:

The present invention provides a PWM test system based on single-cycle multi-point sampling. The system includes a PWM converter valve control board module, a communication management board module and a wave recording device; the PWM converter valve control board module communicates The management board module communicates with the wave recording device.

The PWM converter valve control board module includes an FPGA module and a DSP module; the FPGA module compares the modulation wave and the carrier wave in real time according to the sinusoidal pulse width modulation method, generates a PWM waveform, and communicates with the DSP module.

In a single sampling period, the FPGA module uses a high-frequency clock to sample PWM high and low signals at equal time intervals, and stores the PWM high and low changes in the form of 1 and 0 in the same wave recording signal quantity; the FPGA module records the wave recording The semaphore is sent to the DSP module, and when the sampling synchronization signal is valid, an interrupt signal is generated to the DSP module.

Set N sampling points for sampling in a single sampling period, and N is 16, 32 or 48.

The DSP module interrupts the received interrupt signal, controls the address bus and data bus and related read and write enable signals, the DSP module simultaneously receives the wave recording semaphore, and starts the backplane communication, controls the backplane communication sequence, The board bus sends the wave recording semaphore to the communication management board module.

The communication management board module includes a SRAM memory and a NANDFLASH memory; the SRAM memory is used to store the pre-recorded signal amount received by the communication management board module, and the NANDFLASH memory is used to store the recorded wave signal amount after starting the wave recording .

The communication management board module transmits the stored wave recording signal quantity to the wave recording device according to the wave recording protocol.

The wave recording device analyzes the PWM high and low signals in a single sampling period and completes the wave recording and tracing points of a single sampling period at equal time intervals in chronological order.

Compared with prior art, the beneficial effect of the present invention is:

1) It can be used in valve control devices of static synchronous var generator SVG, static synchronous var compensation device STATCOM, unified power flow controller UPFC, and HVDC transmission device;

2) The present invention samples the PWM waveform at multiple points within a single sampling period, increasing the actual sampling frequency of the PWM signal several times;

3) The cost of PWM testing is low, simple and reliable, without complex and expensive RTDS devices;

4) It can be flexibly configured, and can be set to single-cycle 16-point, 32-point, 48-point sampling according to requirements, so as to further increase the sampling frequency and make the test recording waveform more accurate.

Description of drawings

Figure 1 is a block diagram of a PWM test system based on single-cycle multi-point sampling;

Fig. 2 is a PWM test process diagram of single-cycle multi-point sampling.

detailed description

The present invention will be described in further detail below in conjunction with the accompanying drawings.

The present invention provides a PWM test system based on single-cycle multi-point sampling. The system includes a PWM converter valve control board module, a communication management board module and a wave recording device; the PWM converter valve control board module communicates The management board module communicates with the wave recording device.

The PWM converter valve control board module includes an FPGA module and a DSP module; the FPGA module compares the modulation wave and the carrier wave in real time according to the sinusoidal pulse width modulation method, generates a PWM waveform, and communicates with the DSP module.

In a single sampling period, the FPGA module uses a high-frequency clock to sample PWM high and low signals at equal time intervals, and stores the PWM high and low changes in the form of 1 and 0 in the same wave recording signal quantity; the FPGA module records the wave recording The semaphore is sent to the DSP module, and when the sampling synchronization signal is valid, an interrupt signal is generated to the DSP module.

Set N sampling points for sampling in a single sampling period, and N is 16, 32 or 48.

The DSP module interrupts the received interrupt signal, controls the address bus and data bus and related read and write enable signals, the DSP module simultaneously receives the wave recording semaphore, and starts the backplane communication, controls the backplane communication sequence, The board bus sends the wave recording semaphore to the communication management board module.

The communication management board module includes a SRAM memory and a NANDFLASH memory; the SRAM memory is used to store the pre-recorded signal amount received by the communication management board module, and the NANDFLASH memory is used to store the recorded wave signal amount after starting the wave recording .

The communication management board module transmits the stored wave recording signal quantity to the wave recording device according to the wave recording protocol.

The wave recording device analyzes the PWM high and low signals in a single sampling period and completes the wave recording and tracing points of a single sampling period at equal time intervals in chronological order.

Example

Taking PWM sampling with a sampling period of 156us and 16 points per period as an example, the embodiments of the present invention will be described in detail below.

As shown in Figure 1, the present invention provides a PWM test system based on single-cycle multi-point sampling, including a PWM converter valve control board module, a communication management board module and a wave recording device; the PWM converter valve control board module passes The communication management board module communicates with the wave recording device.

The PWM converter valve control board module includes an FPGA module and a DSP module; the FPGA module compares the modulation wave and the carrier wave in real time according to the sinusoidal pulse width modulation method, generates a PWM waveform, and communicates with the DSP module.

The FPGA module adopts XC3S5000 chip; the DSP module adopts TMS320F28335 chip.

Assume that the communication time interval between the FPGA module and the DSP module dual-port RAM is 156us, and the interrupt signal of the dual-port RAM is generated by the FPGA module, and the period is also 156us. The FPGA module uses a 20MHz clock for sampling and counting, and the PWM pulse width is 32us. For the above situation, as shown in Figure 2, the test system implements the single-cycle multi-point sampling PWM test according to the following process:

1) The sampling synchronization signal uses the dual-port RAM interrupt signal. After the 20MHz clock detects that the signal is pulled high, the FPGA module starts to sample the PWM output;

2) The 20MHz clock performs a PWM output sampling every 9.75us, and sequentially stores the sampling value from low to high into a 16-bit PWM sampling semaphore, that is: 0us sampling value is stored in semaphore bit0, and 9.75us sampling value is stored in Enter bit1, 9.75*2us sampling value is stored in bit2, and analogously, 9.75*nus sampling value is stored in bit(n), when the sampling time reaches 9.75*15=146.25us, the PWM output sampling value is stored in semaphore bit15;

3) When the next sampling synchronization signal is valid, the FPGA module sends the PWM semaphore of the previous cycle to the DSP module, and the communication management board module receives the PWM semaphore sent by the valve control board through the backplane McBSP bus and sends it to the wave recording device recording wave;

4) After the wave recording device obtains the wave recording data of the wave recording PWM signal, within 156us, in the order from low to high, at equal time intervals (9.75us), the value of the corresponding bit is sequentially taken to draw 0 or 1 point.

So far, the single-period (156us) multi-point (16 points) sampling PWM test has been realized. By viewing the recorded waveform in the wave recording device, relevant personnel can judge whether the PWM output by the FPGA is normal.

Due to the fact that there is an objective time difference between the sampling synchronous signal and PWM high and low changes and discrete sampling, there will be errors between the high and low continuous width of the final sampling value and the actual width of the PWM, and the single-cycle 16-point sampling error range: ±7.95us. In this example, due to discrete sampling, the error is 4*7.95us-32us=﹢7us, that is, the PWM width obtained by sampling is 39us. The error can be further reduced by increasing the number of sampling points in a single cycle (such as 32 points, 48 points, etc.).

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the scope of the claims of the present invention.

Claims (6)

1. the PWM test macro based on monocycle multi-point sampling, is characterized in that: described system comprises PWM unsteady flowDevice valve control plate module, telecommunication management plate module and wave recording device; Described PWM current transformer valve control plate module is by telecommunication management plateModule is communicated by letter with wave recording device;

Described PWM current transformer valve control plate module comprises FPGA module and DSP module; Described FPGA module is according to positive taut pulseWide modulator approach, compares modulating wave and carrier wave size in real time, generates PWM waveform, with described DSP module communication;

Described FPGA module, within the single sampling period, is utilized high frequency clock, the multi-point sampling PWM height of constant durationSignal, changes PWM height to deposit in same record ripple semaphore with 1 and 0 form; FPGA module is record ripple semaphoreSend to DSP module, and in the time that sample-synchronous signal is effective, produce interrupt signal to DSP module.

2. the PWM test macro based on monocycle multi-point sampling according to claim 1, is characterized in that: single adoptingN sampled point was set in the sample cycle and samples, N gets 16,32 or 48.

3. the PWM test macro based on monocycle multi-point sampling according to claim 1, is characterized in that: described inDSP module interrupts processing to the interrupt signal receiving, and controls address bus and data/address bus and relevant read-write enable signal,DSP module receives simultaneously records ripple semaphore, and starts backboard communication, controls backboard communication sequential, through core bus, record ripple is believedNumber amount sends to telecommunication management plate module.

4. according to the PWM test macro based on monocycle multi-point sampling described in claim 1 or 3, it is characterized in that: instituteState telecommunication management plate module and comprise SRAM memory and NANDFLASH memory; Described SRAM memory is for storageThe ripple semaphore of pre-recording that described telecommunication management plate module receives, described NANDFLASH memory is used for storing starting to be recorded after rippleRecord ripple semaphore.

5. the PWM test macro based on monocycle multi-point sampling according to claim 1, is characterized in that: described logicalFuse tube reason plate module is passed to described wave recording device according to record ripple agreement the record ripple semaphore of storage.

6. the PWM test macro based on monocycle multi-point sampling according to claim 5, is characterized in that: described recordWave apparatus, within the single sampling period, is resolved PWM high-low signal according to time order and function order, and constant duration completes singleThe record ripple described point in sampling period.