CN103605028B - A kind of PWM test macro based on monocycle multi-point sampling - Google Patents
A kind of PWM test macro based on monocycle multi-point sampling Download PDFInfo
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Abstract
The invention provides a kind of PWM test macro based on monocycle multi-point sampling, described system comprises PWM current transformer valve control plate module, telecommunication management plate module and wave recording device; Described PWM current transformer valve control plate module is communicated by letter with wave recording device by telecommunication management plate module. The invention provides a kind of PWM test macro based on monocycle multi-point sampling, within the single sampling period, to PWM waveform multi-point sampling, the actual samples frequency to pwm signal has been improved to several times; Can flexible configuration, can be according to demand, be arranged to the samplings such as monocycles 16 point, 32 points, at 48, further to improve sample frequency, make test record waveform more accurate, and can be used in the valve control device of static synchronous reacance generator SVG, static synchronous reactive compensator STATCOM, THE UPFC UPFC, high-voltage dc transmission electric installation.
Description
Technical field
The present invention relates to a kind of test macro, specifically relate to a kind of PWM test macro based on monocycle multi-point sampling.
Background technology
At present, power electronics PWM current transformer is widely used in electric power quality control field, as active power filteringDevice APF, SVG, STATCOM etc. What the overall structure of current transformer corresponding controllers generally adopted is that (responsible adjusting is protected in controlControl protection), the composition form of valve control (power model detection trigger), cell controller (power model interface).
For the duty of Real-Time Monitoring converter device, the host computer of device generally has the functions such as remote measurement, remote signalling, record ripple.Wherein recording wave energy can be in the time of device stable state or plant failure transient state, starting the record ripple moment for the previous period and one section afterwardsUnit simulation amount, the switching signal etc. of time are deposited in host computer. The every power frequency period of the general selection of signal sampling frequency of current transformer128 points (sample frequency 6.4kHz, sampling period 156us) or 256 points ((sample frequency 12.8kHz, sampling period 78us).
For analog quantitys such as current/voltages, owing to being that power frequency changes, when being 156us or 78us, can obtain comparatively in the sampling periodComplete record waveform. But for the test of PWM waveform output in PWM current transformer, because its switching frequency scope is severalHundred Hz are to several KHz, and minimum pulse width is tens of us, if the sampling period is 156us or 78us, cannot obtain accurate PWMRecord waveform.
At present in PWM current transformer host computer and special power system fault recorder, all only for analog quantity, openEnter the record ripple passage of the amount of outputing, there is no the record wave energy for PWM waveform specially. Power system RTDS(Real-TimeDigitalSimulator, real-timedigital simulation system) device users can utilize RTDS to cell controller PWM output carry out little step-lengthSampling obtains PWM record ripple signal, but RTDS device is expensive, uses comparatively complicated.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the invention provides a kind of PWM test macro based on monocycle multi-point sampling,For static synchronous reacance generator SVG, static synchronous reactive compensator STATCOM, THE UPFC UPFC,In the valve control device of high-voltage dc transmission electric installation.
In order to realize foregoing invention object, the present invention takes following technical scheme:
The invention provides a kind of PWM test macro based on monocycle multi-point sampling, described system comprises PWM current transformer valveControl plate module, telecommunication management plate module and wave recording device; Described PWM current transformer valve control plate module is by telecommunication management plate moduleCommunicate by letter with wave recording device.
Described PWM current transformer valve control plate module comprises FPGA module and DSP module; Described FPGA module is according to positive taut pulseWide modulator approach, compares modulating wave and carrier wave size in real time, generates PWM waveform, with described DSP module communication.
Described FPGA module, within the single sampling period, is utilized high frequency clock, the multi-point sampling PWM height of constant durationSignal, changes PWM height to deposit in same record ripple semaphore with 1 and 0 form; FPGA module is record ripple semaphoreSend to DSP module, and in the time that sample-synchronous signal is effective, produce interrupt signal to DSP module.
N sampled point was set in the single sampling period and samples, N gets 16,32 or 48.
Described DSP module interrupts processing to the interrupt signal receiving, and controls address bus and data/address bus and be correlated with to read and write to makeEnergy signal, DSP module receives record ripple semaphore simultaneously, and starts backboard communication, controls backboard communication sequential, through core busRecord ripple semaphore is sent to telecommunication management plate module.
Described telecommunication management plate module comprises SRAM memory and NANDFLASH memory; Described SRAM memory is usedThe ripple semaphore of pre-recording receiving in the described telecommunication management plate module of storage, described NANDFLASH memory is used for storing startupRecord ripple semaphore after record ripple.
Described telecommunication management plate module is passed to described wave recording device according to record ripple agreement the record ripple semaphore of storage.
Described wave recording device, within the single sampling period, is resolved PWM high-low signal according to time order and function order, between equal timeEvery the record ripple described point that completes the single sampling period.
Compared with prior art, beneficial effect of the present invention is:
1) can be used for static synchronous reacance generator SVG, static synchronous reactive compensator STATCOM, unified trend controlIn the valve control device of device UPFC, high-voltage dc transmission electric installation;
2) the present invention, to PWM waveform multi-point sampling within the single sampling period, puies forward the actual samples frequency to pwm signalHigh several times;
3) realize PWM testing cost lower, simple and reliable, without complicated and expensive RTDS device;
4) can flexible configuration, can be according to demand, be arranged to the samplings such as monocycles 16 point, 32 points, at 48, with furtherImprove sample frequency, make test record waveform more accurate.
Brief description of the drawings
Fig. 1 is the PWM test system structure block diagram based on monocycle multi-point sampling;
Fig. 2 is the PWM test process figure of monocycle multi-point sampling.
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The invention provides a kind of PWM test macro based on monocycle multi-point sampling, described system comprises PWM current transformer valveControl plate module, telecommunication management plate module and wave recording device; Described PWM current transformer valve control plate module is by telecommunication management plate moduleCommunicate by letter with wave recording device.
Described PWM current transformer valve control plate module comprises FPGA module and DSP module; Described FPGA module is according to positive taut pulseWide modulator approach, compares modulating wave and carrier wave size in real time, generates PWM waveform, with described DSP module communication.
Described FPGA module, within the single sampling period, is utilized high frequency clock, the multi-point sampling PWM height of constant durationSignal, changes PWM height to deposit in same record ripple semaphore with 1 and 0 form; FPGA module is record ripple semaphoreSend to DSP module, and in the time that sample-synchronous signal is effective, produce interrupt signal to DSP module.
N sampled point was set in the single sampling period and samples, N gets 16,32 or 48.
Described DSP module interrupts processing to the interrupt signal receiving, and controls address bus and data/address bus and be correlated with to read and write to makeEnergy signal, DSP module receives record ripple semaphore simultaneously, and starts backboard communication, controls backboard communication sequential, through core busRecord ripple semaphore is sent to telecommunication management plate module.
Described telecommunication management plate module comprises SRAM memory and NANDFLASH memory; Described SRAM memory is usedThe ripple semaphore of pre-recording receiving in the described telecommunication management plate module of storage, described NANDFLASH memory is used for storing startupRecord ripple semaphore after record ripple.
Described telecommunication management plate module is passed to described wave recording device according to record ripple agreement the record ripple semaphore of storage.
Described wave recording device, within the single sampling period, is resolved PWM high-low signal according to time order and function order, between equal timeEvery the record ripple described point that completes the single sampling period.
Embodiment
Carry out PWM and be sampled as example with sampling period 156us, 16 points of each cycle below, embodiments of the invention are done in detailExplanation.
As Fig. 1, the invention provides a kind of PWM test macro based on monocycle multi-point sampling, comprise the control of PWM current transformer valvePlate module, telecommunication management plate module and wave recording device; Described PWM current transformer valve control plate module by telecommunication management plate module withWave recording device communication.
Described PWM current transformer valve control plate module comprises FPGA module and DSP module; Described FPGA module is according to positive taut pulseWide modulator approach, compares modulating wave and carrier wave size in real time, generates PWM waveform, with described DSP module communication.
Described FPGA module adopts XC3S5000 chip; Described DSP module adopts TMS320F28335 chip.
Suppose that FPGA module and DSP module dual port RAM call duration time are spaced apart 156us, dual port RAM interrupt signal byFPGA module produces, and the cycle is also 156us. FPGA inside modules adopts 20MHz clock sampling and counting, PWM pulsewidthFor 32us, for above situation, as shown in Figure 2, test macro is surveyed according to following process implementation monocycle multi-point sampling PWMExamination:
1) sample-synchronous signal adopts dual port RAM interrupt signal, after 20MHz clock detection is drawn high to this signal, and FPGA mouldBOB(beginning of block) sampling PWM output;
2) the every meter of 20MHz clock 9.75us carries out a PWM output sampling, and successively sampled value is deposited from low level to a high positionEnter the PWM sampled signal amount of 16, that is: 0us sampled value deposits semaphore bit0 in, and 9.75us sampled value deposits inBit1,9.75*2us sampled value deposits bit2 in, analogizes, and 9.75*nus sampled value deposits bit (n) in, and the sampling time is to 9.75*15=146.25usTime, PWM output sampled value is deposited in to semaphore bit15;
3), when next sample-synchronous signal is effective, FPGA module sent to DSP module the pwm signal amount in a upper cycle,Telecommunication management plate module is received the pwm signal amount of valve control plate transmission and is sent to wave recording device record by backboard McBSP busRipple;
4) wave recording device obtains recording after ripple pwm signal amount recorder data, in 156us, and according to from low level to high-order order,Constant duration (9.75us) is got successively the value of corresponding bit position and is carried out 0 or 1 described point.
So far, realized the test of monocycle (156us) multiple spot (16 point) sampling PWM, by checking in wave recording deviceRecord waveform, related personnel can judge that whether the PWM of FPGA output is normal.
Because sample-synchronous signal and PWM height changes objective reality time difference in moment and discrete sampling, what finally obtain adoptsSample value height continues width and PWM developed width has error, monocycles 16 point sampling error range: ± 7.95us. This exampleDue to discrete sampling, error is 4*7.95us-32us=﹢ 7us, and the PWM width that sampling obtains is 39us. Can be by carryingThe counting of high monocycle sampling (as 32 points, 48 etc.) further reduces this error.
Finally should be noted that: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit, although referenceAbove-described embodiment has been described in detail the present invention, and those of ordinary skill in the field are to be understood that: still can be to thisInvention detailed description of the invention modify or be equal to replacement, and do not depart from spirit and scope of the invention any amendment or etc.With replacing, it all should be encompassed in the middle of claim scope of the present invention.
Claims (6)
1. the PWM test macro based on monocycle multi-point sampling, is characterized in that: described system comprises PWM unsteady flowDevice valve control plate module, telecommunication management plate module and wave recording device; Described PWM current transformer valve control plate module is by telecommunication management plateModule is communicated by letter with wave recording device;
Described PWM current transformer valve control plate module comprises FPGA module and DSP module; Described FPGA module is according to positive taut pulseWide modulator approach, compares modulating wave and carrier wave size in real time, generates PWM waveform, with described DSP module communication;
Described FPGA module, within the single sampling period, is utilized high frequency clock, the multi-point sampling PWM height of constant durationSignal, changes PWM height to deposit in same record ripple semaphore with 1 and 0 form; FPGA module is record ripple semaphoreSend to DSP module, and in the time that sample-synchronous signal is effective, produce interrupt signal to DSP module.
2. the PWM test macro based on monocycle multi-point sampling according to claim 1, is characterized in that: single adoptingN sampled point was set in the sample cycle and samples, N gets 16,32 or 48.
3. the PWM test macro based on monocycle multi-point sampling according to claim 1, is characterized in that: described inDSP module interrupts processing to the interrupt signal receiving, and controls address bus and data/address bus and relevant read-write enable signal,DSP module receives simultaneously records ripple semaphore, and starts backboard communication, controls backboard communication sequential, through core bus, record ripple is believedNumber amount sends to telecommunication management plate module.
4. according to the PWM test macro based on monocycle multi-point sampling described in claim 1 or 3, it is characterized in that: instituteState telecommunication management plate module and comprise SRAM memory and NANDFLASH memory; Described SRAM memory is for storageThe ripple semaphore of pre-recording that described telecommunication management plate module receives, described NANDFLASH memory is used for storing starting to be recorded after rippleRecord ripple semaphore.
5. the PWM test macro based on monocycle multi-point sampling according to claim 1, is characterized in that: described logicalFuse tube reason plate module is passed to described wave recording device according to record ripple agreement the record ripple semaphore of storage.
6. the PWM test macro based on monocycle multi-point sampling according to claim 5, is characterized in that: described recordWave apparatus, within the single sampling period, is resolved PWM high-low signal according to time order and function order, and constant duration completes singleThe record ripple described point in sampling period.
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| CN104950693B (en) * | 2015-06-23 | 2018-03-27 | 广州供电局有限公司 | Improve the method and system of controller hardware assemblage on-orbit simulation accuracy |
| CN109031981A (en) * | 2018-09-27 | 2018-12-18 | 南方电网科学研究院有限责任公司 | Simulation test method and system of valve control device based on FPGA |
| CN109031980A (en) * | 2018-09-27 | 2018-12-18 | 南方电网科学研究院有限责任公司 | Simulation test method and system of valve control device based on FPGA |
| CN111786865B (en) * | 2020-06-09 | 2021-11-12 | 青岛信芯微电子科技股份有限公司 | Data processing method and equipment |
| CN112946355A (en) * | 2021-02-25 | 2021-06-11 | 云谷技术(珠海)有限公司 | Power distribution terminal PWM analog sampling system and method |
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| US20100085676A1 (en) * | 2008-10-03 | 2010-04-08 | Honeywell International Inc. | Nested pulse width modulation control |
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| CN101599656A (en) * | 2009-04-16 | 2009-12-09 | 中国石油大学(华东) | A kind of charge-discharge machine for power storage battery test system |
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Effective date of registration: 20170531 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee after: China Electric Prime Technology Co., Ltd. Patentee after: State Grid Corporation of China Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee before: State Grid Smart Grid Institute Patentee before: State Grid Corporation of China Co-patentee before: China Electric Prime Technology Co., Ltd. |