CN103579298B - The field element of high-voltage semiconductor element - Google Patents
The field element of high-voltage semiconductor element Download PDFInfo
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- CN103579298B CN103579298B CN201210282402.6A CN201210282402A CN103579298B CN 103579298 B CN103579298 B CN 103579298B CN 201210282402 A CN201210282402 A CN 201210282402A CN 103579298 B CN103579298 B CN 103579298B
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- 239000004065 semiconductor Substances 0.000 title abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 description 14
- 150000004706 metal oxides Chemical class 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 239000002131 composite material Substances 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000009467 reduction Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of field element of high-voltage semiconductor element, this element comprises a substrate of one first conductivity type; One first trap is one second conductivity type, is be formed in substrate and expanded downwards by the surface of substrate; One second trap is the first conductivity type and to be formed in substrate and to be expanded downwards by the surface of substrate, and the second trap adjoins the side of the first trap, and substrate is then positioned at the opposite side of the first trap; One first doped region is the first conductivity type, is be formed at the second trap place and be separated by a distance with the first trap, and wherein the doping content of the first doped region is greater than the doping content of the second trap; One wire, is electric connection first doped region and crosses over (across) first top of trap; With an electric conductor (conductive? body), be between wire and the first trap, and electric conductor crosses over (across) first trap accordingly below wire, electric conductor and wire are by electrical isolation.When high-voltage semiconductor element operates, be applying one high pressure in wire, and apply a fixed-bias transistor circuit to this electric conductor, or do not apply any external voltage in this electric conductor, all can effectively avoid an element to open.
Description
Technical field
The invention relates to a kind of field element effectively can improveing the threshold voltage (Thresholdvoltage) of the parasitic fields element of high-voltage semiconductor element.
Background technology
Between nearly decades, semiconductor industry continues the size reducing semiconductor structure, and improves the unit cost of speed, usefulness, density and integrated circuit simultaneously.For the semiconductor element (as metal-oxide semiconductor (MOS) MOS) that high pressure or superhigh pressure operate, between metal wire in silicon technology to its element connected, the problem that parasitic fields element is opened can be brought out in some region that metal wire is crossed over.That is, to MOS transistor under operation with high pressure, the impact of the threshold voltage (Vth) of the parasitic fields element be unlocked and restriction, the input operating range of MOS transistor may lower than its puncture voltage.
The method avoiding an element to open proposed at present: form pad (pad) in the high-pressure N-shaped trap of such as element on the scene and make do not have pressure reduction between drain electrode end and field element, electric current is not just had to pass through, but pad area takes up space greatly, and easily there is the risk causing high-pressure N-shaped trap insulation isolation failed.In addition, also the mode utilizing and increase field element high-pressure N-shaped trap upper oxide thickness is had, make more difficult labour life reversion (channelreverse) under operation with high pressure of high-pressure N-shaped trap, and increase the difficulty of field element unlatching, but the method increases the time (formation oxide) of semiconductor element thermal process, not only need extra heat budget (extrathermalbudge), its heat history also may cause harmful effect to other elements.
Therefore, how not increase any cost, as extra heat budget and the time cost and the money cost that need additional masks, and the threshold voltage of field element can improved, and then maintain the input operating range of the high-voltage semiconductor element applied, in fact for industry makes great efforts one of target.
Summary of the invention
The invention relates to a kind of field element of high-voltage semiconductor element, not only can not increase manufacturing cost and element area area, also effectively can improve the threshold voltage of the parasitic fields element of high-voltage semiconductor element, when avoiding semiconductor element operation with high pressure, field element is opened.
According to an aspect of the present invention, be propose a kind of field element (fielddevice), comprise a substrate of one first conductivity type; One first trap is one second conductivity type, is be formed in substrate and expanded downwards by the surface of substrate; One second trap is the first conductivity type and to be formed in substrate and to be expanded downwards by the surface of substrate, and the second trap adjoins the side of the first trap, and substrate is then positioned at the opposite side of the first trap; One first doped region is the first conductivity type, is be formed at the second trap place and be separated by a distance with the first trap, and wherein the doping content of the first doped region is greater than the doping content of the second trap; One wire, is electric connection first doped region and crosses over (across) first top of trap; With an electric conductor (conductivebody), be between wire and the first trap, and electric conductor crosses over (across) first trap accordingly below wire, electric conductor and wire are by electrical isolation.
In accordance with a further aspect of the present invention, be the method for operation proposing a kind of high-voltage semiconductor element, the high-voltage semiconductor element providing and have above-mentioned field element is provided; When high-voltage semiconductor element operates, be applying one high pressure in wire, and apply a fixed-bias transistor circuit to this electric conductor, or do not apply any external voltage in this electric conductor.
In order to have better understanding, special embodiment below to above-mentioned and other aspect of the present invention, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Figure 1A is the partial top view of high-voltage metal oxide semiconductor (HVMOS) element according to one of first embodiment of the invention with an element.
Figure 1B is the corresponding field element of Figure 1A of first embodiment of the invention and the generalized section of high-voltage metal oxide semiconductor element thereof.
Fig. 2 A is the partial top view of high-voltage metal oxide semiconductor (HVMOS) element according to one of second embodiment of the invention with an element.
Fig. 2 B is the field element of second embodiment of the invention corresponding diagram 2A and the generalized section of high-voltage metal oxide semiconductor element thereof.
Fig. 3 is the generalized section of the field element of third embodiment of the invention.
Fig. 4 is the generalized section of related embodiment of the present invention wherein five kinds of field element aspects.
[main element symbol description]
1:HVMOS element
111:P type substrate
112:N type buried regions
113:P type trap
114,131: high-pressure N-shaped trap
115: high-voltage P-type trap
116:N type body (N-body)
121,122,123:P type doped region
124:N type doped region
126: insulating barrier
127: patterned conductive layer
13,23,33: field element
141: wire
133,233,333: electric conductor
333a: main part
333b: trunk portion
136: the first insulating barriers
137: the first intermediate dielectric layer (firstILD)
138: the second insulating barriers
332: the second doped regions
422,423: single level polysilicon
435,436,437: composite bed
437a: polysilicon
437b: metal level
Embodiment
In the embodiment of this summary of the invention, propose field element, the high-voltage semiconductor element of application and method of operation thereof, when not increasing cost and element area area, the threshold voltage (Thresholdvoltage) of the parasitic fields element of high-voltage semiconductor element effectively can be improved.
Be below propose to organize embodiment, cooperation correlative type, so that some in summary of the invention to be described, but is not whole more, the aspect of field element of high-voltage semiconductor element.In fact, various embodiment of the present invention can represent by many different kenels, and not should limit by the embodiment content of this summary of the invention; But these embodiments proposed in this summary of the invention are the demands that can meet in application.Moreover describing in embodiment, as thin portion structure, processing step and materials application etc., is only the use illustrated, not does limit to the present invention for the scope of protection.In the embodiment of this summary of the invention, be explain with high-voltage metal oxide semiconductor (highvoltagemetal-oxide-semiconductor, HVMOS) element and field element thereof, but the present invention is not limited only to this.In forming an electric conductor (conductivebody) across between the wire at element place, field and a high pressure trap of field element, when semiconductor element is under operation with high pressure, wire and allow the pressure reduction produced between an element can be dispersed on this electric conductor, the effectively threshold voltage of improvement field element.
< first embodiment >
Figure 1A is the partial top view of high-voltage metal oxide semiconductor (HVMOS) element according to one of first embodiment of the invention with an element.Figure 1B is the corresponding field element of Figure 1A of first embodiment of the invention and the generalized section of high-voltage metal oxide semiconductor element thereof.Please refer to Figure 1A and Figure 1B.HVMOS element 1 comprises a P type substrate 111, is formed at the n type buried layer (N+BuriedLayer, NBL) 112 at P type substrate 111 place, P type trap (PW) 113, high-pressure N-shaped trap (HVNW) 114 and 131, high-voltage P-type trap (HVPW) 115, N-type body (N-body) 116, P type doped region (P+region) 121,122 and 123, N-type doped region (N+region) 124 and insulating barrier 126.Wherein, n type buried layer 112 can provide isolation features, and high-voltage P-type trap (HVPW) 115 is positioned at two high-pressure N-shaped traps (HVNW) between 114 and 131.P type doped region 121 is positioned at P type trap 113 place and is electrically connected to P type substrate 111, and N-type doped region 124 is positioned at N-type body 116 place and is one source pole end (source).Insulating barrier 126 (as oxide) is formed at above P type trap 113, high-pressure N-shaped trap 114 and high-voltage P-type trap 115, and between P type doped region 121 and N-type doped region 124.Another insulating barrier 126 is between P type doped region 123 and N-type body 116, and top forms a patterned conductive layer 127 is electrically connected to P type doped region 122 using as a grid (Gate).
HVMOS element 1 more comprises an element (fielddevice) 13, (namely the first trap is one second conductivity type to comprise one first trap such as high-pressure N-shaped trap (HVNW) 131, in the substrate being formed at the first conductivity type and expanded downwards by substrate surface), (namely the second trap is the first conductivity type to one second trap such as high-voltage P-type trap (HVPW) 115, to be formed in substrate and to be expanded downwards by substrate surface), one first doped region is as P type doped region 123 (namely the first doped region is the first conductivity type), one wire 141 is electric connection first doped region (as P type doped region 123) and crosses over (across) first top of trap (as HVNW131), and one electric conductor (conductivebody) 133 be positioned between wire 141 and the first trap (as HVNW131), and electric conductor 133 crosses over (across) first trap accordingly below wire 141, electric conductor 133 and wire 141 are by electrical isolation.Wherein, the side of adjacent first trap (as HVNW131) of the second trap (as HVPW115), substrate is then positioned at the opposite side of the first trap.First doped region (as P type doped region 123) is formed at the second trap place and is separated by a distance with the first trap, and wherein the doping content of the first doped region is greater than the doping content of the second trap.
Moreover field element 13 more comprises one first insulating barrier 136 and is positioned at the first trap (as HVNW131) top and extends to the first doped region (as P type doped region 123), and wherein, electric conductor 133 is positioned at above the first insulating barrier 136.First insulating barrier 136 is such as a field oxide (FOX).In one embodiment, field element 13 can comprise one first intermediate dielectric layer (firstILD) 137 between the first insulating barrier 136 and electric conductor 133; Also can be that the first insulating barrier 136 directly fills up between the first trap (as HVNW131) and electric conductor 133.In one embodiment, field element 13 more comprises one second insulating barrier 138, as the second intermediate dielectric layer (secondILD), between wire 141 and electric conductor 133, makes electric conductor 133 and wire 141 electrical isolation.First intermediate dielectric layer (firstILD) 137 and the second insulating barrier 138 are such as oxides.
In one embodiment, wire 141 is such as a top metal wires (topmetalline); The material of electric conductor 133 is such as that polysilicon, metal are as aluminium, copper, silver ... wait or any electric conducting material, suitably can add the making of electric conductor 133 pattern, and need not increase extra technique and region in original technique.
In one embodiment, the form of electric conductor 133 is such as a conducting ring (conductivering), is located on the second trap as the surrounding of HVPW115 and be positioned at below wire 141, as shown in Figure 1A.But the present invention is not as limit, the enforcement aspect of electric conductor 133 can be that the ring-type of various shape is as square, circular, oval or other shapes, or the local pattern of aforementioned cyclic, or do not interfere with whole kenel of other elements, dispersion pressure reduction can be reached and effectively improve the effect of the threshold voltage of an element.In a first embodiment, when the HVMOS element 1 of application under high pressure operates, electric conductor 133 is need not external any bias voltage.
In the above-described embodiments, be the first conductivity type and the second conductivity type with P type and N-type respectively, the substrate that element 13 comprises on the spot is P type substrate 111, first trap is high-pressure N-shaped trap (HVNW) 131, second trap is high-voltage P-type trap (HVPW) 115, the current path that field element 13 structure that embodiment proposes can make the n-quadrant of P-N-P (HVNW131) avoid producing reversal development and form unlatching.But the present invention is not as limit, first conductivity type and the second conductivity type also can be respectively N-type and P type, first trap can be a high-voltage P-type trap (HVPW), second trap can be a high-pressure N-shaped trap (HVNW), the P region of its N-P-N formed is avoided producing reversal development, avoids an element to open.
< second embodiment >
Fig. 2 A is the partial top view of high-voltage metal oxide semiconductor (HVMOS) element according to one of second embodiment of the invention with an element.Fig. 2 B is the field element of second embodiment of the invention corresponding diagram 2A and the generalized section of high-voltage metal oxide semiconductor element thereof.In Fig. 2 A, Fig. 2 B, the element identical with Figure 1A, Figure 1B uses same or similar element numbers, and similar elements please refer to the first embodiment, also repeats no more at this.
The field element 23 of the second embodiment, its electric conductor 233 is arranged at below wire 141 equally, but electric conductor 233 is more electrically connected to an external voltage source, can apply a fixed-bias transistor circuit to this electric conductor 233.Its method for making suitably can also add the making of electric conductor 233 pattern in original technique, and need not increase extra technique and region.
In second embodiment, electric conductor 233 is such as the conducting ring of floating-gate metal (floatingmetal) or tool fixed-bias transistor circuit.When the HVMOS element applied under high pressure operates, for floating-gate metal electric conductor 233 or provide a fixed-bias transistor circuit (fixedvoltagebias) to electric conductor 233 (maintaining specific voltage with compulsory passages district), all can effectively avoid an element 23 to open.In one embodiment, such as when wire 141 imposes-150V, electric conductor 233 imposes 0V ,-10V ,-20V ,-30V ,-40V ,-70V ,-80V... etc. or other fixed-bias transistor circuit value (fixed-bias transistor circuit value is required depending on practical application condition, is not limited to those numerical value).
< the 3rd embodiment >
Fig. 3 is the generalized section of the field element of third embodiment of the invention.In Fig. 3, the element identical with Figure 1A-Fig. 2 B uses same or similar element numbers, and similar elements please refer to previous embodiment, does not repeat them here.
In 3rd embodiment, the electric conductor 333 of field element 33 is still arranged between the first trap (as HVNW131) and wire 141; And field element 33 more comprises one second doped region 332, be formed in the first trap (as HVNW131) and interrupt the continuous of the first trap, second doped region 332 has identical conductive state with (being such as the second conductivity type) first trap, and the doping content of the second doped region 332 is greater than the doping content of the first trap, and the second doped region 332 of the 3rd embodiment is electrically connected with electric conductor 333.In one embodiment, the second doped region 332 is such as a heavily doped region (heavilydopedregion), and doping content is such as 3E15 (1/cm
2).Second doped region 332 still makes the first trap (as HVNW131) have good isolation.
As shown in Figure 3, electric conductor 333 be such as a trunk portion (pillarportion) 333b comprising a main part 333a and connection, trunk portion 333b to downward-extension with through the first insulating barrier 136 to be connected with the second doped region 332.Its method for making suitably can also add the making of electric conductor 333 pattern in original technique, and need not increase extra technique and region.
In the third embodiment, when the HVMOS element of application under high pressure operates, electric conductor 333 be such as in the first embodiment need not external any bias voltage, can effectively avoid an element 33 to open.
Moreover, be explain for the electric conductor of individual layer (as 133,233,333a) in above-described embodiment, but the present invention is not as limit, and a composite bed also can be used as the electric conductor of application.Fig. 4 is the generalized section of related embodiment of the present invention wherein five kinds of field element aspects.As shown in Figure 4, the present invention can use if single level polysilicon 432 (as PL2), 433 (as PL3) are as the electric conductor below wire 141, and wherein single level polysilicon 432 is directly formed on the first insulating barrier 136; Then such as, with intermediate dielectric layer (ILD, oxide) electrical isolation between single level polysilicon 433 and wire 141, and and the spacing and separating with intermediate dielectric layer of being separated by between the first insulating barrier 136.Single level polysilicon or as the electric conductors such as metal can avoid an element under operation with high pressure improper unlatching cause passage reversion.Moreover, as shown in Figure 4, the present invention also can use composite bed, the composite bed 437 of the PIP composite bed 435 of such as two-layer polysilicon sandwiched one insulating barrier or the MIM composite bed 436 of two metal layers sandwiched one insulating barrier or one deck polysilicon 437a collocation layer of metal layer 437b or the combination of one deck polysilicon and layer of metal layer sandwiched one insulating barrier (not shown) etc., can avoid the element passage that improper unlatching causes under operation with high pressure to reverse.Wherein, PIP composite bed 435 is such as directly be formed on the first insulating barrier 136; MIM composite bed 436 is such as the spacing and separating with intermediate dielectric layer of being separated by between the first insulating barrier 136; The composite bed 437 that polysilicon 437a and metal level 437b arranges in pairs or groups is such as that polysilicon 437a is directly formed on the first insulating barrier 136, is separate with intermediate dielectric layer between polysilicon 437a and metal level 437b.But the present invention is not limited to this, also can produce other according to the condition change of above-described embodiment and practical application and adjustment and apply aspect.
The application of above-described embodiment is very extensive, such as PN junction (PNjunction), bipolar junction transistors (bipolarjunctiontransistor, BJT), mos field effect transistor (metal-oxide-semiconductorfieldeffecttransistor, MOSFET), drain electrode extends metal-oxide semiconductor (MOS) conductor (extendeddrainMOS, EDN/PMOS), sideways diffusion type metal oxide semiconductor conductor (lateraldiffusedMOS, LDN/PMOS), double-diffused drain electrode metal-oxide semiconductor (MOS) conductor (doublediffuseddrainMOS, DDDN/PMOS), lightly doped drain metal-oxide semiconductor (MOS) conductor (lightly-dopeddrainMOS, LDDN/PMOS), COOLMOS
tM, vertical DMOS conductor (verticaldouble-diffusedMOS, VDMOS), igbt (insulatedgatebipolartransistor, IGBT) ... etc. variously have parasitic fields element to open the semiconductor element of problem, can apply as above-described embodiment at wire as arranged an electric conductor below top metal wires, or when high voltage device operates, a fixed-bias transistor circuit is applied to set electric conductor, or the high-concentration dopant district (conductive state identical with HVNW131) electric conductor is electrically connected in the first trap (as HVNW131), an element all can be effectively avoided to open.
In sum, although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (8)
1. a field element (fielddevice), comprising:
One substrate of one first conductivity type;
One first trap is one second conductivity type, is be formed in this substrate and expanded downwards by the surface of this substrate;
One second trap, for this first conductivity type is expanded downwards with being formed in this substrate and by the surface of this substrate, this second trap adjoins the side of this first trap, and this substrate is then positioned at the opposite side of this first trap;
One first doped region is this first conductivity type, is be formed at this second trap place and be separated by a distance with this first trap, and wherein the doping content of this first doped region is greater than the doping content of this second trap;
One wire is the top being electrically connected this first doped region and crossing over (across) this first trap;
One electric conductor (conductivebody), be cross over (across) this first trap accordingly between this wire and this first trap and below this wire, this electric conductor and this wire are by electrical isolation;
One first insulating barrier, being positioned at above this first trap and extending to this first doped region, wherein this electric conductor is positioned at above this first insulating barrier; And
One first intermediate dielectric layer (firstILD), between this first insulating barrier and this electric conductor.
2. according to claim 1 element, wherein this electric conductor is electrically connected to a voltage source, can apply a fixed-bias transistor circuit to this electric conductor.
3. according to claim 1 element, more comprise one second doped region for this second conductivity type, be formed at this first trap place and interrupt the continuous of this first trap, and the doping content of this second doped region is greater than the doping content of this first trap, this second doped region is electrically connected with this electric conductor.
4. according to claim 3 element, wherein this electric conductor comprise a trunk portion (pillarportion) to downward-extension with through this first insulating barrier to be connected with this second doped region.
5. according to claim 1 element, wherein this first insulating barrier is a field oxide.
6. according to claim 1 element, more comprises one second insulating barrier between this wire and this electric conductor, makes this electric conductor and this wire electrical isolation.
7. according to claim 6 element, wherein this second insulating barrier is one second intermediate dielectric layer (secondILD).
8. according to claim 1 element, wherein this electric conductor is a polysilicon or a metal level of individual layer.
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| CN201210282402.6A CN103579298B (en) | 2012-08-09 | 2012-08-09 | The field element of high-voltage semiconductor element |
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| CN201210282402.6A CN103579298B (en) | 2012-08-09 | 2012-08-09 | The field element of high-voltage semiconductor element |
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| CN103579298B true CN103579298B (en) | 2016-04-27 |
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| US5654574A (en) * | 1994-10-19 | 1997-08-05 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5654574A (en) * | 1994-10-19 | 1997-08-05 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
| CN101752366A (en) * | 2008-12-17 | 2010-06-23 | 三菱电机株式会社 | Semiconductor device |
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