CN103560151B - Optimize hyperconjugation VDMOS and the preparation method of body diode reverse recovery characteristics - Google Patents
Optimize hyperconjugation VDMOS and the preparation method of body diode reverse recovery characteristics Download PDFInfo
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- CN103560151B CN103560151B CN201310489831.5A CN201310489831A CN103560151B CN 103560151 B CN103560151 B CN 103560151B CN 201310489831 A CN201310489831 A CN 201310489831A CN 103560151 B CN103560151 B CN 103560151B
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- 238000011084 recovery Methods 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000000407 epitaxy Methods 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 55
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000024241 parasitism Effects 0.000 abstract description 2
- 208000034657 Convalescence Diseases 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The present invention relates to a kind of hyperconjugation VDMOS and the preparation method that optimize body diode reverse recovery characteristics.In the structure of conventional hyperconjugation VDMOS this expropriation of land parasitism bipolar transistor NPN structure and body diode structure, open for avoiding this parasitic NPN transistor, the reverse recovery current flowing through P post or body diode top must be reduced, reduce parasitic NPN pipe base resistance R
bthe pressure drop at two ends make it open.The present invention includes P post and be positioned at the Pbody district of P column top, it is characterized in that: the sidewall on described P post top is provided with oxide layer.P post sidewall of the present invention has silicon dioxide oxide layer, the component failure that the unlatching avoiding parasitic bipolar NPN transistor causes; The deep etching of the compatible superjunction of the present invention and deep trouth epitaxy technique, do not increase manufacture technics cost while lifting body diode reverse recovery ability.
Description
Technical field
The invention belongs to semiconductor device and manufacture technics field, be specifically related to a kind of hyperconjugation VDMOS and the preparation method that optimize body diode reverse recovery characteristics.
Background technology
In high-voltage switch gear application, need to adopt and there is the body diode of superperformance and the strong VDMOS of durability, but the conducting resistance that the VDMOS device of routine is higher adds the quiescent dissipation of switching circuit, be introduced into market according to the device designed by superjunction theory (SuperJunction) charge balance concept at the end of the nineties, it has the R more much lower than conventional VDMOS
dS(on) be used widely.Due to its R
dSand BV (on)
1.3proportional, and the R of commonplace components
dS(on) be and BV
2.5proportional, its R
dS(on) more much lower than common MOSFET, therefore the application of this kind of superjunction devices when high voltage is very attractive.
Diode is called Reverse recovery by on-state to the switching process of reverse blocking state, as shown in Figure 1, the intrinsic diode that the P post of hyperconjugation VDMOS and N epitaxial loayer are formed is called body diode, in switch application especially bridge circuit, the reverse drain current needing body diode to provide is circuit afterflow, and oppositely turn off after body diode conducting, high voltage change ratio (dv/dt) will be produced, this may cause parasitic NPN transistor to open, and thus the reliability of the reversely restoring process of body diode is extremely crucial in this application.
Hyperconjugation VDMOS device obtains charge balance by numerous PN column structure, and this structure brings two consequences to the body diode of hyperconjugation VDMOS device simultaneously, and one is that the area of PN junction is large many, Irrm and Qrr rising when causing larger injections; Two is exhaust due to PN post knot the increase bringing dv/dt fast, causes parasitic NPN transistor open or recover very soon.Thus, a shortcoming of common hyperconjugation VDMOS is exactly that the reverse recovery characteristic of its body diode is poor.Hyperconjugation VDMOS device has larger reverse recovery current, and is easy to when some Reverse recovery lose efficacy.In addition, application circuit requires that body diode also should be able to bear higher di/dt and dv/dt.Even if apply to relax the di/dt risen, the body diode of common hyperconjugation VDMOS device also can lose efficacy sometimes.If the reverse recovery characteristic of body diode is poor, so will increase the turn-on consumption of MOSFET, therefore, the MOSFET with the body diode that characteristic is good, durability is strong be needed for these application.
In hyperconjugation VDMOS device, due to the deviation of manufacturing process, the complete equipilibrium of N post and P post electric charge can not realize completely.The impact that the people such as PraveenM.Shenoy bring to device property for the charge unbalance of N post and P post has carried out careful discussion in document " Analysisoftheeffectofchargeimbalanceonthestaticanddynami ccharacteristicsofthesuperjunctionMOSFET ", as shown in Figure 1, the electric charge complete equipilibrium (Q of three kinds of situation N posts and P post is analyzed altogether
p=Q
n), P post charge number is less than N post charge number (Q
p<Q
n) and P post charge number more than N post charge number (Q
p>Q
n).At Q
p=Q
nwhen charge balance, peak electric field is the position being about junction depth half at PN post knot, and most of electric current directly flows to the contact site in PBODY district, and remaining electric current is at N
+flow through below source electrode.For Q
p<Q
nwhen, peak value electric field is at the P trap top of knot, and most of electric current is at N
+flow through below source region.Big current below source electrode can cause the unlatching of parasitic NPN transistor, and the electric current under highfield and source electrode can cause local overheating in this area, along with the rising of temperature, and R
bincrease and V
bEreduction can accelerate further this parasitic bipolar transistor open problem, therefore, during the Reverse recovery applying big current or high di/dt, Q
p<Q
nsituation more easily make parasitic bipolar transistor open and then lost efficacy.Work as Q
p>Q
n, peak value electric field is in the bottom of PN post knot, and whole electric current flows directly into the metal electrode contact zone, source in Pbody district.At N
+do not have electric current to flow through below source region, focus is in far place, distance sources polar region, P column bottom.Therefore this design makes parasitic bipolar transistor least influenced, and durability when Reverse recovery is also much better, but, excessive (charge number of P post is more than the charge number 10% of N post) Q of this design
pconduction resistance increase and puncture voltage are declined significantly.
Summary of the invention
The invention provides a kind of hyperconjugation VDMOS and the preparation method that optimize body diode reverse recovery characteristics, parasitic bipolar NPN transistor can be avoided to be subject to the impact of body diode reverse restoring current, and the durability thus when Reverse recovery is very strong.
For solving above-mentioned technical problem, the technical scheme that the present invention takes: a kind of hyperconjugation VDMOS optimizing body diode reverse recovery characteristics, comprise P post and be positioned at the Pbody district of P column top, its special feature is: the sidewall on described P post top is provided with oxide layer.
Described oxidated layer thickness is 50 ~ 200nm, and extends to 1/3 ~ 1/2 of P post by bottom, Pbody district.
Described oxide layer is silicon dioxide layer.
The forming process of described oxide layer comprises the following steps:
Step one, utilize epitaxy technique, at N
+the N-type epitaxy layer of extension one deck 30 ~ 50 μm on substrate;
Step 2, in N-type epitaxy layer deposit Si
3n
4protective layer, and utilize P post mask blank to Si
3n
4protective layer etches;
Step 3, utilize P post mask blank mask, carry out deep etching in N-type epitaxy layer, then etching is the deep trouth of 25 ~ 45 μm deeply;
Step 4, in deep trouth epitaxial growth go out P post, i.e. P type epitaxial loayer, its thickness is 15 ~ 25 μm, and wherein the doping content of P post is 1 × 10
15~ 5 × 10
15cm
-3;
Step 5, at 1000 ~ 1200 DEG C of temperature dry-oxygen oxidation 60 ~ 120 minutes, grow the thick oxide layer of 50 ~ 200nm at the upper surface place of deep trouth sidewall and P type epitaxial loayer;
Step 6, use dry etching, etch away the oxide layer of P post surface in deep trouth;
Step 7, in deep trouth epitaxial growth P post, make P capital end differ 5 μm with the tip height of N-type epitaxy layer, wherein the doping content of P post is identical with step 4;
Step 8, adopt dry etching, make deposit Si in 5 μm of dark oxide layers and N-type epitaxy layer topmost
3n
4protective layer etches away completely;
Step 9, in deep trouth 5 μm, epitaxial growth P post, wherein the doping content of P post is identical with step 4, and P post is concordant with N-type epitaxy layer upper surface.
Compared with prior art, beneficial effect of the present invention:
The P post sidewall of hyperconjugation VDMOS of the present invention has silicon dioxide blocking layer, between body diode reverse convalescence, effectively prevent reverse recovery current by P post top, make all reverse recovery currents by the bottom of P post and run through the contact zone that P post flows directly into Pbody district, the component failure that the unlatching avoiding parasitic bipolar NPN transistor causes; The P post of hyperconjugation VDMOS and N post charge balance are subject to the fluctuation of technique, occur that P post amount of charge is greater than N post and Q
p<Q
ntime, due to the prevention of sidewall thin oxide layer, reverse recovery current still must run through by the bottom of P post the contact zone that P post flows directly into Pbody district, thus improves stability and the yield of devices of technique; Structure of the present invention reduces the reverse recovery time of body diode significantly, and makes reverse recovery current peak I rrm reduce by 10%; The deep etching of the compatible existing superjunction of the present invention and deep trouth epitaxy technique, do not increase manufacture technics cost while lifting body diode reverse recovery ability.
Accompanying drawing explanation
Fig. 1 is the structure of conventional hyperconjugation VDMOS and parasitic triode and body diode equivalent structure schematic diagram;
Fig. 2 is a kind of cross-sectional view optimizing the hyperconjugation VDMOS of body diode reverse recovery characteristics of the present invention;
Fig. 3 (a) ~ 3 (m) is that a kind of technique optimizing the hyperconjugation VDMOS of body diode reverse recovery characteristics with sidewall oxidation Rotating fields makes schematic diagram;
Fig. 4 of the present inventionly a kind ofly optimizes the hyperconjugation VDMOS of body diode reverse recovery characteristics and the simulated effect figure of conventional hyperconjugation VDMOS.
Wherein, 1, N
+substrate, 2, N-type epitaxy layer, 3, P post, 4, Pbody district, 5, N
+source region, 6, gate oxide, 7, polygate electrodes, 8, BPSG dielectric layer, 9, source metal electrode, 10, oxide layer, 11, Si
3n
4protective layer.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
See Fig. 2, a kind of hyperconjugation VDMOS optimizing body diode reverse recovery characteristics, comprise P post 3 and be positioned at the Pbody district 4 at P post 3 top, the sidewall on described P post 3 top is provided with silicon dioxide oxide layer.
Described silicon dioxide oxidated layer thickness is 50 ~ 200nm, and extends to 1/3 ~ 1/2 of P post by bottom, Pbody district 4.
The preparation method of the hyperconjugation VDMOS of above-mentioned optimization body diode reverse recovery characteristics, the forming process of silicon dioxide oxide layer comprises the following steps:
Step one, utilize epitaxy technique, at N
+the N-type epitaxy layer 2 of extension one deck 30 ~ 50 μm on substrate 1;
Step 2, in N-type epitaxy layer 2 deposit Si
3n
4protective layer 11, and utilize P post mask blank to Si
3n
4protective layer 11 etches;
Step 3, utilize P post mask blank mask, carry out deep etching in N-type epitaxy layer 2, then etching is the deep trouth of 25 ~ 45 μm deeply;
Step 4, in deep trouth epitaxial growth go out P post 3, i.e. P type epitaxial loayer, its degree of depth is 15 ~ 25 μm, and wherein the doping content of P post 3 is 1 × 10
15~ 5 × 10
15cm
-3;
Step 5, at 1000 ~ 1200 DEG C of temperature dry-oxygen oxidation 60 ~ 120 minutes, grow the thick oxide layer of 50 ~ 200nm 10 at the upper surface place of deep trouth sidewall and P type epitaxial loayer;
Step 6, use dry etching, etch away the oxide layer of P post 3 surface in deep trouth;
Step 7, in deep trouth epitaxial growth P post, make P post 3 top differ 5 μm with the tip height of N-type epitaxy layer 2, wherein the doping content of P post 3 is identical with step 4;
Step 8, adopt dry etching, make deposit Si in 5 μm of dark oxide layers and N-type epitaxy layer 2 topmost
3n
4protective layer 11 etches away completely;
Step 9, in deep trouth 35 μm, epitaxial growth P post, wherein the doping content of P post 3 is identical with step 4, and P post 3 is concordant with N-type epitaxy layer 2 upper surface;
Principle of the present invention is: hyperconjugation VDMOS has a kind of P post sidewall being used for optimizing body diode reverse recovery characteristics and has silicon dioxide oxide layer, between body diode reverse convalescence, this sidewall silicon dioxide layer prevents reverse recovery current by P post top effectively, avoid the impact that parasitic bipolar NPN transistor is subject to body diode reverse restoring current, thus the durability when Reverse recovery is very strong, thus inhibits the unlatching of the emitter junction of parasitic BJT dramatically; The compatible existing deep etching of the present invention and deep trouth epitaxy technique, do not increase manufacture technics cost while lifting body diode reverse recovery ability; Sidewall oxide of the present invention can use location oxidation of silicon process, is not having Si
3n
4the P post sidewall growth silicon dioxide layer of protection.
See Fig. 1, in the structure of conventional hyperconjugation VDMOS this expropriation of land parasitism bipolar transistor NPN structure and body diode structure, open for avoiding this parasitic NPN transistor, between body diode reverse convalescence, the reverse recovery current flowing through P post or body diode top must be reduced, thus reduce parasitic NPN pipe base resistance R
bthe pressure drop at two ends make it open.
Embodiment:
One, backing material prepares, and employing resistivity is the N of 0.001 Ω cm
+zone melting single-crystal silicon substrate 1, its crystal orientation is <100>;
Two, at N
+substrate Epitaxial growth 45 μm of resistivity are the N-type epitaxy layer of 4 Ω cm, as N post layer, as shown in Fig. 3 (a);
Three, deposit Si
3n
4protective layer, and utilize P post mask blank to Si
3n
4protective layer etches;
Four, utilize P post mask blank mask, going out N-type epitaxy layer deep etching is the deep trouth of 40 μm deeply, as shown in Fig. 3 (b);
Five, 20 μm, epitaxial growth P post in deep trouth, wherein the doping content of P post is 3.2 × 10
15cm
-3, as shown in Fig. 3 (c);
Six, dry oxide growth 90 minutes at 1100 DEG C of temperature, grows the thick oxide layer of 100nm, as shown in Fig. 3 (d) at the upper surface place of deep trouth sidewall and P type epitaxial loayer;
Seven, use dry etching, the oxide layer of P post upper surface in deep trouth is etched away, completely as shown in Fig. 3 (e)
Eight, 15 μm, epitaxial growth P post in deep trouth, wherein the doping content of P post is 3.2 × 10
15cm
-3, as shown in Fig. 3 (f);
Nine, dry etching is adopted, the oxide layer making 5 μm, the top dark and Si
3n
4protective layer etches away completely, as shown in Fig. 3 (g);
Ten, 5 μm, epitaxial growth P post in deep trouth, wherein the doping content of P post is 3.2 × 10
15cm
-3, P post is concordant with N post upper surface, as shown in Fig. 3 (h);
11, the energy injection dosage adopting 120KeV is 5.2 × 10
13cm
-2boron ion, and knot forms Pbody district 4, as shown in Fig. 3 (i) in 120 minutes under the high temperature of 1000 DEG C;
12, the gate oxide 6 that 90 minutes dry oxide growth 100nm are thick at 1100 DEG C of temperature, the polysilicon that deposit 400nm is thick afterwards, and use dry etching polysilicon to form polygate electrodes 7, as shown in Fig. 3 (j);
13, the energy injection dosage adopting 80KeV is 3 × 10
15cm
-2arsenic ion, and knot 30 minutes forms N at the temperature of 900 DEG C
+source region 5, as shown in Fig. 3 (k);
14, the bpsg layer 8 that deposit 2 μm is thick, refluxes 30 minutes under 950 DEG C of nitrogen atmospheres, and etching forms contact hole, as shown in Fig. 3 (l);
At upper surface deposit one deck aluminium of whole device, and etch aluminium formation source electrode 9, passivation, back face metalization forms drain electrode, as shown in Fig. 3 (m).
Claims (1)
1. optimize a hyperconjugation VDMOS for body diode reverse recovery characteristics, comprise P post (3) and be positioned at the Pbody district (4) at P post (3) top, it is characterized in that: the sidewall on described P post (3) top is provided with oxide layer (10); Described oxide layer (10) thickness is 50 ~ 200nm, and extends to 1/3 ~ 1/2 of P post (3) by Pbody district (4) bottom; Described oxide layer is silicon dioxide layer;
The forming process of described oxide layer comprises the following steps:
Step one, utilize epitaxy technique, at N
+the N-type epitaxy layer (2) of the upper extension one deck 30 ~ 50 μm of substrate (1);
Step 2, at the upper deposit Si of N-type epitaxy layer (2)
3n
4protective layer (11), and utilize P post mask blank to Si
3n
4protective layer (11) etches;
Step 3, utilize P post mask blank mask, carry out deep etching in N-type epitaxy layer (2), then etching is the deep trouth of 25 ~ 45 μm deeply;
Step 4, in deep trouth epitaxial growth go out P post (3), i.e. P type epitaxial loayer, its thickness is 15 ~ 25 μm, and wherein the doping content of P post (3) is 1 × 10
15~ 5 × 10
15cm
-3;
Step 5, at 1000 ~ 1200 DEG C of temperature dry-oxygen oxidation 60 ~ 120 minutes, grow the thick oxide layer of 50 ~ 200nm (10) at the upper surface place of deep trouth sidewall and P type epitaxial loayer;
Step 6, use dry etching, etch away the oxide layer (10) of P post (3) surface in deep trouth;
Step 7, in deep trouth epitaxial growth P post, make P post (3) top differ 5 μm with the tip height of N-type epitaxy layer (2), wherein the doping content of P post (3) is identical with step 4;
Step 8, employing dry etching, the oxide layer making 5 μm, the top dark and the upper deposit Si of N-type epitaxy layer (2)
3n
4protective layer (11) etches away completely;
Step 9, in deep trouth (3) 5 μm, epitaxial growth P post, wherein the doping content of P post (3) is identical with step 4, and P post (3) is concordant with N-type epitaxy layer (2) upper surface.
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| CN110660658B (en) * | 2018-06-28 | 2022-02-18 | 上海先进半导体制造有限公司 | VDMOS and manufacturing method thereof |
| CN109860301B (en) * | 2019-01-21 | 2020-06-30 | 东南大学 | Low reverse recovery charge SJ-VDMOS device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101950759A (en) * | 2010-08-27 | 2011-01-19 | 电子科技大学 | Super Junction VDMOS device |
| CN102169902A (en) * | 2010-03-19 | 2011-08-31 | 成都芯源系统有限公司 | Deep groove and deep injection type super junction device |
| CN202616236U (en) * | 2012-04-06 | 2012-12-19 | 东南大学 | Super junction VDMOS with P-type buried layer |
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| JP3634848B2 (en) * | 2003-01-07 | 2005-03-30 | 株式会社東芝 | Power semiconductor device |
| GB0407363D0 (en) * | 2004-03-31 | 2004-05-05 | Koninkl Philips Electronics Nv | Trench semiconductor device and method of manufacturing it |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169902A (en) * | 2010-03-19 | 2011-08-31 | 成都芯源系统有限公司 | Deep groove and deep injection type super junction device |
| CN101950759A (en) * | 2010-08-27 | 2011-01-19 | 电子科技大学 | Super Junction VDMOS device |
| CN202616236U (en) * | 2012-04-06 | 2012-12-19 | 东南大学 | Super junction VDMOS with P-type buried layer |
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