CN110660658B - VDMOS and manufacturing method thereof - Google Patents

VDMOS and manufacturing method thereof Download PDF

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CN110660658B
CN110660658B CN201810683880.5A CN201810683880A CN110660658B CN 110660658 B CN110660658 B CN 110660658B CN 201810683880 A CN201810683880 A CN 201810683880A CN 110660658 B CN110660658 B CN 110660658B
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doped region
vdmos
region
type
target
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CN110660658A (en
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王学良
刘建华
袁志巧
闵亚能
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SHANGHAI ADVANCED SEMICONDUCTO
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SHANGHAI ADVANCED SEMICONDUCTO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The invention discloses a VDMOS and a manufacturing method thereof, wherein the VDMOS comprises a built-in freewheeling diode, the freewheeling diode comprises a p-type doped region and an n-type doped region which are adjacent, a semiconductor substrate is provided with a first main surface and a second main surface, the first main surface is provided with a first target doped region, the second main surface is provided with a second target doped region, the first target doped region is a region for manufacturing the p-type doped region, and the second target doped region is a region for manufacturing the n-type doped region, the manufacturing method comprises the following steps: doping p-type impurity ions into the first target region to form a p-type doped region; hydrogen ions are implanted into the second target region to form an n-type doped region and recombination centers for reducing the critical saturation voltage of the freewheeling diode and accelerating reverse recovery time. The invention adopts the hydrogen ion implantation process to form the recombination center in the n-type doped layer, can accelerate the reverse recovery speed of the built-in freewheeling diode and improve the performance.

Description

VDMOS and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices and manufacturing processes, and particularly relates to a vertical metal-insulator-semiconductor (VDMOS) transistor and a manufacturing method thereof.
Background
The VDMOS is an ideal power device no matter in switch application or linear application, and is mainly applied to motor speed regulation, inverters, uninterruptible power supplies, electronic switches, high-fidelity acoustics, automobile electrical appliances, electronic ballasts and the like. The VDMOS can be classified into a planar VDMOS and a trench VDMOS.
In some VDMOS, a freewheeling diode (wheeldiode) is built in. Fig. 1 shows a semiconductor device structure including a trench VDMOS in which a freewheel diode is built, in which an equivalent circuit of the freewheel diode D is shown by a dotted line. Referring to fig. 1, the trench VDMOS includes a first n-type heavily doped layer 104, an n-type doped layer 102, an n-type lightly doped layer 101, a second p-type doped layer 108, a third p-type doped layer 114, a third n-type heavily doped layer 109, a fourth n-type heavily doped layer 112, a fifth n-type heavily doped layer 111, a sixth n-type heavily doped layer 110, a gate oxide layer 106, a gate 107, and a metal layer Source (Source)113, wherein the n-type doped layer 102 and the first n-type heavily doped layer 104 are connected in parallel to form a drain (drain). The second p-type doped layer 108, the n-type lightly doped layer 101, and the n-type doped layer 102 constitute a built-in free wheel diode D. The n-type doped layer 102 is an n-type region of the freewheeling diode D.
In the process of manufacturing the n-type region of the freewheel diode, it is necessary to perform ion implantation in the substrate to form an n-type doped layer. In the prior art, a phosphorus injection push-pull technology is often adopted in the process of performing ion implantation in the substrate to form the n-type region of the freewheeling diode. Specifically, referring to fig. 1, phosphorus ions are implanted into a semiconductor substrate at an appropriate concentration to form an n-type doped layer in a target region of the semiconductor substrate, the n-type doped layer serving as an n-type region of a flywheel diode built in the VDMOS. However, the freewheeling diode obtained by the method has a slow reverse recovery speed, which results in poor performance of the VDMOS.
Disclosure of Invention
The invention provides a VDMOS and a manufacturing method thereof, aiming at overcoming the defect that the performance of the VDMOS is poor due to the fact that the reverse recovery speed of a freewheeling diode in the VDMOS is slow in the prior art.
The invention solves the technical problems through the following technical scheme:
the invention provides a VDMOS manufacturing method, wherein the VDMOS comprises a built-in freewheeling diode, the freewheeling diode comprises a p-type doped region and an n-type doped region which are adjacent, the VDMOS is manufactured on a semiconductor substrate, the semiconductor substrate is provided with a first main surface and a second main surface, the first main surface is provided with a first target doped region, the second main surface is provided with a second target doped region, the first target doped region is adjacent to the second target doped region, the first target doped region is a region for manufacturing the p-type doped region, the second target doped region is a region for manufacturing the n-type doped region, and the VDMOS manufacturing method comprises the following steps:
doping p-type impurity ions into the first target region to form the p-type doped region;
and implanting hydrogen ions into the second target region to form the n-type doped region and recombination centers, wherein the recombination centers are used for reducing the critical saturation voltage of the free-wheeling diode and accelerating the reverse recovery time of the free-wheeling diode.
Preferably, before the step of implanting hydrogen ions into the second target region to form the n-type doped region and recombination centers, the method for manufacturing the VDMOS further comprises the steps of:
arranging a mask on the surface of the semiconductor substrate, wherein the mask comprises a blocking area and a transmission area, and the blocking area is used for blocking the hydrogen ions from being implanted into the semiconductor substrate; the transmission area is used for hydrogen ions to pass through so as to implant the semiconductor substrate.
Preferably, after the step of implanting hydrogen ions into the second target region to form the n-type doped region and recombination centers, the method for manufacturing the VDMOS further comprises the steps of:
and carrying out electron irradiation on the n-type doped region of the freewheeling diode.
Preferably, in the process of implanting hydrogen ions into the second target region to form the n-type doped region and the recombination centers, the n-type doped region of the freewheel diode is annealed to form the recombination centers in the n-type doped region of the freewheel diode.
Preferably, the annealing step adopts furnace tube annealing, the annealing temperature is 200-400 ℃, and the annealing time is 1-5 hours.
Preferably, the mask comprises a polyimide resin mask, or an aluminum mask, or a silicon nitride mask.
Preferably, the mask has a thickness of 2-100 microns.
Preferably, the annealing step uses laser annealing.
Preferably, the p-type impurity ions include aluminum ions or gallium ions or boron ions.
The invention also provides a VDMOS which is manufactured by the manufacturing method of the VDMOS.
The positive progress effects of the invention are as follows: in the VDMOS and the manufacturing method thereof, in the step of manufacturing the n-type region of the freewheel diode of the VDMOS, a hydrogen ion implantation process is adopted to replace a phosphorus ion implantation process in the prior art, and then annealing activation is carried out, so that hydrogen ions form a recombination center in the n-type doped layer, and the recombination center can simultaneously reduce the critical saturation voltage of the freewheel diode and accelerate the reverse recovery time of the freewheel diode, thereby shortening the reverse recovery time and improving the performance of the VDMOS.
Drawings
Fig. 1 is a schematic structural diagram of a conventional trench VDMOS in the prior art.
Fig. 2 is a flow chart of a method for manufacturing a VDMOS according to a preferred embodiment of the invention.
Fig. 3 is a schematic structural diagram of a trench VDMOS manufactured based on the method for manufacturing the VDMOS of fig. 2.
Fig. 4 is a schematic structural diagram of a planar VDMOS manufactured based on the method for manufacturing the VDMOS of fig. 2.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
The present embodiment provides a method for manufacturing a VDMOS, which is used for manufacturing a VDMOS including a built-in freewheeling diode, the freewheeling diode including a p-type doped region and an n-type doped region that are adjacent to each other, the VDMOS being manufactured on a semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface, the first main surface being provided with a first target doped region, the second main surface being provided with a second target doped region, the first target doped region being adjacent to the second target doped region, the first target doped region being a region for manufacturing the p-type doped region, the second target doped region being a region for manufacturing the n-type doped region, as shown in fig. 2, the method for manufacturing a VDMOS includes the following steps:
step S401, setting a mask on the surface of a semiconductor substrate;
step S402, doping p-type impurity ions into the first target region to form a p-type doped region;
step S403, implanting hydrogen ions into the second target region to form an n-type doped region and a recombination center;
wherein the recombination center is used for reducing the critical saturation voltage of the free wheel diode and accelerating the reverse recovery time of the free wheel diode. Specifically, the n-type doped region of the freewheel diode is annealed to form the recombination center within the n-type doped region of the freewheel diode.
And S404, performing electron irradiation on the n-type doped region of the freewheeling diode.
In step S401, the mask includes a blocking region for blocking impurity ions from being implanted into the semiconductor substrate and a transmissive region; the transmission region is used for impurity ions to pass through so as to be implanted into the semiconductor substrate.
The mask is made of polyimide resin material, aluminum material or silicon nitride material. The polyimide resin material, or the aluminum material, or the silicon nitride material is commercially available. According to experimental data, the blocking efficiency of the aluminum material mask with a thickness of 1 μm during hydrogen ion implantation is 1 μm, that is, assuming that the aluminum material mask has a thickness of 5 μm, when hydrogen ion implantation is performed and hydrogen ions are implanted into a region 5 μm below the transmission region, no hydrogen ion implantation is performed below the blocking region, and all hydrogen ions are blocked. According to the experimental data, the blocking efficiency of a 1 micron thick polyimide resin mask is 0.7 micron. The polyimide resin mask preferably has a thickness of 2-100 micrometers, and the aluminum material mask preferably has a thickness of 2-100 micrometers. In the prior art, a silicon dioxide mask is often adopted, and due to the factors of tension and stress, when the thickness of the silicon dioxide mask reaches a certain value, warping is easy to occur, and the reliability of the VDMOS is affected. Therefore, the silicon dioxide mask cannot achieve a large thickness. The polyimide resin mask and the aluminum material mask can reach larger thicknesses, the warping still cannot occur, and the reliability of the VDMOS can be guaranteed.
In the manufacturing method of the VDMOS, a hydrogen ion implantation process is adopted to replace the phosphorus ion implantation process in the prior art in the process of manufacturing the n-type region of the freewheel diode, a recombination center is formed in the n-type region of the freewheel diode while the n-type region of the freewheel diode is formed, and the recombination center can simultaneously reduce the critical saturation voltage of the freewheel diode and accelerate the reverse recovery time of the freewheel diode, so that the reverse recovery time of the VDMOS is shortened, and the performance of the VDMOS is improved.
In the prior art, the p-type doped region of the freewheel diode is doped with boron ions, but the formed freewheel diode is a abrupt junction, and in order to make the freewheel diode a gradual junction, in step S402, the p-type impurity ions may be selected from aluminum ions or gallium ions. The first target region is doped with aluminum ions or gallium ions, and implantation, evaporation, sputtering, soaking and other processes can be adopted. Because the diffusion coefficients of aluminum ions and gallium ions are larger, the freewheeling diode formed by the p-type doped region and the n-type doped region is a gradual change junction, so that the reverse breakdown voltage is higher, and the VDMOS is more stable.
In order to obtain a better ion implantation effect, after step S403, step S404 of performing electron irradiation on the n-type doped region of the freewheeling diode is further performed.
In this embodiment, the n-type doped region of the freewheeling diode is annealed to form a recombination center within the n-type doped region of the freewheeling diode. The annealing step adopts a furnace tube for annealing, the annealing temperature is 200-400 ℃, and the annealing time is 1-5 hours. In other alternative embodiments, the annealing step employs laser annealing.
The present embodiment further provides a trench VDMOS as shown in fig. 3, which is manufactured based on the method for manufacturing a VDMOS as shown in fig. 2, and is specifically used for manufacturing an n-type region of a freewheeling diode embedded in the trench VDMOS. The trench VDMOS comprises a first n-type heavily doped layer 104, an n-type doped layer 202, an n-type lightly doped layer 101, a second p-type doped layer 108, a third p-type doped layer 114, a third n-type heavily doped layer 109, a fourth n-type heavily doped layer 112, a fifth n-type heavily doped layer 111, a sixth n-type heavily doped layer 110, a gate oxide layer 106, a gate 107, a metal layer source 113, and the n-type doped layer 202 and the first n-type heavily doped layer 104 which are connected in parallel to form a drain. The second p-type doped layer 108, the n-type lightly doped layer 101, and the n-type doped layer 202 constitute a built-in freewheeling diode D'. The n-type doped layer 202 serves as an n-type region of a freewheeling diode built in the trench VDMOS. The trench VDMOS is manufactured by the method for manufacturing a VDMOS according to this embodiment, and the detailed process is not described again. In the step of manufacturing the n-type region of the freewheeling diode of the trench VDMOS, a hydrogen ion implantation process is adopted to replace a phosphorus ion implantation process in the prior art, and then annealing activation is carried out, so that hydrogen ions form a recombination center in the n-type doped layer, the reverse recovery speed of the built-in freewheeling diode can be accelerated, and the reverse recovery time of the built-in freewheeling diode can be shortened.
The present embodiment further provides a planar VDMOS as shown in fig. 4, which is manufactured based on the manufacturing method of the VDMOS shown in fig. 2, and is specifically used for manufacturing an n-type region of a freewheeling diode embedded in the planar VDMOS. The planar VDMOS comprises a drain 503, a first n-type heavily doped layer 104, an n-type doped layer 302, an n-type drift region 505, a p-well 506, a second n-type heavily doped layer 507, a source 501, a gate oxide layer 504 and a gate 508. The p-well 506, the n-type drift region 505, and the n-doped layer 302 form a freewheeling diode D1, the equivalent circuit of which is shown in fig. 4 with dashed lines as freewheeling diode D1, wherein the n-doped layer 302 serves as the n-type region of the freewheeling diode built into the planar VDMOS. The planar VDMOS is manufactured by the method for manufacturing a VDMOS of this embodiment, and the specific flow is not described again. In the step of manufacturing the n-type region of the freewheeling diode of the planar VDMOS, a hydrogen ion implantation process is adopted to replace a phosphorus ion implantation process in the prior art, and then annealing activation is carried out, so that hydrogen ions form a recombination center in the n-type doped layer, the reverse recovery speed of the built-in freewheeling diode can be accelerated, and the reverse recovery time of the built-in freewheeling diode can be shortened.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (10)

1. A method for manufacturing a VDMOS, the VDMOS including a built-in freewheeling diode, the freewheeling diode including a p-type doped region and an n-type doped region that are adjacent to each other, the VDMOS being manufactured on a semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface, the first main surface being provided with a first target doped region, the second main surface being provided with a second target doped region, the first target doped region being adjacent to the second target doped region, the first target doped region being a region for manufacturing the p-type doped region, the second target doped region being a region for manufacturing the n-type doped region, the method comprising: doping p-type impurity ions into the first target doping region to form the p-type doping region; implanting hydrogen ions into the second target doped region to form the n-type doped region and a recombination center for reducing a critical saturation voltage of the freewheel diode and accelerating a reverse recovery time of the freewheel diode;
wherein the n-type doped region is an n-type region of the freewheeling diode and the recombination center is formed in the n-type region of the freewheeling diode.
2. The method of fabricating the VDMOS of claim 1, wherein prior to the step of implanting hydrogen ions into the second target doped region to form the n-type doped region and recombination centers, the method of fabricating the VDMOS further comprises the steps of: arranging a mask on the surface of the semiconductor substrate, wherein the mask comprises a blocking area and a transmission area, and the blocking area is used for blocking the hydrogen ions from being implanted into the semiconductor substrate; the transmission area is used for hydrogen ions to pass through so as to implant the semiconductor substrate.
3. The method of fabricating the VDMOS of claim 1, wherein after the step of implanting hydrogen ions into the second target doping region to form the n-type doping region and recombination centers, the method of fabricating the VDMOS further comprises the steps of: and carrying out electron irradiation on the n-type doped region of the freewheeling diode.
4. The method of fabricating the VDMOS of claim 1, wherein during the implanting of hydrogen ions into the second target doped region to form the n-type doped region and recombination centers, the n-type doped region of the freewheel diode is annealed to form the recombination centers within the n-type doped region of the freewheel diode.
5. The VDMOS manufacturing method of claim 4, wherein the annealing step employs furnace annealing at 200-400 ℃ for 1-5 hours.
6. The method for manufacturing the VDMOS of claim 2, wherein the mask comprises a polyimide resin mask, or an aluminum mask, or a silicon nitride mask.
7. The method for fabricating the VDMOS of claim 6, wherein the thickness of the mask is 2 to 100 μm.
8. The method for fabricating the VDMOS of claim 4, wherein the annealing step employs laser annealing.
9. The method for fabricating the VDMOS according to claim 1, wherein the p-type impurity ions include aluminum ions or gallium ions or boron ions.
10. A VDMOS manufactured by the method for manufacturing a VDMOS according to any one of claims 1 to 9.
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